| /qemu/target/arm/ |
| H A D | cortex-regs.c | 40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | helper.c | 716 .resetvalue = 0 },
719 .resetvalue = 0 },
723 .resetvalue = 0 },
2215 .resetvalue = 0,
2221 .resetvalue = 0,
2228 .resetvalue = 0,
2434 .resetvalue = 0,
3260 .resetvalue = 0,
3287 .resetvalue = 0,
3305 .resetvalue = 0,
[all …]
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| H A D | debug_helper.c | 954 .type = ARM_CP_CONST, .resetvalue = 0 },
965 .resetvalue = 0 },
973 .type = ARM_CP_CONST, .resetvalue = 0 },
983 .type = ARM_CP_CONST, .resetvalue = 0 },
987 .type = ARM_CP_CONST, .resetvalue = 0 },
992 .type = ARM_CP_CONST, .resetvalue = 0 },
1002 .type = ARM_CP_CONST, .resetvalue = 0 },
1021 .access = PL1_R, .resetvalue = 10,
1084 .resetvalue = 0 },
1087 .resetvalue = 0 },
[all …]
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| H A D | cpregs.h | 895 uint64_t resetvalue; member
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| H A D | cpu.c | 196 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
198 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
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| /qemu/target/arm/tcg/ |
| H A D | cpu64.c | 482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
534 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
538 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
542 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
546 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
754 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
[all …]
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| H A D | cpu32.c | 200 .resetvalue = 0 in arm1026_initfn()
389 .access = PL1_RW, .resetvalue = 0,
392 .access = PL1_RW, .resetvalue = 0,
395 .access = PL1_RW, .resetvalue = 0,
401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
701 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
704 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
707 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
710 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
[all …]
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| H A D | translate.c | 3111 tmp64 = tcg_constant_i64(ri->resetvalue); in do_coproc_insn()
3131 tmp = tcg_constant_i32(ri->resetvalue); in do_coproc_insn()
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| H A D | translate-a64.c | 2547 tcg_gen_movi_i64(tcg_rt, ri->resetvalue); in handle_sys()
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| /qemu/hw/arm/ |
| H A D | pxa2xx.c | 366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
375 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
377 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
379 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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| /qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 2585 .resetvalue = 0x7,
2611 .resetvalue = 0xf,
2627 .resetvalue = 0xf,
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| /qemu/target/arm/hvf/ |
| H A D | hvf.c | 1252 *val = ri->resetvalue; in hvf_sysreg_read_cp()
|