/qemu/tests/unit/ |
H A D | test-mul64.c | 15 uint64_t rh, rl; member 43 uint64_t rl, rh; in test_u() local 44 mulu64(&rl, &rh, test_u_data[i].a, test_u_data[i].b); in test_u() 45 g_assert_cmpuint(rl, ==, test_u_data[i].rl); in test_u() 55 uint64_t rl, rh; in test_s() local 56 muls64(&rl, &rh, test_s_data[i].a, test_s_data[i].b); in test_s() 57 g_assert_cmpuint(rl, ==, test_s_data[i].rl); in test_s()
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/qemu/target/riscv/ |
H A D | m128_helper.c | 49 target_ulong rl, rh; in HELPER() local 53 rl = ul; in HELPER() 57 rl = int128_getlo(r); in HELPER() 62 return rl; in HELPER() 94 target_ulong rh, rl; in HELPER() local 98 rl = ul; in HELPER() 102 rl = int128_getlo(r); in HELPER() 107 return rl; in HELPER()
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H A D | insn32.decode | 53 &atomic aq rl rs2 rs1 rd 71 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 72 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
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H A D | translate.c | 423 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) in gen_set_gpr128() argument 427 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); in gen_set_gpr128()
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvm.c.inc | 50 static void gen_mul_i128(TCGv rl, TCGv rh, 58 tcg_gen_mulu2_tl(rl, rh, rs1l, rs2l); 71 static void gen_mulh_i128(TCGv rl, TCGv rh, 86 tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h); 87 tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h); 110 static void gen_mulhsu_i128(TCGv rl, TCGv rh, 121 tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h); 126 TCGv rl = tcg_temp_new(); 129 tcg_gen_mulu2_tl(rl, rh, arg1, arg2); 132 tcg_gen_and_tl(rl, rl, arg2); [all …]
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H A D | trans_rvi.c.inc | 89 static TCGCond gen_compare_i128(bool bz, TCGv rl, 100 tcg_gen_or_tl(rl, al, ah); 102 tcg_gen_xor_tl(rl, al, bl); 104 tcg_gen_or_tl(rl, rl, rh); 111 tcg_gen_mov_tl(rl, ah); 115 tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh); 116 tcg_gen_xor_tl(rl, rh, ah); 118 tcg_gen_and_tl(rl, rl, tmp); 119 tcg_gen_xor_tl(rl, rh, rl); 151 static void gen_setcond_i128(TCGv rl, TCGv rh, [all …]
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H A D | trans_rva.c.inc | 39 if (a->rl) { 85 TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
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/qemu/crypto/ |
H A D | clmul.c | 98 uint64_t rl = 0, rh = 0; in clmul_64_gen() local 102 rl = m; in clmul_64_gen() 107 rl ^= (m << i) & mask; in clmul_64_gen() 110 return int128_make128(rl, rh); in clmul_64_gen()
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/qemu/bsd-user/ |
H A D | main.c | 236 struct rlimit rl; in adjust_ssize() local 238 if (getrlimit(RLIMIT_STACK, &rl) != 0) { in adjust_ssize() 242 target_maxssiz = MIN(target_maxssiz, rl.rlim_max); in adjust_ssize() 243 target_dflssiz = MIN(MAX(target_dflssiz, rl.rlim_cur), target_maxssiz); in adjust_ssize() 245 rl.rlim_max = target_maxssiz; in adjust_ssize() 246 rl.rlim_cur = target_dflssiz; in adjust_ssize() 247 setrlimit(RLIMIT_STACK, &rl); in adjust_ssize()
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/qemu/util/ |
H A D | host-utils.c | 44 LL rl, rm, rn, rh, a0, b0; in mul64() local 50 rl.ll = (uint64_t)a0.l.low * b0.l.low; in mul64() 55 c = (uint64_t)rl.l.high + rm.l.low + rn.l.low; in mul64() 56 rl.l.high = c; in mul64() 62 *plow = rl.ll; in mul64()
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/qemu/tcg/ |
H A D | tcg-op.c | 1182 tcg_gen_mov_i32(rl, t); in tcg_gen_mulu2_i32() 1206 tcg_gen_mov_i32(rl, t); in tcg_gen_muls2_i32() 1221 tcg_gen_mov_i32(rl, t0); in tcg_gen_muls2_i32() 1249 tcg_gen_mov_i32(rl, t0); in tcg_gen_mulsu2_i32() 3018 tcg_gen_mov_i64(rl, t0); in tcg_gen_add2_i64() 3036 tcg_gen_mov_i64(rl, t0); in tcg_gen_sub2_i64() 3050 tcg_gen_mov_i64(rl, t); in tcg_gen_mulu2_i64() 3056 tcg_gen_mov_i64(rl, t0); in tcg_gen_mulu2_i64() 3069 tcg_gen_mov_i64(rl, t); in tcg_gen_muls2_i64() 3084 tcg_gen_mov_i64(rl, t0); in tcg_gen_muls2_i64() [all …]
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H A D | optimize.c | 1215 TCGArg rl, rh; in fold_addsub2() local 1244 rl = op->args[0]; in fold_addsub2() 1250 tcg_opt_gen_movi(ctx, op, rl, al); in fold_addsub2() 1944 TCGArg rl, rh; in fold_multiply2() local 1968 rl = op->args[0]; in fold_multiply2() 1974 tcg_opt_gen_movi(ctx, op, rl, l); in fold_multiply2()
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/qemu/include/tcg/ |
H A D | tcg-op-common.h | 134 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 136 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 138 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 139 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 140 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 237 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 239 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 241 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 242 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 243 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
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/qemu/include/qemu/ |
H A D | host-utils.h | 104 uint64_t rl, rh; in muldiv64_rounding() local 107 rl = (uint64_t)u.l.low * (uint64_t)b; in muldiv64_rounding() 109 rl += c - 1; in muldiv64_rounding() 112 rh += (rl >> 32); in muldiv64_rounding() 114 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; in muldiv64_rounding()
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/qemu/linux-user/ |
H A D | flatload.c | 148 static void old_reloc(struct lib_info *libinfo, uint32_t rl) in old_reloc() argument 157 offset = rl & 0x3fffffff; in old_reloc() 158 reloc_type = rl >> 30; in old_reloc()
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H A D | strace.c | 3968 struct target_rlimit64 *rl; in print_rlimit64() local 3970 rl = lock_user(VERIFY_READ, rlim_addr, sizeof(*rl), 1); in print_rlimit64() 3971 if (!rl) { in print_rlimit64() 3975 print_raw_param64("{rlim_cur=%" PRId64, tswap64(rl->rlim_cur), 0); in print_rlimit64() 3976 print_raw_param64("rlim_max=%" PRId64 "}", tswap64(rl->rlim_max), in print_rlimit64() 3978 unlock_user(rl, rlim_addr, 0); in print_rlimit64()
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/qemu/target/tricore/ |
H A D | translate.c | 240 gen_st_2regs_64(rh, rl, temp, ctx); in gen_offset_st_2regs() 249 tcg_gen_extr_i64_i32(rl, rh, temp); in gen_ld_2regs_64() 257 gen_ld_2regs_64(rh, rl, temp, ctx); in gen_offset_ld_2regs() 1091 tcg_gen_extr_i64_i32(rl, rh, t3); in gen_m16add64_q() 1117 tcg_gen_extr_i64_i32(rl, rh, t1); in gen_m16adds64_q() 1158 tcg_gen_extr_i64_i32(rl, rh, t4); in gen_madd64_q() 1195 tcg_gen_extr_i64_i32(rl, rh, r1); in gen_madds64_q() 1824 tcg_gen_extr_i64_i32(rl, rh, t3); in gen_m16sub64_q() 1850 tcg_gen_extr_i64_i32(rl, rh, t1); in gen_m16subs64_q() 1891 tcg_gen_extr_i64_i32(rl, rh, t4); in gen_msub64_q() [all …]
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/qemu/tcg/sparc64/ |
H A D | tcg-target.c.inc | 836 static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, 843 if (rl != ah && (bhconst || rl != bh)) { 844 tmp = rl; 849 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); 852 static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, 859 if (rl != ah && (bhconst || rl != bh)) { 860 tmp = rl; 901 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
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/qemu/disas/ |
H A D | riscv.h | 206 uint8_t rl; member
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 723 TCGReg rl, TCGReg rh, 745 } else if (bh != 0 || ah == rl) { 755 tcg_out_opc_imm(s, opc_addi, rl, al, -bl); 758 tcg_out_opc_reg(s, opc_sub, rl, al, bl); 763 tcg_out_opc_imm(s, opc_addi, rl, al, bl); 764 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); 773 tcg_out_opc_reg(s, opc_add, rl, al, al); 775 tcg_out_opc_reg(s, opc_add, rl, al, bl); 777 rl, (rl == bl ? al : bl));
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/qemu/tcg/mips/ |
H A D | tcg-target.c.inc | 826 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 844 } else if (bh != 0 || ah == rl) { 854 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 857 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 862 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 863 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 864 } else if (rl == al && rl == bl) { 866 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 868 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 869 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
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/qemu/fpu/ |
H A D | softfloat-parts.c.inc | 704 uint64_t dh, dl, rh, rl, sh, sl, uh, ul; /* 128-bit computation */ 844 mul64To128(u64, r64, &rh, &rl); 845 add128(rh, rl, rh, rl, &rh, &rl); 848 mul128To256(a->frac_hi, a->frac_lo, rh, rl, &sh, &sl, &discard, &discard); 849 mul128To256(sh, sl, rh, rl, &dh, &dl, &discard, &discard);
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/qemu/target/arm/ |
H A D | kvm.c | 802 struct kvm_reg_list rl; in kvm_arm_init_cpreg_list() local 807 rl.n = 0; in kvm_arm_init_cpreg_list() 808 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); in kvm_arm_init_cpreg_list() 812 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); in kvm_arm_init_cpreg_list() 813 rlp->n = rl.n; in kvm_arm_init_cpreg_list()
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_vec.c.inc | 364 rl = tcg_temp_new_i64(); 2138 TCGv_i64 rh, rl, arg1, arg2; 2146 rl = tcg_temp_new_i64(); 2802 rl = tcg_temp_new_i64(); 2815 tcg_gen_add2_i64(rl, rh, rl, rh, tl, th); 5247 TCGv_i64 rl, rh; 5260 rl = tcg_temp_new_i64(); 5268 set_vreg64(rl, a->vd, 0); 5305 TCGv_i64 rl, rh; 5319 rl = tcg_temp_new_i64(); [all …]
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 1594 static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, 1599 TCGReg orig_rl = rl; 1602 if (rl == ah || (!const_bh && rl == bh)) { 1603 rl = TCG_REG_TMP0; 1623 tcg_out_insn_3401(s, insn, ext, rl, al, bl); 1625 tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); 1641 tcg_out_mov(s, ext, orig_rl, rl);
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