1 /*
2 * MIPS SIMD Architecture (MSA) translation routines
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 *
11 * SPDX-License-Identifier: LGPL-2.1-or-later
12 */
13 #include "qemu/osdep.h"
14 #include "translate.h"
15 #include "fpu_helper.h"
16
17 static int elm_n(DisasContext *ctx, int x);
18 static int elm_df(DisasContext *ctx, int x);
19 static int bit_m(DisasContext *ctx, int x);
20 static int bit_df(DisasContext *ctx, int x);
21
plus_1(DisasContext * s,int x)22 static inline int plus_1(DisasContext *s, int x)
23 {
24 return x + 1;
25 }
26
plus_2(DisasContext * s,int x)27 static inline int plus_2(DisasContext *s, int x)
28 {
29 return x + 2;
30 }
31
32 /* Include the auto-generated decoder. */
33 #include "decode-msa.c.inc"
34
35 static const char msaregnames[][6] = {
36 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
37 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
38 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
39 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
40 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
41 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
42 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
43 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
44 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
45 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
46 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
47 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
48 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
49 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
50 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
51 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
52 };
53
54 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */
55 struct dfe {
56 int start;
57 int length;
58 uint32_t mask;
59 };
60
61 /*
62 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions).
63 * Returns the immediate value, or -1 if the format does not match.
64 */
df_extract_val(DisasContext * ctx,int x,const struct dfe * s)65 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s)
66 {
67 for (unsigned i = 0; i < 4; i++) {
68 if (extract32(x, s[i].start, s[i].length) == s[i].mask) {
69 return extract32(x, 0, s[i].start);
70 }
71 }
72 return -1;
73 }
74
75 /*
76 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions).
77 * Returns the DataField, or -1 if the format does not match.
78 */
df_extract_df(DisasContext * ctx,int x,const struct dfe * s)79 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s)
80 {
81 for (unsigned i = 0; i < 4; i++) {
82 if (extract32(x, s[i].start, s[i].length) == s[i].mask) {
83 return i;
84 }
85 }
86 return -1;
87 }
88
89 static const struct dfe df_elm[] = {
90 /* Table 3.26 ELM Instruction Format */
91 [DF_BYTE] = {4, 2, 0b00},
92 [DF_HALF] = {3, 3, 0b100},
93 [DF_WORD] = {2, 4, 0b1100},
94 [DF_DOUBLE] = {1, 5, 0b11100}
95 };
96
elm_n(DisasContext * ctx,int x)97 static int elm_n(DisasContext *ctx, int x)
98 {
99 return df_extract_val(ctx, x, df_elm);
100 }
101
elm_df(DisasContext * ctx,int x)102 static int elm_df(DisasContext *ctx, int x)
103 {
104 return df_extract_df(ctx, x, df_elm);
105 }
106
107 static const struct dfe df_bit[] = {
108 /* Table 3.28 BIT Instruction Format */
109 [DF_BYTE] = {3, 4, 0b1110},
110 [DF_HALF] = {4, 3, 0b110},
111 [DF_WORD] = {5, 2, 0b10},
112 [DF_DOUBLE] = {6, 1, 0b0}
113 };
114
bit_m(DisasContext * ctx,int x)115 static int bit_m(DisasContext *ctx, int x)
116 {
117 return df_extract_val(ctx, x, df_bit);
118 }
119
bit_df(DisasContext * ctx,int x)120 static int bit_df(DisasContext *ctx, int x)
121 {
122 return df_extract_df(ctx, x, df_bit);
123 }
124
125 static TCGv_i64 msa_wr_d[64];
126
msa_translate_init(void)127 void msa_translate_init(void)
128 {
129 int i;
130
131 for (i = 0; i < 32; i++) {
132 int off;
133
134 /*
135 * The MSA vector registers are mapped on the
136 * scalar floating-point unit (FPU) registers.
137 */
138 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
139 msa_wr_d[i * 2] = fpu_f64[i];
140
141 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
142 msa_wr_d[i * 2 + 1] =
143 tcg_global_mem_new_i64(tcg_env, off, msaregnames[i * 2 + 1]);
144 }
145 }
146
147 /*
148 * Check if MSA is enabled.
149 * This function is always called with MSA available.
150 * If MSA is disabled, raise an exception.
151 */
check_msa_enabled(DisasContext * ctx)152 static inline bool check_msa_enabled(DisasContext *ctx)
153 {
154 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
155 !(ctx->hflags & MIPS_HFLAG_F64))) {
156 gen_reserved_instruction(ctx);
157 return false;
158 }
159
160 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
161 generate_exception_end(ctx, EXCP_MSADIS);
162 return false;
163 }
164 return true;
165 }
166
167 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);
168 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32);
169 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
170 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
171
172 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \
173 static gen_helper_p##TYPE * const NAME##_tab[4] = { \
174 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \
175 }; \
176 TRANS(NAME, trans_func, NAME##_tab[a->df])
177
178 #define TRANS_DF_iv(NAME, trans_func, gen_func) \
179 TRANS_DF_x(iv, NAME, trans_func, gen_func)
180
181 #define TRANS_DF_ii(NAME, trans_func, gen_func) \
182 TRANS_DF_x(ii, NAME, trans_func, gen_func)
183
184 #define TRANS_DF_iii(NAME, trans_func, gen_func) \
185 TRANS_DF_x(iii, NAME, trans_func, gen_func)
186
187 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
188 static gen_helper_piii * const NAME##_tab[4] = { \
189 NULL, gen_func##_h, gen_func##_w, gen_func##_d \
190 }; \
191 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
192 { \
193 return trans_func(ctx, a, NAME##_tab[a->df]); \
194 }
195
gen_check_zero_element(TCGv tresult,uint8_t df,uint8_t wt,TCGCond cond)196 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
197 TCGCond cond)
198 {
199 /* generates tcg ops to check if any element is 0 */
200 /* Note this function only works with MSA_WRLEN = 128 */
201 uint64_t eval_zero_or_big = dup_const(df, 1);
202 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1);
203 TCGv_i64 t0 = tcg_temp_new_i64();
204 TCGv_i64 t1 = tcg_temp_new_i64();
205
206 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
207 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
208 tcg_gen_andi_i64(t0, t0, eval_big);
209 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big);
210 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]);
211 tcg_gen_andi_i64(t1, t1, eval_big);
212 tcg_gen_or_i64(t0, t0, t1);
213 /* if all bits are zero then all elements are not zero */
214 /* if some bit is non-zero then some element is zero */
215 tcg_gen_setcondi_i64(cond, t0, t0, 0);
216 tcg_gen_trunc_i64_tl(tresult, t0);
217 }
218
gen_msa_BxZ_V(DisasContext * ctx,int wt,int sa,TCGCond cond)219 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
220 {
221 TCGv_i64 t0;
222
223 if (!check_msa_enabled(ctx)) {
224 return true;
225 }
226
227 if (ctx->hflags & MIPS_HFLAG_BMASK) {
228 gen_reserved_instruction(ctx);
229 return true;
230 }
231 t0 = tcg_temp_new_i64();
232 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
233 tcg_gen_setcondi_i64(cond, t0, t0, 0);
234 tcg_gen_trunc_i64_tl(bcond, t0);
235
236 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
237
238 ctx->hflags |= MIPS_HFLAG_BC;
239 ctx->hflags |= MIPS_HFLAG_BDS32;
240
241 return true;
242 }
243
trans_BZ_V(DisasContext * ctx,arg_msa_bz * a)244 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
245 {
246 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
247 }
248
trans_BNZ_V(DisasContext * ctx,arg_msa_bz * a)249 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
250 {
251 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
252 }
253
gen_msa_BxZ(DisasContext * ctx,int df,int wt,int sa,bool if_not)254 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
255 {
256 if (!check_msa_enabled(ctx)) {
257 return true;
258 }
259
260 if (ctx->hflags & MIPS_HFLAG_BMASK) {
261 gen_reserved_instruction(ctx);
262 return true;
263 }
264
265 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
266
267 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
268 ctx->hflags |= MIPS_HFLAG_BC;
269 ctx->hflags |= MIPS_HFLAG_BDS32;
270
271 return true;
272 }
273
trans_BZ(DisasContext * ctx,arg_msa_bz * a)274 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
275 {
276 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
277 }
278
trans_BNZ(DisasContext * ctx,arg_msa_bz * a)279 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
280 {
281 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
282 }
283
trans_msa_i8(DisasContext * ctx,arg_msa_i * a,gen_helper_piii * gen_msa_i8)284 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a,
285 gen_helper_piii *gen_msa_i8)
286 {
287 if (!check_msa_enabled(ctx)) {
288 return true;
289 }
290
291 gen_msa_i8(tcg_env,
292 tcg_constant_i32(a->wd),
293 tcg_constant_i32(a->ws),
294 tcg_constant_i32(a->sa));
295
296 return true;
297 }
298
299 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b);
300 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b);
301 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b);
302 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b);
303 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b);
304 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b);
305 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b);
306
trans_SHF(DisasContext * ctx,arg_msa_i * a)307 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a)
308 {
309 if (a->df == DF_DOUBLE) {
310 return false;
311 }
312
313 if (!check_msa_enabled(ctx)) {
314 return true;
315 }
316
317 gen_helper_msa_shf_df(tcg_env,
318 tcg_constant_i32(a->df),
319 tcg_constant_i32(a->wd),
320 tcg_constant_i32(a->ws),
321 tcg_constant_i32(a->sa));
322
323 return true;
324 }
325
trans_msa_i5(DisasContext * ctx,arg_msa_i * a,gen_helper_piiii * gen_msa_i5)326 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a,
327 gen_helper_piiii *gen_msa_i5)
328 {
329 if (!check_msa_enabled(ctx)) {
330 return true;
331 }
332
333 gen_msa_i5(tcg_env,
334 tcg_constant_i32(a->df),
335 tcg_constant_i32(a->wd),
336 tcg_constant_i32(a->ws),
337 tcg_constant_i32(a->sa));
338
339 return true;
340 }
341
342 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df);
343 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df);
344 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df);
345 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df);
346 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df);
347 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df);
348 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df);
349 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df);
350 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df);
351 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df);
352 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df);
353
trans_LDI(DisasContext * ctx,arg_msa_ldi * a)354 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
355 {
356 if (!check_msa_enabled(ctx)) {
357 return true;
358 }
359
360 gen_helper_msa_ldi_df(tcg_env,
361 tcg_constant_i32(a->df),
362 tcg_constant_i32(a->wd),
363 tcg_constant_i32(a->sa));
364
365 return true;
366 }
367
trans_msa_bit(DisasContext * ctx,arg_msa_bit * a,gen_helper_piiii * gen_msa_bit)368 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
369 gen_helper_piiii *gen_msa_bit)
370 {
371 if (a->df < 0) {
372 return false;
373 }
374
375 if (!check_msa_enabled(ctx)) {
376 return true;
377 }
378
379 gen_msa_bit(tcg_env,
380 tcg_constant_i32(a->df),
381 tcg_constant_i32(a->wd),
382 tcg_constant_i32(a->ws),
383 tcg_constant_i32(a->m));
384
385 return true;
386 }
387
388 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df);
389 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df);
390 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df);
391 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df);
392 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df);
393 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df);
394 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df);
395 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df);
396 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_s_df);
397 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df);
398 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
399 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
400
trans_msa_3rf(DisasContext * ctx,arg_msa_r * a,gen_helper_piiii * gen_msa_3rf)401 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
402 gen_helper_piiii *gen_msa_3rf)
403 {
404 if (!check_msa_enabled(ctx)) {
405 return true;
406 }
407
408 gen_msa_3rf(tcg_env,
409 tcg_constant_i32(a->df),
410 tcg_constant_i32(a->wd),
411 tcg_constant_i32(a->ws),
412 tcg_constant_i32(a->wt));
413
414 return true;
415 }
416
trans_msa_3r(DisasContext * ctx,arg_msa_r * a,gen_helper_piii * gen_msa_3r)417 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
418 gen_helper_piii *gen_msa_3r)
419 {
420 if (!gen_msa_3r) {
421 return false;
422 }
423
424 if (!check_msa_enabled(ctx)) {
425 return true;
426 }
427
428 gen_msa_3r(tcg_env,
429 tcg_constant_i32(a->wd),
430 tcg_constant_i32(a->ws),
431 tcg_constant_i32(a->wt));
432
433 return true;
434 }
435
436 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v);
437 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v);
438 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v);
439 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v);
440 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v);
441 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v);
442 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v);
443
444 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll);
445 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra);
446 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl);
447 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr);
448 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset);
449 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg);
450 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
451 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
452
453 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv);
454 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv);
455 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s);
456 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u);
457 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s);
458 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u);
459 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a);
460 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a);
461
462 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq);
463 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s);
464 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u);
465 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s);
466 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u);
467
468 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a);
469 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a);
470 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s);
471 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u);
472 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s);
473 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u);
474 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s);
475 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u);
476
477 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s);
478 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u);
479 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u);
480 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s);
481 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s);
482 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u);
483
484 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv);
485 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv);
486 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv);
487 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s);
488 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u);
489 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s);
490 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u);
491
492 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
493 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
494 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
495 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u);
496 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s);
497 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u);
498
499 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df);
500 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df);
501 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev);
502 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod);
503 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl);
504 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr);
505 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev);
506 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod);
507
508 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df);
509 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar);
510 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr);
511 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s);
512 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u);
513 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s);
514 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u);
515
trans_MOVE_V(DisasContext * ctx,arg_msa_elm * a)516 static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
517 {
518 if (!check_msa_enabled(ctx)) {
519 return true;
520 }
521
522 gen_helper_msa_move_v(tcg_env,
523 tcg_constant_i32(a->wd),
524 tcg_constant_i32(a->ws));
525
526 return true;
527 }
528
trans_CTCMSA(DisasContext * ctx,arg_msa_elm * a)529 static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
530 {
531 TCGv telm;
532
533 if (!check_msa_enabled(ctx)) {
534 return true;
535 }
536
537 telm = tcg_temp_new();
538
539 gen_load_gpr(telm, a->ws);
540 gen_helper_msa_ctcmsa(tcg_env, telm, tcg_constant_i32(a->wd));
541
542 return true;
543 }
544
trans_CFCMSA(DisasContext * ctx,arg_msa_elm * a)545 static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
546 {
547 TCGv telm;
548
549 if (!check_msa_enabled(ctx)) {
550 return true;
551 }
552
553 telm = tcg_temp_new();
554
555 gen_helper_msa_cfcmsa(telm, tcg_env, tcg_constant_i32(a->ws));
556 gen_store_gpr(telm, a->wd);
557
558 return true;
559 }
560
trans_msa_elm(DisasContext * ctx,arg_msa_elm_df * a,gen_helper_piiii * gen_msa_elm_df)561 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
562 gen_helper_piiii *gen_msa_elm_df)
563 {
564 if (a->df < 0) {
565 return false;
566 }
567
568 if (!check_msa_enabled(ctx)) {
569 return true;
570 }
571
572 gen_msa_elm_df(tcg_env,
573 tcg_constant_i32(a->df),
574 tcg_constant_i32(a->wd),
575 tcg_constant_i32(a->ws),
576 tcg_constant_i32(a->n));
577
578 return true;
579 }
580
581 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df);
582 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df);
583 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df);
584
trans_msa_elm_fn(DisasContext * ctx,arg_msa_elm_df * a,gen_helper_piii * const gen_msa_elm[4])585 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
586 gen_helper_piii * const gen_msa_elm[4])
587 {
588 if (a->df < 0 || !gen_msa_elm[a->df]) {
589 return false;
590 }
591
592 if (!check_msa_enabled(ctx)) {
593 return true;
594 }
595
596 gen_msa_elm[a->df](tcg_env,
597 tcg_constant_i32(a->wd),
598 tcg_constant_i32(a->ws),
599 tcg_constant_i32(a->n));
600
601 return true;
602 }
603
604 #if defined(TARGET_MIPS64)
605 #define NULL_IF_MIPS32(function) function
606 #else
607 #define NULL_IF_MIPS32(function) NULL
608 #endif
609
trans_COPY_U(DisasContext * ctx,arg_msa_elm_df * a)610 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
611 {
612 if (a->wd == 0) {
613 /* Treat as NOP. */
614 return true;
615 }
616
617 static gen_helper_piii * const gen_msa_copy_u[4] = {
618 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h,
619 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL
620 };
621
622 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u);
623 }
624
trans_COPY_S(DisasContext * ctx,arg_msa_elm_df * a)625 static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a)
626 {
627 if (a->wd == 0) {
628 /* Treat as NOP. */
629 return true;
630 }
631
632 static gen_helper_piii * const gen_msa_copy_s[4] = {
633 gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h,
634 gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d)
635 };
636
637 return trans_msa_elm_fn(ctx, a, gen_msa_copy_s);
638 }
639
trans_INSERT(DisasContext * ctx,arg_msa_elm_df * a)640 static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a)
641 {
642 static gen_helper_piii * const gen_msa_insert[4] = {
643 gen_helper_msa_insert_b, gen_helper_msa_insert_h,
644 gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d)
645 };
646
647 return trans_msa_elm_fn(ctx, a, gen_msa_insert);
648 }
649
650 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df);
651 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df);
652 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df);
653 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df);
654 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df);
655 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df);
656 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df);
657 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df);
658 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df);
659 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df);
660 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df);
661 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df);
662 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df);
663 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df);
664 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df);
665 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df);
666
667 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df);
668 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df);
669 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df);
670 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df);
671 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df);
672 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df);
673 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df);
674 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df);
675 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df);
676 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df);
677 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df);
678 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df);
679 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df);
680
681 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df);
682 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df);
683 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df);
684 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df);
685 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df);
686 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df);
687 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df);
688 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df);
689 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df);
690 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df);
691 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df);
692 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df);
693
trans_msa_2r(DisasContext * ctx,arg_msa_r * a,gen_helper_pii * gen_msa_2r)694 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
695 gen_helper_pii *gen_msa_2r)
696 {
697 if (!check_msa_enabled(ctx)) {
698 return true;
699 }
700
701 gen_msa_2r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
702
703 return true;
704 }
705
706 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
707 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc);
708 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
709
trans_FILL(DisasContext * ctx,arg_msa_r * a)710 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
711 {
712 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
713 /* Double format valid only for MIPS64 */
714 return false;
715 }
716
717 if (!check_msa_enabled(ctx)) {
718 return true;
719 }
720
721 gen_helper_msa_fill_df(tcg_env,
722 tcg_constant_i32(a->df),
723 tcg_constant_i32(a->wd),
724 tcg_constant_i32(a->ws));
725
726 return true;
727 }
728
trans_msa_2rf(DisasContext * ctx,arg_msa_r * a,gen_helper_piii * gen_msa_2rf)729 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
730 gen_helper_piii *gen_msa_2rf)
731 {
732 if (!check_msa_enabled(ctx)) {
733 return true;
734 }
735
736 gen_msa_2rf(tcg_env,
737 tcg_constant_i32(a->df),
738 tcg_constant_i32(a->wd),
739 tcg_constant_i32(a->ws));
740
741 return true;
742 }
743
744 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df);
745 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
746 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_u_df);
747 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df);
748 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df);
749 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df);
750 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df);
751 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df);
752 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df);
753 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df);
754 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df);
755 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df);
756 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df);
757 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
758 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
759 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
760
trans_msa_ldst(DisasContext * ctx,arg_msa_i * a,gen_helper_piv * gen_msa_ldst)761 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
762 gen_helper_piv *gen_msa_ldst)
763 {
764 TCGv taddr;
765
766 if (!check_msa_enabled(ctx)) {
767 return true;
768 }
769
770 taddr = tcg_temp_new();
771
772 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
773 gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);
774
775 return true;
776 }
777
778 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld);
779 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
780
trans_LSA(DisasContext * ctx,arg_r * a)781 static bool trans_LSA(DisasContext *ctx, arg_r *a)
782 {
783 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
784 }
785
trans_DLSA(DisasContext * ctx,arg_r * a)786 static bool trans_DLSA(DisasContext *ctx, arg_r *a)
787 {
788 if (TARGET_LONG_BITS != 64) {
789 return false;
790 }
791 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
792 }
793