/qemu/accel/tcg/ |
H A D | watchpoint.c | 45 vaddr wpend = wp->vaddr + wp->len - 1; in watchpoint_address_matches() 48 return !(addr > wpend || wp->vaddr > addrend); in watchpoint_address_matches() 54 CPUWatchpoint *wp; in cpu_watchpoint_address_matches() local 59 ret |= wp->flags; in cpu_watchpoint_address_matches() 70 CPUWatchpoint *wp; in cpu_check_watchpoint() local 92 int hit_flags = wp->flags & flags; in cpu_check_watchpoint() 115 wp->hitaddr = MAX(addr, wp->vaddr); in cpu_check_watchpoint() 116 wp->hitattrs = attrs; in cpu_check_watchpoint() 118 if (wp->flags & BP_CPU in cpu_check_watchpoint() 124 cpu->watchpoint_hit = wp; in cpu_check_watchpoint() [all …]
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H A D | cpu-exec.c | 706 CPUWatchpoint *wp; in cpu_handle_debug_exception() local 709 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { in cpu_handle_debug_exception() 710 wp->flags &= ~BP_WATCHPOINT_HIT; in cpu_handle_debug_exception()
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/qemu/system/ |
H A D | watchpoint.c | 29 CPUWatchpoint *wp; in cpu_watchpoint_insert() local 38 wp = g_malloc(sizeof(*wp)); in cpu_watchpoint_insert() 40 wp->vaddr = addr; in cpu_watchpoint_insert() 41 wp->len = len; in cpu_watchpoint_insert() 42 wp->flags = flags; in cpu_watchpoint_insert() 59 *watchpoint = wp; in cpu_watchpoint_insert() 68 CPUWatchpoint *wp; in cpu_watchpoint_remove() local 70 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { in cpu_watchpoint_remove() 71 if (addr == wp->vaddr && len == wp->len in cpu_watchpoint_remove() 93 CPUWatchpoint *wp, *next; in cpu_watchpoint_remove_all() local [all …]
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/qemu/target/arm/ |
H A D | hyp_gdbstub.c | 130 HWWatchpoint wp = { in insert_hw_watchpoint() local 144 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); in insert_hw_watchpoint() 148 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); in insert_hw_watchpoint() 149 wp.details.flags = BP_MEM_READ; in insert_hw_watchpoint() 152 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); in insert_hw_watchpoint() 156 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); in insert_hw_watchpoint() 168 wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas); in insert_hw_watchpoint() 175 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); in insert_hw_watchpoint() 176 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); in insert_hw_watchpoint() 188 HWWatchpoint *wp = get_hw_wp(i); in check_watchpoint_in_range() local [all …]
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H A D | debug_helper.c | 269 CPUWatchpoint *wp = env->cpu_watchpoint[n]; in bp_wp_matches() local 271 if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { in bp_wp_matches() 275 if (wp->hitattrs.user) { in bp_wp_matches() 423 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) in arm_debug_check_watchpoint() argument
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H A D | kvm.c | 1396 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); in kvm_arm_handle_debug() local 1397 if (wp) { in kvm_arm_handle_debug() 1398 cs->watchpoint_hit = wp; in kvm_arm_handle_debug() 1481 HWWatchpoint *wp = get_hw_wp(i); in kvm_arm_copy_hw_debug_data() local 1482 ptr->dbg_wcr[i] = wp->wcr; in kvm_arm_copy_hw_debug_data() 1483 ptr->dbg_wvr[i] = wp->wvr; in kvm_arm_copy_hw_debug_data()
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/qemu/tests/tcg/multiarch/gdbstub/ |
H A D | memory.py | 47 wp = gdb.Breakpoint(sym, gdb.BP_WATCHPOINT, wtype) 51 if wp.hit_count > 0: 53 wp.delete()
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/qemu/hw/ppc/ |
H A D | ppc_booke.c | 115 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; in booke_get_wdt_target() local 121 wp = 63 - (wp | wpext << 2); in booke_get_wdt_target() 123 wp = env->wdt_period[wp]; in booke_get_wdt_target() 126 return wp; in booke_get_wdt_target()
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/qemu/include/block/ |
H A D | block-common.h | 123 uint64_t wp; member 133 uint64_t wp[]; member 269 #define BDRV_ZT_IS_CONV(wp) (wp & (1ULL << 63)) argument
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/qemu/io/ |
H A D | channel-command.c | 296 pid_t wp; in qio_channel_command_close() local 315 wp = waitpid(cioc->pid, NULL, 0); in qio_channel_command_close() 316 } while (wp == (pid_t)-1 && errno == EINTR); in qio_channel_command_close() 317 if (wp == (pid_t)-1) { in qio_channel_command_close()
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/qemu/hw/block/ |
H A D | nand.c | 73 uint8_t cle, ale, ce, wp, gnd; member 312 if (s->wp) { in nand_command() 325 if (s->wp) { in nand_command() 372 VMSTATE_UINT8(wp, NANDFlashState), 485 uint8_t ce, uint8_t wp, uint8_t gnd) in nand_setpins() argument 492 s->wp = wp; in nand_setpins() 494 if (wp) { in nand_setpins()
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/qemu/util/ |
H A D | userfaultfd.c | 214 bool wp, bool dont_wake) in uffd_change_protection() argument 220 if (!wp && dont_wake) { in uffd_change_protection() 224 uffd_writeprotect.mode = (wp ? UFFDIO_WRITEPROTECT_MODE_WP : 0); in uffd_change_protection()
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/qemu/target/riscv/ |
H A D | debug.c | 836 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) in riscv_cpu_debug_check_watchpoint() argument 867 if ((wp->flags & flags) && (wp->vaddr == addr)) { in riscv_cpu_debug_check_watchpoint() 886 if ((wp->flags & flags) && (wp->vaddr == addr)) { in riscv_cpu_debug_check_watchpoint()
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H A D | debug.h | 146 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
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/qemu/include/qemu/ |
H A D | userfaultfd.h | 36 bool wp, bool dont_wake);
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/qemu/block/ |
H A D | file-posix.c | 1358 wps->wp[j] |= 1ULL << 63; in get_zones_wp() 1374 wps->wp[j] = blkz[i].wp << BDRV_SECTOR_BITS; in get_zones_wp() 2024 zone->wp = blkz->wp << BDRV_SECTOR_BITS; in parse_zone() 2492 offset = bs->wps->wp[index]; in raw_co_prw() 2542 uint64_t *wp = &wps->wp[offset / bs->bl.zone_size]; in raw_co_prw() local 2543 if (!BDRV_ZT_IS_CONV(*wp)) { in raw_co_prw() 2545 *offset_ptr = *wp; in raw_co_prw() 2550 if (offset + bytes > *wp) { in raw_co_prw() 2551 *wp = offset + bytes; in raw_co_prw() 3436 uint64_t *wp = &wps->wp[i]; in raw_co_zone_mgmt() local [all …]
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/qemu/include/hw/block/ |
H A D | flash.h | 50 uint8_t ce, uint8_t wp, uint8_t gnd);
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/qemu/include/hw/core/ |
H A D | tcg-cpu-ops.h | 167 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
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H A D | cpu.h | 1116 CPUWatchpoint *wp) in cpu_watchpoint_remove_by_ref() argument
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/qemu/hw/audio/ |
H A D | intel-hda.c | 348 uint32_t wp, ex; in intel_hda_response() local 366 wp = (d->rirb_wp + 1) & 0xff; in intel_hda_response() 368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); in intel_hda_response() 369 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); in intel_hda_response() 374 d->rirb_wp = wp; in intel_hda_response() 377 __func__, wp, response, ex); in intel_hda_response()
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/qemu/target/arm/hvf/ |
H A D | hvf.c | 1893 CPUWatchpoint *wp = in hvf_vcpu_exec() local 1895 if (!wp) { in hvf_vcpu_exec() 1898 cpu->watchpoint_hit = wp; in hvf_vcpu_exec() 2136 HWWatchpoint *wp = get_hw_wp(i); in hvf_put_gdbstub_debug_registers() local 2137 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); in hvf_put_gdbstub_debug_registers() 2139 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); in hvf_put_gdbstub_debug_registers()
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/qemu/hw/nvme/ |
H A D | ns.c | 257 zone->d.wp = start; in nvme_ns_zoned_init_state() 335 zone->w_ptr = zone->d.wp; in nvme_clear_zone() 337 if (zone->d.wp != zone->d.zslba || in nvme_clear_zone()
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H A D | trace-events | 145 …not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "writing at slba=%"PRIu64", zone=%"PRIu64", b… 151 pci_nvme_err_zone_invalid_write(uint64_t slba, uint64_t wp) "lba 0x%"PRIx64" wp 0x%"PRIx64""
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/qemu/target/ppc/ |
H A D | internal.h | 289 bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
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/qemu/target/arm/tcg/ |
H A D | mte_helper.c | 179 int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; in allocation_tag_mem_probe() 181 cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); in allocation_tag_mem_probe()
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