1 /** @file 2 Intel Architectural MSR Definitions. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR> 10 SPDX-License-Identifier: BSD-2-Clause-Patent 11 12 @par Specification Reference: 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 14 May 2018, Volume 4: Model-Specific-Registers (MSR) 15 16 **/ 17 18 #ifndef __INTEL_ARCHITECTURAL_MSR_H__ 19 #define __INTEL_ARCHITECTURAL_MSR_H__ 20 21 /** 22 See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H). 23 24 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000) 25 @param EAX Lower 32-bits of MSR value. 26 @param EDX Upper 32-bits of MSR value. 27 28 <b>Example usage</b> 29 @code 30 UINT64 Msr; 31 32 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR); 33 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr); 34 @endcode 35 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM. 36 **/ 37 #define MSR_IA32_P5_MC_ADDR 0x00000000 38 39 /** 40 See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H. 41 42 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001) 43 @param EAX Lower 32-bits of MSR value. 44 @param EDX Upper 32-bits of MSR value. 45 46 <b>Example usage</b> 47 @code 48 UINT64 Msr; 49 50 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE); 51 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr); 52 @endcode 53 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM. 54 **/ 55 #define MSR_IA32_P5_MC_TYPE 0x00000001 56 57 /** 58 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced 59 at Display Family / Display Model 0F_03H. 60 61 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006) 62 @param EAX Lower 32-bits of MSR value. 63 @param EDX Upper 32-bits of MSR value. 64 65 <b>Example usage</b> 66 @code 67 UINT64 Msr; 68 69 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE); 70 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr); 71 @endcode 72 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM. 73 **/ 74 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 75 76 /** 77 See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family / 78 Display Model 05_01H. 79 80 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010) 81 @param EAX Lower 32-bits of MSR value. 82 @param EDX Upper 32-bits of MSR value. 83 84 <b>Example usage</b> 85 @code 86 UINT64 Msr; 87 88 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER); 89 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr); 90 @endcode 91 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM. 92 **/ 93 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 94 95 /** 96 Platform ID (RO) The operating system can use this MSR to determine "slot" 97 information for the processor and the proper microcode update to load. 98 Introduced at Display Family / Display Model 06_01H. 99 100 @param ECX MSR_IA32_PLATFORM_ID (0x00000017) 101 @param EAX Lower 32-bits of MSR value. 102 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 103 @param EDX Upper 32-bits of MSR value. 104 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 105 106 <b>Example usage</b> 107 @code 108 MSR_IA32_PLATFORM_ID_REGISTER Msr; 109 110 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); 111 @endcode 112 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. 113 **/ 114 #define MSR_IA32_PLATFORM_ID 0x00000017 115 116 /** 117 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID 118 **/ 119 typedef union { 120 /// 121 /// Individual bit fields 122 /// 123 struct { 124 UINT32 Reserved1 : 32; 125 UINT32 Reserved2 : 18; 126 /// 127 /// [Bits 52:50] Platform Id (RO) Contains information concerning the 128 /// intended platform for the processor. 129 /// 52 51 50 130 /// -- -- -- 131 /// 0 0 0 Processor Flag 0. 132 /// 0 0 1 Processor Flag 1 133 /// 0 1 0 Processor Flag 2 134 /// 0 1 1 Processor Flag 3 135 /// 1 0 0 Processor Flag 4 136 /// 1 0 1 Processor Flag 5 137 /// 1 1 0 Processor Flag 6 138 /// 1 1 1 Processor Flag 7 139 /// 140 UINT32 PlatformId : 3; 141 UINT32 Reserved3 : 11; 142 } Bits; 143 /// 144 /// All bit fields as a 64-bit value 145 /// 146 UINT64 Uint64; 147 } MSR_IA32_PLATFORM_ID_REGISTER; 148 149 /** 150 06_01H. 151 152 @param ECX MSR_IA32_APIC_BASE (0x0000001B) 153 @param EAX Lower 32-bits of MSR value. 154 Described by the type MSR_IA32_APIC_BASE_REGISTER. 155 @param EDX Upper 32-bits of MSR value. 156 Described by the type MSR_IA32_APIC_BASE_REGISTER. 157 158 <b>Example usage</b> 159 @code 160 MSR_IA32_APIC_BASE_REGISTER Msr; 161 162 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); 163 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64); 164 @endcode 165 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM. 166 **/ 167 #define MSR_IA32_APIC_BASE 0x0000001B 168 169 /** 170 MSR information returned for MSR index #MSR_IA32_APIC_BASE 171 **/ 172 typedef union { 173 /// 174 /// Individual bit fields 175 /// 176 struct { 177 UINT32 Reserved1 : 8; 178 /// 179 /// [Bit 8] BSP flag (R/W). 180 /// 181 UINT32 BSP : 1; 182 UINT32 Reserved2 : 1; 183 /// 184 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display 185 /// Model 06_1AH. 186 /// 187 UINT32 EXTD : 1; 188 /// 189 /// [Bit 11] APIC Global Enable (R/W). 190 /// 191 UINT32 EN : 1; 192 /// 193 /// [Bits 31:12] APIC Base (R/W). 194 /// 195 UINT32 ApicBase : 20; 196 /// 197 /// [Bits 63:32] APIC Base (R/W). 198 /// 199 UINT32 ApicBaseHi : 32; 200 } Bits; 201 /// 202 /// All bit fields as a 64-bit value 203 /// 204 UINT64 Uint64; 205 } MSR_IA32_APIC_BASE_REGISTER; 206 207 /** 208 Control Features in Intel 64 Processor (R/W). If any one enumeration 209 condition for defined bit field holds. 210 211 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A) 212 @param EAX Lower 32-bits of MSR value. 213 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 214 @param EDX Upper 32-bits of MSR value. 215 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 216 217 <b>Example usage</b> 218 @code 219 MSR_IA32_FEATURE_CONTROL_REGISTER Msr; 220 221 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); 222 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64); 223 @endcode 224 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. 225 **/ 226 #define MSR_IA32_FEATURE_CONTROL 0x0000003A 227 228 /** 229 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL 230 **/ 231 typedef union { 232 /// 233 /// Individual bit fields 234 /// 235 struct { 236 /// 237 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from 238 /// being written, writes to this bit will result in GP(0). Note: Once the 239 /// Lock bit is set, the contents of this register cannot be modified. 240 /// Therefore the lock bit must be set after configuring support for Intel 241 /// Virtualization Technology and prior to transferring control to an 242 /// option ROM or the OS. Hence, once the Lock bit is set, the entire 243 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD 244 /// is not deasserted. If any one enumeration condition for defined bit 245 /// field position greater than bit 0 holds. 246 /// 247 UINT32 Lock : 1; 248 /// 249 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a 250 /// system executive to use VMX in conjunction with SMX to support 251 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only 252 /// when the CPUID function 1 returns VMX feature flag and SMX feature 253 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && 254 /// CPUID.01H:ECX[6] = 1. 255 /// 256 UINT32 EnableVmxInsideSmx : 1; 257 /// 258 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX 259 /// for system executive that do not require SMX. BIOS must set this bit 260 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit 261 /// 5). If CPUID.01H:ECX[5] = 1. 262 /// 263 UINT32 EnableVmxOutsideSmx : 1; 264 UINT32 Reserved1 : 5; 265 /// 266 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit 267 /// in the field represents an enable control for a corresponding SENTER 268 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If 269 /// CPUID.01H:ECX[6] = 1. 270 /// 271 UINT32 SenterLocalFunctionEnables : 7; 272 /// 273 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable 274 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit 275 /// 6] is set. If CPUID.01H:ECX[6] = 1. 276 /// 277 UINT32 SenterGlobalEnable : 1; 278 UINT32 Reserved2 : 1; 279 /// 280 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to 281 /// enable runtime reconfiguration of SGX Launch Control via 282 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. 283 /// 284 UINT32 SgxLaunchControlEnable : 1; 285 /// 286 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX 287 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1. 288 /// 289 UINT32 SgxEnable : 1; 290 UINT32 Reserved3 : 1; 291 /// 292 /// [Bit 20] LMCE On (R/WL): When set, system software can program the 293 /// MSRs associated with LMCE to configure delivery of some machine check 294 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1. 295 /// 296 UINT32 LmceOn : 1; 297 UINT32 Reserved4 : 11; 298 UINT32 Reserved5 : 32; 299 } Bits; 300 /// 301 /// All bit fields as a 32-bit value 302 /// 303 UINT32 Uint32; 304 /// 305 /// All bit fields as a 64-bit value 306 /// 307 UINT64 Uint64; 308 } MSR_IA32_FEATURE_CONTROL_REGISTER; 309 310 /** 311 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, 312 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for 313 a logical processor. Reset value is Zero. A write to IA32_TSC will modify 314 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does 315 not affect the internal invariant TSC hardware. 316 317 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B) 318 @param EAX Lower 32-bits of MSR value. 319 @param EDX Upper 32-bits of MSR value. 320 321 <b>Example usage</b> 322 @code 323 UINT64 Msr; 324 325 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST); 326 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr); 327 @endcode 328 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM. 329 **/ 330 #define MSR_IA32_TSC_ADJUST 0x0000003B 331 332 /** 333 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a 334 microcode update to be loaded into the processor. See Section 9.11.6, 335 "Microcode Update Loader." A processor may prevent writing to this MSR when 336 loading guest states on VM entries or saving guest states on VM exits. 337 Introduced at Display Family / Display Model 06_01H. 338 339 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079) 340 @param EAX Lower 32-bits of MSR value. 341 @param EDX Upper 32-bits of MSR value. 342 343 <b>Example usage</b> 344 @code 345 UINT64 Msr; 346 347 Msr = 0; 348 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr); 349 @endcode 350 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM. 351 **/ 352 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 353 354 /** 355 BIOS Update Signature (RO) Returns the microcode update signature following 356 the execution of CPUID.01H. A processor may prevent writing to this MSR when 357 loading guest states on VM entries or saving guest states on VM exits. 358 Introduced at Display Family / Display Model 06_01H. 359 360 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B) 361 @param EAX Lower 32-bits of MSR value. 362 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 363 @param EDX Upper 32-bits of MSR value. 364 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 365 366 <b>Example usage</b> 367 @code 368 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr; 369 370 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); 371 @endcode 372 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM. 373 **/ 374 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B 375 376 /** 377 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID 378 **/ 379 typedef union { 380 /// 381 /// Individual bit fields 382 /// 383 struct { 384 UINT32 Reserved : 32; 385 /// 386 /// [Bits 63:32] Microcode update signature. This field contains the 387 /// signature of the currently loaded microcode update when read following 388 /// the execution of the CPUID instruction, function 1. It is required 389 /// that this register field be pre-loaded with zero prior to executing 390 /// the CPUID, function 1. If the field remains equal to zero, then there 391 /// is no microcode update loaded. Another nonzero value will be the 392 /// signature. 393 /// 394 UINT32 MicrocodeUpdateSignature : 32; 395 } Bits; 396 /// 397 /// All bit fields as a 64-bit value 398 /// 399 UINT64 Uint64; 400 } MSR_IA32_BIOS_SIGN_ID_REGISTER; 401 402 /** 403 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the 404 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the 405 default value is the digest of Intel's signing key. Read permitted If 406 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): 407 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1. 408 409 @param ECX MSR_IA32_SGXLEPUBKEYHASHn 410 @param EAX Lower 32-bits of MSR value. 411 @param EDX Upper 32-bits of MSR value. 412 413 <b>Example usage</b> 414 @code 415 UINT64 Msr; 416 417 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn); 418 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr); 419 @endcode 420 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. 421 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. 422 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. 423 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM. 424 @{ 425 **/ 426 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 427 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 428 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 429 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 430 /// @} 431 432 /** 433 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = 434 1. 435 436 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) 437 @param EAX Lower 32-bits of MSR value. 438 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 439 @param EDX Upper 32-bits of MSR value. 440 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 441 442 <b>Example usage</b> 443 @code 444 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr; 445 446 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); 447 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64); 448 @endcode 449 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM. 450 **/ 451 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B 452 453 /** 454 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL 455 **/ 456 typedef union { 457 /// 458 /// Individual bit fields 459 /// 460 struct { 461 /// 462 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this 463 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment 464 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated 465 /// if the bit is 0. This bit is cleared when the logical processor is 466 /// reset. 467 /// 468 UINT32 Valid : 1; 469 UINT32 Reserved1 : 1; 470 /// 471 /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If 472 /// IA32_VMX_MISC[28]. 473 /// 474 UINT32 BlockSmi : 1; 475 UINT32 Reserved2 : 9; 476 /// 477 /// [Bits 31:12] MSEG Base (R/W). 478 /// 479 UINT32 MsegBase : 20; 480 UINT32 Reserved3 : 32; 481 } Bits; 482 /// 483 /// All bit fields as a 32-bit value 484 /// 485 UINT32 Uint32; 486 /// 487 /// All bit fields as a 64-bit value 488 /// 489 UINT64 Uint64; 490 } MSR_IA32_SMM_MONITOR_CTL_REGISTER; 491 492 /** 493 MSEG header that is located at the physical address specified by the MsegBase 494 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. 495 **/ 496 typedef struct { 497 /// 498 /// Different processors may use different MSEG revision identifiers. These 499 /// identifiers enable software to avoid using an MSEG header formatted for 500 /// one processor on a processor that uses a different format. Software can 501 /// discover the MSEG revision identifier that a processor uses by reading 502 /// the VMX capability MSR IA32_VMX_MISC. 503 // 504 UINT32 MsegHeaderRevision; 505 /// 506 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field 507 /// is the IA-32e mode SMM feature bit. It indicates whether the logical 508 /// processor will be in IA-32e mode after the STM is activated. 509 /// 510 UINT32 MonitorFeatures; 511 UINT32 GdtrLimit; 512 UINT32 GdtrBaseOffset; 513 UINT32 CsSelector; 514 UINT32 EipOffset; 515 UINT32 EspOffset; 516 UINT32 Cr3Offset; 517 /// 518 /// Pad header so total size is 2KB 519 /// 520 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; 521 } MSEG_HEADER; 522 523 /// 524 /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER 525 /// 526 #define STM_FEATURES_IA32E 0x1 527 /// 528 /// @} 529 /// 530 531 /** 532 Base address of the logical processor's SMRAM image (RO, SMM only). If 533 IA32_VMX_MISC[15]. 534 535 @param ECX MSR_IA32_SMBASE (0x0000009E) 536 @param EAX Lower 32-bits of MSR value. 537 @param EDX Upper 32-bits of MSR value. 538 539 <b>Example usage</b> 540 @code 541 UINT64 Msr; 542 543 Msr = AsmReadMsr64 (MSR_IA32_SMBASE); 544 @endcode 545 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM. 546 **/ 547 #define MSR_IA32_SMBASE 0x0000009E 548 549 /** 550 General Performance Counters (R/W). 551 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n. 552 553 @param ECX MSR_IA32_PMCn 554 @param EAX Lower 32-bits of MSR value. 555 @param EDX Upper 32-bits of MSR value. 556 557 <b>Example usage</b> 558 @code 559 UINT64 Msr; 560 561 Msr = AsmReadMsr64 (MSR_IA32_PMC0); 562 AsmWriteMsr64 (MSR_IA32_PMC0, Msr); 563 @endcode 564 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. 565 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. 566 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. 567 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. 568 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. 569 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. 570 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. 571 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM. 572 @{ 573 **/ 574 #define MSR_IA32_PMC0 0x000000C1 575 #define MSR_IA32_PMC1 0x000000C2 576 #define MSR_IA32_PMC2 0x000000C3 577 #define MSR_IA32_PMC3 0x000000C4 578 #define MSR_IA32_PMC4 0x000000C5 579 #define MSR_IA32_PMC5 0x000000C6 580 #define MSR_IA32_PMC6 0x000000C7 581 #define MSR_IA32_PMC7 0x000000C8 582 /// @} 583 584 /** 585 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. 586 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative 587 to TSC freq.) when the logical processor is in C0. Cleared upon overflow / 588 wrap-around of IA32_APERF. 589 590 @param ECX MSR_IA32_MPERF (0x000000E7) 591 @param EAX Lower 32-bits of MSR value. 592 @param EDX Upper 32-bits of MSR value. 593 594 <b>Example usage</b> 595 @code 596 UINT64 Msr; 597 598 Msr = AsmReadMsr64 (MSR_IA32_MPERF); 599 AsmWriteMsr64 (MSR_IA32_MPERF, Msr); 600 @endcode 601 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM. 602 **/ 603 #define MSR_IA32_MPERF 0x000000E7 604 605 /** 606 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 607 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at 608 the coordinated clock frequency, when the logical processor is in C0. 609 Cleared upon overflow / wrap-around of IA32_MPERF. 610 611 @param ECX MSR_IA32_APERF (0x000000E8) 612 @param EAX Lower 32-bits of MSR value. 613 @param EDX Upper 32-bits of MSR value. 614 615 <b>Example usage</b> 616 @code 617 UINT64 Msr; 618 619 Msr = AsmReadMsr64 (MSR_IA32_APERF); 620 AsmWriteMsr64 (MSR_IA32_APERF, Msr); 621 @endcode 622 @note MSR_IA32_APERF is defined as IA32_APERF in SDM. 623 **/ 624 #define MSR_IA32_APERF 0x000000E8 625 626 /** 627 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". 628 Introduced at Display Family / Display Model 06_01H. 629 630 @param ECX MSR_IA32_MTRRCAP (0x000000FE) 631 @param EAX Lower 32-bits of MSR value. 632 Described by the type MSR_IA32_MTRRCAP_REGISTER. 633 @param EDX Upper 32-bits of MSR value. 634 Described by the type MSR_IA32_MTRRCAP_REGISTER. 635 636 <b>Example usage</b> 637 @code 638 MSR_IA32_MTRRCAP_REGISTER Msr; 639 640 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); 641 @endcode 642 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM. 643 **/ 644 #define MSR_IA32_MTRRCAP 0x000000FE 645 646 /** 647 MSR information returned for MSR index #MSR_IA32_MTRRCAP 648 **/ 649 typedef union { 650 /// 651 /// Individual bit fields 652 /// 653 struct { 654 /// 655 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the 656 /// processor. 657 /// 658 UINT32 VCNT : 8; 659 /// 660 /// [Bit 8] Fixed range MTRRs are supported when set. 661 /// 662 UINT32 FIX : 1; 663 UINT32 Reserved1 : 1; 664 /// 665 /// [Bit 10] WC Supported when set. 666 /// 667 UINT32 WC : 1; 668 /// 669 /// [Bit 11] SMRR Supported when set. 670 /// 671 UINT32 SMRR : 1; 672 UINT32 Reserved2 : 20; 673 UINT32 Reserved3 : 32; 674 } Bits; 675 /// 676 /// All bit fields as a 32-bit value 677 /// 678 UINT32 Uint32; 679 /// 680 /// All bit fields as a 64-bit value 681 /// 682 UINT64 Uint64; 683 } MSR_IA32_MTRRCAP_REGISTER; 684 685 /** 686 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 687 688 @param ECX MSR_IA32_SYSENTER_CS (0x00000174) 689 @param EAX Lower 32-bits of MSR value. 690 Described by the type MSR_IA32_SYSENTER_CS_REGISTER. 691 @param EDX Upper 32-bits of MSR value. 692 Described by the type MSR_IA32_SYSENTER_CS_REGISTER. 693 694 <b>Example usage</b> 695 @code 696 MSR_IA32_SYSENTER_CS_REGISTER Msr; 697 698 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS); 699 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64); 700 @endcode 701 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM. 702 **/ 703 #define MSR_IA32_SYSENTER_CS 0x00000174 704 705 /** 706 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS 707 **/ 708 typedef union { 709 /// 710 /// Individual bit fields 711 /// 712 struct { 713 /// 714 /// [Bits 15:0] CS Selector. 715 /// 716 UINT32 CS : 16; 717 UINT32 Reserved1 : 16; 718 UINT32 Reserved2 : 32; 719 } Bits; 720 /// 721 /// All bit fields as a 32-bit value 722 /// 723 UINT32 Uint32; 724 /// 725 /// All bit fields as a 64-bit value 726 /// 727 UINT64 Uint64; 728 } MSR_IA32_SYSENTER_CS_REGISTER; 729 730 /** 731 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 732 733 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175) 734 @param EAX Lower 32-bits of MSR value. 735 @param EDX Upper 32-bits of MSR value. 736 737 <b>Example usage</b> 738 @code 739 UINT64 Msr; 740 741 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP); 742 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr); 743 @endcode 744 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM. 745 **/ 746 #define MSR_IA32_SYSENTER_ESP 0x00000175 747 748 /** 749 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 750 751 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176) 752 @param EAX Lower 32-bits of MSR value. 753 @param EDX Upper 32-bits of MSR value. 754 755 <b>Example usage</b> 756 @code 757 UINT64 Msr; 758 759 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP); 760 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr); 761 @endcode 762 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM. 763 **/ 764 #define MSR_IA32_SYSENTER_EIP 0x00000176 765 766 /** 767 Global Machine Check Capability (RO). Introduced at Display Family / Display 768 Model 06_01H. 769 770 @param ECX MSR_IA32_MCG_CAP (0x00000179) 771 @param EAX Lower 32-bits of MSR value. 772 Described by the type MSR_IA32_MCG_CAP_REGISTER. 773 @param EDX Upper 32-bits of MSR value. 774 Described by the type MSR_IA32_MCG_CAP_REGISTER. 775 776 <b>Example usage</b> 777 @code 778 MSR_IA32_MCG_CAP_REGISTER Msr; 779 780 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); 781 @endcode 782 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. 783 **/ 784 #define MSR_IA32_MCG_CAP 0x00000179 785 786 /** 787 MSR information returned for MSR index #MSR_IA32_MCG_CAP 788 **/ 789 typedef union { 790 /// 791 /// Individual bit fields 792 /// 793 struct { 794 /// 795 /// [Bits 7:0] Count: Number of reporting banks. 796 /// 797 UINT32 Count : 8; 798 /// 799 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. 800 /// 801 UINT32 MCG_CTL_P : 1; 802 /// 803 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present 804 /// if this bit is set. 805 /// 806 UINT32 MCG_EXT_P : 1; 807 /// 808 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. 809 /// Introduced at Display Family / Display Model 06_01H. 810 /// 811 UINT32 MCP_CMCI_P : 1; 812 /// 813 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present 814 /// if this bit is set. 815 /// 816 UINT32 MCG_TES_P : 1; 817 UINT32 Reserved1 : 4; 818 /// 819 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state 820 /// registers present. 821 /// 822 UINT32 MCG_EXT_CNT : 8; 823 /// 824 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if 825 /// this bit is set. 826 /// 827 UINT32 MCG_SER_P : 1; 828 UINT32 Reserved2 : 1; 829 /// 830 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform 831 /// firmware to be invoked when an error is detected so that it may 832 /// provide additional platform specific information in an ACPI format 833 /// "Generic Error Data Entry" that augments the data included in machine 834 /// check bank registers. Introduced at Display Family / Display Model 835 /// 06_3EH. 836 /// 837 UINT32 MCG_ELOG_P : 1; 838 /// 839 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended 840 /// state in IA32_MCG_STATUS and associated MSR necessary to configure 841 /// Local Machine Check Exception (LMCE). Introduced at Display Family / 842 /// Display Model 06_3EH. 843 /// 844 UINT32 MCG_LMCE_P : 1; 845 UINT32 Reserved3 : 4; 846 UINT32 Reserved4 : 32; 847 } Bits; 848 /// 849 /// All bit fields as a 32-bit value 850 /// 851 UINT32 Uint32; 852 /// 853 /// All bit fields as a 64-bit value 854 /// 855 UINT64 Uint64; 856 } MSR_IA32_MCG_CAP_REGISTER; 857 858 /** 859 Global Machine Check Status (R/W0). Introduced at Display Family / Display 860 Model 06_01H. 861 862 @param ECX MSR_IA32_MCG_STATUS (0x0000017A) 863 @param EAX Lower 32-bits of MSR value. 864 Described by the type MSR_IA32_MCG_STATUS_REGISTER. 865 @param EDX Upper 32-bits of MSR value. 866 Described by the type MSR_IA32_MCG_STATUS_REGISTER. 867 868 <b>Example usage</b> 869 @code 870 MSR_IA32_MCG_STATUS_REGISTER Msr; 871 872 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); 873 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64); 874 @endcode 875 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM. 876 **/ 877 #define MSR_IA32_MCG_STATUS 0x0000017A 878 879 /** 880 MSR information returned for MSR index #MSR_IA32_MCG_STATUS 881 **/ 882 typedef union { 883 /// 884 /// Individual bit fields 885 /// 886 struct { 887 /// 888 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display 889 /// Model 06_01H. 890 /// 891 UINT32 RIPV : 1; 892 /// 893 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display 894 /// Model 06_01H. 895 /// 896 UINT32 EIPV : 1; 897 /// 898 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family 899 /// / Display Model 06_01H. 900 /// 901 UINT32 MCIP : 1; 902 /// 903 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1. 904 /// 905 UINT32 LMCE_S : 1; 906 UINT32 Reserved1 : 28; 907 UINT32 Reserved2 : 32; 908 } Bits; 909 /// 910 /// All bit fields as a 32-bit value 911 /// 912 UINT32 Uint32; 913 /// 914 /// All bit fields as a 64-bit value 915 /// 916 UINT64 Uint64; 917 } MSR_IA32_MCG_STATUS_REGISTER; 918 919 /** 920 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1. 921 922 @param ECX MSR_IA32_MCG_CTL (0x0000017B) 923 @param EAX Lower 32-bits of MSR value. 924 @param EDX Upper 32-bits of MSR value. 925 926 <b>Example usage</b> 927 @code 928 UINT64 Msr; 929 930 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL); 931 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr); 932 @endcode 933 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM. 934 **/ 935 #define MSR_IA32_MCG_CTL 0x0000017B 936 937 /** 938 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n. 939 940 @param ECX MSR_IA32_PERFEVTSELn 941 @param EAX Lower 32-bits of MSR value. 942 Described by the type MSR_IA32_PERFEVTSEL_REGISTER. 943 @param EDX Upper 32-bits of MSR value. 944 Described by the type MSR_IA32_PERFEVTSEL_REGISTER. 945 946 <b>Example usage</b> 947 @code 948 MSR_IA32_PERFEVTSEL_REGISTER Msr; 949 950 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0); 951 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64); 952 @endcode 953 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. 954 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. 955 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. 956 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. 957 @{ 958 **/ 959 #define MSR_IA32_PERFEVTSEL0 0x00000186 960 #define MSR_IA32_PERFEVTSEL1 0x00000187 961 #define MSR_IA32_PERFEVTSEL2 0x00000188 962 #define MSR_IA32_PERFEVTSEL3 0x00000189 963 /// @} 964 965 /** 966 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to 967 #MSR_IA32_PERFEVTSEL3 968 **/ 969 typedef union { 970 /// 971 /// Individual bit fields 972 /// 973 struct { 974 /// 975 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 976 /// 977 UINT32 EventSelect : 8; 978 /// 979 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 980 /// detect on the selected event logic. 981 /// 982 UINT32 UMASK : 8; 983 /// 984 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 985 /// 986 UINT32 USR : 1; 987 /// 988 /// [Bit 17] OS: Counts while in privilege level is ring 0. 989 /// 990 UINT32 OS : 1; 991 /// 992 /// [Bit 18] Edge: Enables edge detection if set. 993 /// 994 UINT32 E : 1; 995 /// 996 /// [Bit 19] PC: enables pin control. 997 /// 998 UINT32 PC : 1; 999 /// 1000 /// [Bit 20] INT: enables interrupt on counter overflow. 1001 /// 1002 UINT32 INT : 1; 1003 /// 1004 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 1005 /// event conditions occurring across all logical processors sharing a 1006 /// processor core. When set to 0, the counter only increments the 1007 /// associated event conditions occurring in the logical processor which 1008 /// programmed the MSR. 1009 /// 1010 UINT32 ANY : 1; 1011 /// 1012 /// [Bit 22] EN: enables the corresponding performance counter to commence 1013 /// counting when this bit is set. 1014 /// 1015 UINT32 EN : 1; 1016 /// 1017 /// [Bit 23] INV: invert the CMASK. 1018 /// 1019 UINT32 INV : 1; 1020 /// 1021 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 1022 /// performance counter increments each cycle if the event count is 1023 /// greater than or equal to the CMASK. 1024 /// 1025 UINT32 CMASK : 8; 1026 UINT32 Reserved : 32; 1027 } Bits; 1028 /// 1029 /// All bit fields as a 32-bit value 1030 /// 1031 UINT32 Uint32; 1032 /// 1033 /// All bit fields as a 64-bit value 1034 /// 1035 UINT64 Uint64; 1036 } MSR_IA32_PERFEVTSEL_REGISTER; 1037 1038 /** 1039 Current performance state(P-State) operating point (RO). Introduced at 1040 Display Family / Display Model 0F_03H. 1041 1042 @param ECX MSR_IA32_PERF_STATUS (0x00000198) 1043 @param EAX Lower 32-bits of MSR value. 1044 Described by the type MSR_IA32_PERF_STATUS_REGISTER. 1045 @param EDX Upper 32-bits of MSR value. 1046 Described by the type MSR_IA32_PERF_STATUS_REGISTER. 1047 1048 <b>Example usage</b> 1049 @code 1050 MSR_IA32_PERF_STATUS_REGISTER Msr; 1051 1052 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS); 1053 @endcode 1054 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM. 1055 **/ 1056 #define MSR_IA32_PERF_STATUS 0x00000198 1057 1058 /** 1059 MSR information returned for MSR index #MSR_IA32_PERF_STATUS 1060 **/ 1061 typedef union { 1062 /// 1063 /// Individual bit fields 1064 /// 1065 struct { 1066 /// 1067 /// [Bits 15:0] Current performance State Value. 1068 /// 1069 UINT32 State : 16; 1070 UINT32 Reserved1 : 16; 1071 UINT32 Reserved2 : 32; 1072 } Bits; 1073 /// 1074 /// All bit fields as a 32-bit value 1075 /// 1076 UINT32 Uint32; 1077 /// 1078 /// All bit fields as a 64-bit value 1079 /// 1080 UINT64 Uint64; 1081 } MSR_IA32_PERF_STATUS_REGISTER; 1082 1083 /** 1084 (R/W). Introduced at Display Family / Display Model 0F_03H. 1085 1086 @param ECX MSR_IA32_PERF_CTL (0x00000199) 1087 @param EAX Lower 32-bits of MSR value. 1088 Described by the type MSR_IA32_PERF_CTL_REGISTER. 1089 @param EDX Upper 32-bits of MSR value. 1090 Described by the type MSR_IA32_PERF_CTL_REGISTER. 1091 1092 <b>Example usage</b> 1093 @code 1094 MSR_IA32_PERF_CTL_REGISTER Msr; 1095 1096 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL); 1097 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64); 1098 @endcode 1099 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM. 1100 **/ 1101 #define MSR_IA32_PERF_CTL 0x00000199 1102 1103 /** 1104 MSR information returned for MSR index #MSR_IA32_PERF_CTL 1105 **/ 1106 typedef union { 1107 /// 1108 /// Individual bit fields 1109 /// 1110 struct { 1111 /// 1112 /// [Bits 15:0] Target performance State Value. 1113 /// 1114 UINT32 TargetState : 16; 1115 UINT32 Reserved1 : 16; 1116 /// 1117 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH 1118 /// (Mobile only). 1119 /// 1120 UINT32 IDA : 1; 1121 UINT32 Reserved2 : 31; 1122 } Bits; 1123 /// 1124 /// All bit fields as a 64-bit value 1125 /// 1126 UINT64 Uint64; 1127 } MSR_IA32_PERF_CTL_REGISTER; 1128 1129 /** 1130 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled 1131 Clock Modulation.". If CPUID.01H:EDX[22] = 1. 1132 1133 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A) 1134 @param EAX Lower 32-bits of MSR value. 1135 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. 1136 @param EDX Upper 32-bits of MSR value. 1137 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. 1138 1139 <b>Example usage</b> 1140 @code 1141 MSR_IA32_CLOCK_MODULATION_REGISTER Msr; 1142 1143 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); 1144 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64); 1145 @endcode 1146 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. 1147 **/ 1148 #define MSR_IA32_CLOCK_MODULATION 0x0000019A 1149 1150 /** 1151 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION 1152 **/ 1153 typedef union { 1154 /// 1155 /// Individual bit fields 1156 /// 1157 struct { 1158 /// 1159 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If 1160 /// CPUID.06H:EAX[5] = 1. 1161 /// 1162 UINT32 ExtendedOnDemandClockModulationDutyCycle : 1; 1163 /// 1164 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded 1165 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1. 1166 /// 1167 UINT32 OnDemandClockModulationDutyCycle : 3; 1168 /// 1169 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. 1170 /// If CPUID.01H:EDX[22] = 1. 1171 /// 1172 UINT32 OnDemandClockModulationEnable : 1; 1173 UINT32 Reserved1 : 27; 1174 UINT32 Reserved2 : 32; 1175 } Bits; 1176 /// 1177 /// All bit fields as a 32-bit value 1178 /// 1179 UINT32 Uint32; 1180 /// 1181 /// All bit fields as a 64-bit value 1182 /// 1183 UINT64 Uint64; 1184 } MSR_IA32_CLOCK_MODULATION_REGISTER; 1185 1186 /** 1187 Thermal Interrupt Control (R/W) Enables and disables the generation of an 1188 interrupt on temperature transitions detected with the processor's thermal 1189 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". 1190 If CPUID.01H:EDX[22] = 1 1191 1192 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B) 1193 @param EAX Lower 32-bits of MSR value. 1194 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. 1195 @param EDX Upper 32-bits of MSR value. 1196 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. 1197 1198 <b>Example usage</b> 1199 @code 1200 MSR_IA32_THERM_INTERRUPT_REGISTER Msr; 1201 1202 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT); 1203 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64); 1204 @endcode 1205 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM. 1206 **/ 1207 #define MSR_IA32_THERM_INTERRUPT 0x0000019B 1208 1209 /** 1210 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT 1211 **/ 1212 typedef union { 1213 /// 1214 /// Individual bit fields 1215 /// 1216 struct { 1217 /// 1218 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1219 /// 1220 UINT32 HighTempEnable : 1; 1221 /// 1222 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1223 /// 1224 UINT32 LowTempEnable : 1; 1225 /// 1226 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1227 /// 1228 UINT32 PROCHOT_Enable : 1; 1229 /// 1230 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1231 /// 1232 UINT32 FORCEPR_Enable : 1; 1233 /// 1234 /// [Bit 4] Critical Temperature Interrupt Enable. 1235 /// If CPUID.01H:EDX[22] = 1. 1236 /// 1237 UINT32 CriticalTempEnable : 1; 1238 UINT32 Reserved1 : 3; 1239 /// 1240 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1. 1241 /// 1242 UINT32 Threshold1 : 7; 1243 /// 1244 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1245 /// 1246 UINT32 Threshold1Enable : 1; 1247 /// 1248 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1. 1249 /// 1250 UINT32 Threshold2 : 7; 1251 /// 1252 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1253 /// 1254 UINT32 Threshold2Enable : 1; 1255 /// 1256 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1. 1257 /// 1258 UINT32 PowerLimitNotificationEnable : 1; 1259 UINT32 Reserved2 : 7; 1260 UINT32 Reserved3 : 32; 1261 } Bits; 1262 /// 1263 /// All bit fields as a 32-bit value 1264 /// 1265 UINT32 Uint32; 1266 /// 1267 /// All bit fields as a 64-bit value 1268 /// 1269 UINT64 Uint64; 1270 } MSR_IA32_THERM_INTERRUPT_REGISTER; 1271 1272 /** 1273 Thermal Status Information (RO) Contains status information about the 1274 processor's thermal sensor and automatic thermal monitoring facilities. See 1275 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1. 1276 1277 @param ECX MSR_IA32_THERM_STATUS (0x0000019C) 1278 @param EAX Lower 32-bits of MSR value. 1279 Described by the type MSR_IA32_THERM_STATUS_REGISTER. 1280 @param EDX Upper 32-bits of MSR value. 1281 Described by the type MSR_IA32_THERM_STATUS_REGISTER. 1282 1283 <b>Example usage</b> 1284 @code 1285 MSR_IA32_THERM_STATUS_REGISTER Msr; 1286 1287 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS); 1288 @endcode 1289 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM. 1290 **/ 1291 #define MSR_IA32_THERM_STATUS 0x0000019C 1292 1293 /** 1294 MSR information returned for MSR index #MSR_IA32_THERM_STATUS 1295 **/ 1296 typedef union { 1297 /// 1298 /// Individual bit fields 1299 /// 1300 struct { 1301 /// 1302 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1. 1303 /// 1304 UINT32 ThermalStatus : 1; 1305 /// 1306 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1. 1307 /// 1308 UINT32 ThermalStatusLog : 1; 1309 /// 1310 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1. 1311 /// 1312 UINT32 PROCHOT_FORCEPR_Event : 1; 1313 /// 1314 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1. 1315 /// 1316 UINT32 PROCHOT_FORCEPR_Log : 1; 1317 /// 1318 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1. 1319 /// 1320 UINT32 CriticalTempStatus : 1; 1321 /// 1322 /// [Bit 5] Critical Temperature Status log (R/WC0). 1323 /// If CPUID.01H:EDX[22] = 1. 1324 /// 1325 UINT32 CriticalTempStatusLog : 1; 1326 /// 1327 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1. 1328 /// 1329 UINT32 ThermalThreshold1Status : 1; 1330 /// 1331 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1. 1332 /// 1333 UINT32 ThermalThreshold1Log : 1; 1334 /// 1335 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1. 1336 /// 1337 UINT32 ThermalThreshold2Status : 1; 1338 /// 1339 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1. 1340 /// 1341 UINT32 ThermalThreshold2Log : 1; 1342 /// 1343 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1. 1344 /// 1345 UINT32 PowerLimitStatus : 1; 1346 /// 1347 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1. 1348 /// 1349 UINT32 PowerLimitLog : 1; 1350 /// 1351 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1. 1352 /// 1353 UINT32 CurrentLimitStatus : 1; 1354 /// 1355 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. 1356 /// 1357 UINT32 CurrentLimitLog : 1; 1358 /// 1359 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1. 1360 /// 1361 UINT32 CrossDomainLimitStatus : 1; 1362 /// 1363 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. 1364 /// 1365 UINT32 CrossDomainLimitLog : 1; 1366 /// 1367 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1. 1368 /// 1369 UINT32 DigitalReadout : 7; 1370 UINT32 Reserved1 : 4; 1371 /// 1372 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = 1373 /// 1. 1374 /// 1375 UINT32 ResolutionInDegreesCelsius : 4; 1376 /// 1377 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1. 1378 /// 1379 UINT32 ReadingValid : 1; 1380 UINT32 Reserved2 : 32; 1381 } Bits; 1382 /// 1383 /// All bit fields as a 32-bit value 1384 /// 1385 UINT32 Uint32; 1386 /// 1387 /// All bit fields as a 64-bit value 1388 /// 1389 UINT64 Uint64; 1390 } MSR_IA32_THERM_STATUS_REGISTER; 1391 1392 /** 1393 Enable Misc. Processor Features (R/W) Allows a variety of processor 1394 functions to be enabled and disabled. 1395 1396 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0) 1397 @param EAX Lower 32-bits of MSR value. 1398 Described by the type MSR_IA32_MISC_ENABLE_REGISTER. 1399 @param EDX Upper 32-bits of MSR value. 1400 Described by the type MSR_IA32_MISC_ENABLE_REGISTER. 1401 1402 <b>Example usage</b> 1403 @code 1404 MSR_IA32_MISC_ENABLE_REGISTER Msr; 1405 1406 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); 1407 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64); 1408 @endcode 1409 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 1410 **/ 1411 #define MSR_IA32_MISC_ENABLE 0x000001A0 1412 1413 /** 1414 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE 1415 **/ 1416 typedef union { 1417 /// 1418 /// Individual bit fields 1419 /// 1420 struct { 1421 /// 1422 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for 1423 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings 1424 /// are disabled. Introduced at Display Family / Display Model 0F_0H. 1425 /// 1426 UINT32 FastStrings : 1; 1427 UINT32 Reserved1 : 2; 1428 /// 1429 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting 1430 /// this bit enables the thermal control circuit (TCC) portion of the 1431 /// Intel Thermal Monitor feature. This allows the processor to 1432 /// automatically reduce power consumption in response to TCC activation. 1433 /// 0 = Disabled. Note: In some products clearing this bit might be 1434 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive 1435 /// thermal throttling will still be activated. The default value of this 1436 /// field varies with product. See respective tables where default value is 1437 /// listed. Introduced at Display Family / Display Model 0F_0H. 1438 /// 1439 UINT32 AutomaticThermalControlCircuit : 1; 1440 UINT32 Reserved2 : 3; 1441 /// 1442 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance 1443 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at 1444 /// Display Family / Display Model 0F_0H. 1445 /// 1446 UINT32 PerformanceMonitoring : 1; 1447 UINT32 Reserved3 : 3; 1448 /// 1449 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't 1450 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at 1451 /// Display Family / Display Model 0F_0H. 1452 /// 1453 UINT32 BTS : 1; 1454 /// 1455 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = 1456 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display 1457 /// Family / Display Model 06_0FH. 1458 /// 1459 UINT32 PEBS : 1; 1460 UINT32 Reserved4 : 3; 1461 /// 1462 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced 1463 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep 1464 /// Technology enabled. If CPUID.01H: ECX[7] =1. 1465 /// 1466 UINT32 EIST : 1; 1467 UINT32 Reserved5 : 1; 1468 /// 1469 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the 1470 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This 1471 /// indicates that MONITOR/MWAIT are not supported. Software attempts to 1472 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit 1473 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit 1474 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 1475 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it 1476 /// in the default state. Writing this bit when the SSE3 feature flag is 1477 /// set to 0 may generate a #GP exception. Introduced at Display Family / 1478 /// Display Model 0F_03H. 1479 /// 1480 UINT32 MONITOR : 1; 1481 UINT32 Reserved6 : 3; 1482 /// 1483 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H 1484 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup 1485 /// question that allows users to specify when the installed OS does not 1486 /// support CPUID functions greater than 2. Before setting this bit, BIOS 1487 /// must execute the CPUID.0H and examine the maximum value returned in 1488 /// EAX[7:0]. If the maximum value is greater than 2, this bit is 1489 /// supported. Otherwise, this bit is not supported. Setting this bit when 1490 /// the maximum value is not greater than 2 may generate a #GP exception. 1491 /// Setting this bit may cause unexpected behavior in software that 1492 /// depends on the availability of CPUID leaves greater than 2. Introduced 1493 /// at Display Family / Display Model 0F_03H. 1494 /// 1495 UINT32 LimitCpuidMaxval : 1; 1496 /// 1497 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are 1498 /// disabled. xTPR messages are optional messages that allow the processor 1499 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1. 1500 /// 1501 UINT32 xTPR_Message_Disable : 1; 1502 UINT32 Reserved7 : 8; 1503 UINT32 Reserved8 : 2; 1504 /// 1505 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit 1506 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will 1507 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the 1508 /// Execute Disable Bit feature (if available) allows the OS to enable PAE 1509 /// paging and take advantage of data only pages. BIOS must not alter the 1510 /// contents of this bit location, if XD bit is not supported. Writing 1511 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may 1512 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1. 1513 /// 1514 UINT32 XD : 1; 1515 UINT32 Reserved9 : 29; 1516 } Bits; 1517 /// 1518 /// All bit fields as a 64-bit value 1519 /// 1520 UINT64 Uint64; 1521 } MSR_IA32_MISC_ENABLE_REGISTER; 1522 1523 /** 1524 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1. 1525 1526 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0) 1527 @param EAX Lower 32-bits of MSR value. 1528 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. 1529 @param EDX Upper 32-bits of MSR value. 1530 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. 1531 1532 <b>Example usage</b> 1533 @code 1534 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr; 1535 1536 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS); 1537 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64); 1538 @endcode 1539 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. 1540 **/ 1541 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0 1542 1543 /** 1544 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS 1545 **/ 1546 typedef union { 1547 /// 1548 /// Individual bit fields 1549 /// 1550 struct { 1551 /// 1552 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest 1553 /// performance. 15 indicates preference to maximize energy saving. 1554 /// 1555 UINT32 PowerPolicyPreference : 4; 1556 UINT32 Reserved1 : 28; 1557 UINT32 Reserved2 : 32; 1558 } Bits; 1559 /// 1560 /// All bit fields as a 32-bit value 1561 /// 1562 UINT32 Uint32; 1563 /// 1564 /// All bit fields as a 64-bit value 1565 /// 1566 UINT64 Uint64; 1567 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER; 1568 1569 /** 1570 Package Thermal Status Information (RO) Contains status information about 1571 the package's thermal sensor. See Section 14.8, "Package Level Thermal 1572 Management.". If CPUID.06H: EAX[6] = 1. 1573 1574 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1) 1575 @param EAX Lower 32-bits of MSR value. 1576 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. 1577 @param EDX Upper 32-bits of MSR value. 1578 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. 1579 1580 <b>Example usage</b> 1581 @code 1582 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr; 1583 1584 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS); 1585 @endcode 1586 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM. 1587 **/ 1588 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1 1589 1590 /** 1591 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS 1592 **/ 1593 typedef union { 1594 /// 1595 /// Individual bit fields 1596 /// 1597 struct { 1598 /// 1599 /// [Bit 0] Pkg Thermal Status (RO):. 1600 /// 1601 UINT32 ThermalStatus : 1; 1602 /// 1603 /// [Bit 1] Pkg Thermal Status Log (R/W):. 1604 /// 1605 UINT32 ThermalStatusLog : 1; 1606 /// 1607 /// [Bit 2] Pkg PROCHOT # event (RO). 1608 /// 1609 UINT32 PROCHOT_Event : 1; 1610 /// 1611 /// [Bit 3] Pkg PROCHOT # log (R/WC0). 1612 /// 1613 UINT32 PROCHOT_Log : 1; 1614 /// 1615 /// [Bit 4] Pkg Critical Temperature Status (RO). 1616 /// 1617 UINT32 CriticalTempStatus : 1; 1618 /// 1619 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0). 1620 /// 1621 UINT32 CriticalTempStatusLog : 1; 1622 /// 1623 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO). 1624 /// 1625 UINT32 ThermalThreshold1Status : 1; 1626 /// 1627 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0). 1628 /// 1629 UINT32 ThermalThreshold1Log : 1; 1630 /// 1631 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO). 1632 /// 1633 UINT32 ThermalThreshold2Status : 1; 1634 /// 1635 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0). 1636 /// 1637 UINT32 ThermalThreshold2Log : 1; 1638 /// 1639 /// [Bit 10] Pkg Power Limitation Status (RO). 1640 /// 1641 UINT32 PowerLimitStatus : 1; 1642 /// 1643 /// [Bit 11] Pkg Power Limitation log (R/WC0). 1644 /// 1645 UINT32 PowerLimitLog : 1; 1646 UINT32 Reserved1 : 4; 1647 /// 1648 /// [Bits 22:16] Pkg Digital Readout (RO). 1649 /// 1650 UINT32 DigitalReadout : 7; 1651 UINT32 Reserved2 : 9; 1652 UINT32 Reserved3 : 32; 1653 } Bits; 1654 /// 1655 /// All bit fields as a 32-bit value 1656 /// 1657 UINT32 Uint32; 1658 /// 1659 /// All bit fields as a 64-bit value 1660 /// 1661 UINT64 Uint64; 1662 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER; 1663 1664 /** 1665 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of 1666 an interrupt on temperature transitions detected with the package's thermal 1667 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: 1668 EAX[6] = 1. 1669 1670 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2) 1671 @param EAX Lower 32-bits of MSR value. 1672 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. 1673 @param EDX Upper 32-bits of MSR value. 1674 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. 1675 1676 <b>Example usage</b> 1677 @code 1678 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr; 1679 1680 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT); 1681 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64); 1682 @endcode 1683 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM. 1684 **/ 1685 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2 1686 1687 /** 1688 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT 1689 **/ 1690 typedef union { 1691 /// 1692 /// Individual bit fields 1693 /// 1694 struct { 1695 /// 1696 /// [Bit 0] Pkg High-Temperature Interrupt Enable. 1697 /// 1698 UINT32 HighTempEnable : 1; 1699 /// 1700 /// [Bit 1] Pkg Low-Temperature Interrupt Enable. 1701 /// 1702 UINT32 LowTempEnable : 1; 1703 /// 1704 /// [Bit 2] Pkg PROCHOT# Interrupt Enable. 1705 /// 1706 UINT32 PROCHOT_Enable : 1; 1707 UINT32 Reserved1 : 1; 1708 /// 1709 /// [Bit 4] Pkg Overheat Interrupt Enable. 1710 /// 1711 UINT32 OverheatEnable : 1; 1712 UINT32 Reserved2 : 3; 1713 /// 1714 /// [Bits 14:8] Pkg Threshold #1 Value. 1715 /// 1716 UINT32 Threshold1 : 7; 1717 /// 1718 /// [Bit 15] Pkg Threshold #1 Interrupt Enable. 1719 /// 1720 UINT32 Threshold1Enable : 1; 1721 /// 1722 /// [Bits 22:16] Pkg Threshold #2 Value. 1723 /// 1724 UINT32 Threshold2 : 7; 1725 /// 1726 /// [Bit 23] Pkg Threshold #2 Interrupt Enable. 1727 /// 1728 UINT32 Threshold2Enable : 1; 1729 /// 1730 /// [Bit 24] Pkg Power Limit Notification Enable. 1731 /// 1732 UINT32 PowerLimitNotificationEnable : 1; 1733 UINT32 Reserved3 : 7; 1734 UINT32 Reserved4 : 32; 1735 } Bits; 1736 /// 1737 /// All bit fields as a 32-bit value 1738 /// 1739 UINT32 Uint32; 1740 /// 1741 /// All bit fields as a 64-bit value 1742 /// 1743 UINT64 Uint64; 1744 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER; 1745 1746 /** 1747 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display 1748 Model 06_0EH. 1749 1750 @param ECX MSR_IA32_DEBUGCTL (0x000001D9) 1751 @param EAX Lower 32-bits of MSR value. 1752 Described by the type MSR_IA32_DEBUGCTL_REGISTER. 1753 @param EDX Upper 32-bits of MSR value. 1754 Described by the type MSR_IA32_DEBUGCTL_REGISTER. 1755 1756 <b>Example usage</b> 1757 @code 1758 MSR_IA32_DEBUGCTL_REGISTER Msr; 1759 1760 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL); 1761 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64); 1762 @endcode 1763 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM. 1764 **/ 1765 #define MSR_IA32_DEBUGCTL 0x000001D9 1766 1767 /** 1768 MSR information returned for MSR index #MSR_IA32_DEBUGCTL 1769 **/ 1770 typedef union { 1771 /// 1772 /// Individual bit fields 1773 /// 1774 struct { 1775 /// 1776 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a 1777 /// running trace of the most recent branches taken by the processor in 1778 /// the LBR stack. Introduced at Display Family / Display Model 06_01H. 1779 /// 1780 UINT32 LBR : 1; 1781 /// 1782 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat 1783 /// EFLAGS.TF as single-step on branches instead of single-step on 1784 /// instructions. Introduced at Display Family / Display Model 06_01H. 1785 /// 1786 UINT32 BTF : 1; 1787 UINT32 Reserved1 : 4; 1788 /// 1789 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be 1790 /// sent. Introduced at Display Family / Display Model 06_0EH. 1791 /// 1792 UINT32 TR : 1; 1793 /// 1794 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to 1795 /// be logged in a BTS buffer. Introduced at Display Family / Display 1796 /// Model 06_0EH. 1797 /// 1798 UINT32 BTS : 1; 1799 /// 1800 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular 1801 /// fashion. When this bit is set, an interrupt is generated by the BTS 1802 /// facility when the BTS buffer is full. Introduced at Display Family / 1803 /// Display Model 06_0EH. 1804 /// 1805 UINT32 BTINT : 1; 1806 /// 1807 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. 1808 /// Introduced at Display Family / Display Model 06_0FH. 1809 /// 1810 UINT32 BTS_OFF_OS : 1; 1811 /// 1812 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. 1813 /// Introduced at Display Family / Display Model 06_0FH. 1814 /// 1815 UINT32 BTS_OFF_USR : 1; 1816 /// 1817 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a 1818 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. 1819 /// 1820 UINT32 FREEZE_LBRS_ON_PMI : 1; 1821 /// 1822 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the 1823 /// global counter control MSR are frozen (address 38FH) on a PMI request. 1824 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. 1825 /// 1826 UINT32 FREEZE_PERFMON_ON_PMI : 1; 1827 /// 1828 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to 1829 /// receive and generate PMI on behalf of the uncore. Introduced at 1830 /// Display Family / Display Model 06_1AH. 1831 /// 1832 UINT32 ENABLE_UNCORE_PMI : 1; 1833 /// 1834 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace 1835 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1. 1836 /// 1837 UINT32 FREEZE_WHILE_SMM : 1; 1838 /// 1839 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If 1840 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1). 1841 /// 1842 UINT32 RTM_DEBUG : 1; 1843 UINT32 Reserved2 : 16; 1844 UINT32 Reserved3 : 32; 1845 } Bits; 1846 /// 1847 /// All bit fields as a 32-bit value 1848 /// 1849 UINT32 Uint32; 1850 /// 1851 /// All bit fields as a 64-bit value 1852 /// 1853 UINT64 Uint64; 1854 } MSR_IA32_DEBUGCTL_REGISTER; 1855 1856 /** 1857 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. 1858 If IA32_MTRRCAP.SMRR[11] = 1. 1859 1860 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2) 1861 @param EAX Lower 32-bits of MSR value. 1862 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. 1863 @param EDX Upper 32-bits of MSR value. 1864 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. 1865 1866 <b>Example usage</b> 1867 @code 1868 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr; 1869 1870 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE); 1871 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64); 1872 @endcode 1873 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM. 1874 **/ 1875 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2 1876 1877 /** 1878 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE 1879 **/ 1880 typedef union { 1881 /// 1882 /// Individual bit fields 1883 /// 1884 struct { 1885 /// 1886 /// [Bits 7:0] Type. Specifies memory type of the range. 1887 /// 1888 UINT32 Type : 8; 1889 UINT32 Reserved1 : 4; 1890 /// 1891 /// [Bits 31:12] PhysBase. SMRR physical Base Address. 1892 /// 1893 UINT32 PhysBase : 20; 1894 UINT32 Reserved2 : 32; 1895 } Bits; 1896 /// 1897 /// All bit fields as a 32-bit value 1898 /// 1899 UINT32 Uint32; 1900 /// 1901 /// All bit fields as a 64-bit value 1902 /// 1903 UINT64 Uint64; 1904 } MSR_IA32_SMRR_PHYSBASE_REGISTER; 1905 1906 /** 1907 SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If 1908 IA32_MTRRCAP[SMRR] = 1. 1909 1910 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3) 1911 @param EAX Lower 32-bits of MSR value. 1912 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. 1913 @param EDX Upper 32-bits of MSR value. 1914 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. 1915 1916 <b>Example usage</b> 1917 @code 1918 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr; 1919 1920 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK); 1921 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64); 1922 @endcode 1923 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM. 1924 **/ 1925 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3 1926 1927 /** 1928 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK 1929 **/ 1930 typedef union { 1931 /// 1932 /// Individual bit fields 1933 /// 1934 struct { 1935 UINT32 Reserved1 : 11; 1936 /// 1937 /// [Bit 11] Valid Enable range mask. 1938 /// 1939 UINT32 Valid : 1; 1940 /// 1941 /// [Bits 31:12] PhysMask SMRR address range mask. 1942 /// 1943 UINT32 PhysMask : 20; 1944 UINT32 Reserved2 : 32; 1945 } Bits; 1946 /// 1947 /// All bit fields as a 32-bit value 1948 /// 1949 UINT32 Uint32; 1950 /// 1951 /// All bit fields as a 64-bit value 1952 /// 1953 UINT64 Uint64; 1954 } MSR_IA32_SMRR_PHYSMASK_REGISTER; 1955 1956 /** 1957 DCA Capability (R). If CPUID.01H: ECX[18] = 1. 1958 1959 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8) 1960 @param EAX Lower 32-bits of MSR value. 1961 @param EDX Upper 32-bits of MSR value. 1962 1963 <b>Example usage</b> 1964 @code 1965 UINT64 Msr; 1966 1967 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP); 1968 @endcode 1969 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM. 1970 **/ 1971 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 1972 1973 /** 1974 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1. 1975 1976 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9) 1977 @param EAX Lower 32-bits of MSR value. 1978 @param EDX Upper 32-bits of MSR value. 1979 1980 <b>Example usage</b> 1981 @code 1982 UINT64 Msr; 1983 1984 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP); 1985 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr); 1986 @endcode 1987 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM. 1988 **/ 1989 #define MSR_IA32_CPU_DCA_CAP 0x000001F9 1990 1991 /** 1992 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1. 1993 1994 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA) 1995 @param EAX Lower 32-bits of MSR value. 1996 Described by the type MSR_IA32_DCA_0_CAP_REGISTER. 1997 @param EDX Upper 32-bits of MSR value. 1998 Described by the type MSR_IA32_DCA_0_CAP_REGISTER. 1999 2000 <b>Example usage</b> 2001 @code 2002 MSR_IA32_DCA_0_CAP_REGISTER Msr; 2003 2004 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP); 2005 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64); 2006 @endcode 2007 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM. 2008 **/ 2009 #define MSR_IA32_DCA_0_CAP 0x000001FA 2010 2011 /** 2012 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP 2013 **/ 2014 typedef union { 2015 /// 2016 /// Individual bit fields 2017 /// 2018 struct { 2019 /// 2020 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no 2021 /// defeatures are set. 2022 /// 2023 UINT32 DCA_ACTIVE : 1; 2024 /// 2025 /// [Bits 2:1] TRANSACTION. 2026 /// 2027 UINT32 TRANSACTION : 2; 2028 /// 2029 /// [Bits 6:3] DCA_TYPE. 2030 /// 2031 UINT32 DCA_TYPE : 4; 2032 /// 2033 /// [Bits 10:7] DCA_QUEUE_SIZE. 2034 /// 2035 UINT32 DCA_QUEUE_SIZE : 4; 2036 UINT32 Reserved1 : 2; 2037 /// 2038 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW 2039 /// side-effect. 2040 /// 2041 UINT32 DCA_DELAY : 4; 2042 UINT32 Reserved2 : 7; 2043 /// 2044 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit. 2045 /// 2046 UINT32 SW_BLOCK : 1; 2047 UINT32 Reserved3 : 1; 2048 /// 2049 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). 2050 /// 2051 UINT32 HW_BLOCK : 1; 2052 UINT32 Reserved4 : 5; 2053 UINT32 Reserved5 : 32; 2054 } Bits; 2055 /// 2056 /// All bit fields as a 32-bit value 2057 /// 2058 UINT32 Uint32; 2059 /// 2060 /// All bit fields as a 64-bit value 2061 /// 2062 UINT64 Uint64; 2063 } MSR_IA32_DCA_0_CAP_REGISTER; 2064 2065 /** 2066 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". 2067 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. 2068 2069 @param ECX MSR_IA32_MTRR_PHYSBASEn 2070 @param EAX Lower 32-bits of MSR value. 2071 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. 2072 @param EDX Upper 32-bits of MSR value. 2073 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. 2074 2075 <b>Example usage</b> 2076 @code 2077 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr; 2078 2079 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0); 2080 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64); 2081 @endcode 2082 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. 2083 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. 2084 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. 2085 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. 2086 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. 2087 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. 2088 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. 2089 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. 2090 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. 2091 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM. 2092 @{ 2093 **/ 2094 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200 2095 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202 2096 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204 2097 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206 2098 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208 2099 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A 2100 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C 2101 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E 2102 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210 2103 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212 2104 /// @} 2105 2106 /** 2107 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to 2108 #MSR_IA32_MTRR_PHYSBASE9 2109 **/ 2110 typedef union { 2111 /// 2112 /// Individual bit fields 2113 /// 2114 struct { 2115 /// 2116 /// [Bits 7:0] Type. Specifies memory type of the range. 2117 /// 2118 UINT32 Type : 8; 2119 UINT32 Reserved1 : 4; 2120 /// 2121 /// [Bits 31:12] PhysBase. MTRR physical Base Address. 2122 /// 2123 UINT32 PhysBase : 20; 2124 /// 2125 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. 2126 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the 2127 /// maximum physical address range supported by the processor. It is 2128 /// reported by CPUID leaf function 80000008H. If CPUID does not support 2129 /// leaf 80000008H, the processor supports 36-bit physical address size, 2130 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. 2131 /// 2132 UINT32 PhysBaseHi : 32; 2133 } Bits; 2134 /// 2135 /// All bit fields as a 64-bit value 2136 /// 2137 UINT64 Uint64; 2138 } MSR_IA32_MTRR_PHYSBASE_REGISTER; 2139 2140 /** 2141 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". 2142 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. 2143 2144 @param ECX MSR_IA32_MTRR_PHYSMASKn 2145 @param EAX Lower 32-bits of MSR value. 2146 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. 2147 @param EDX Upper 32-bits of MSR value. 2148 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. 2149 2150 <b>Example usage</b> 2151 @code 2152 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr; 2153 2154 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0); 2155 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64); 2156 @endcode 2157 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. 2158 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. 2159 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. 2160 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. 2161 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. 2162 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. 2163 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. 2164 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. 2165 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. 2166 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM. 2167 @{ 2168 **/ 2169 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201 2170 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203 2171 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205 2172 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207 2173 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209 2174 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B 2175 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D 2176 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F 2177 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211 2178 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213 2179 /// @} 2180 2181 /** 2182 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to 2183 #MSR_IA32_MTRR_PHYSMASK9 2184 **/ 2185 typedef union { 2186 /// 2187 /// Individual bit fields 2188 /// 2189 struct { 2190 UINT32 Reserved1 : 11; 2191 /// 2192 /// [Bit 11] Valid Enable range mask. 2193 /// 2194 UINT32 V : 1; 2195 /// 2196 /// [Bits 31:12] PhysMask. MTRR address range mask. 2197 /// 2198 UINT32 PhysMask : 20; 2199 /// 2200 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. 2201 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the 2202 /// maximum physical address range supported by the processor. It is 2203 /// reported by CPUID leaf function 80000008H. If CPUID does not support 2204 /// leaf 80000008H, the processor supports 36-bit physical address size, 2205 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. 2206 /// 2207 UINT32 PhysMaskHi : 32; 2208 } Bits; 2209 /// 2210 /// All bit fields as a 64-bit value 2211 /// 2212 UINT64 Uint64; 2213 } MSR_IA32_MTRR_PHYSMASK_REGISTER; 2214 2215 /** 2216 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1. 2217 2218 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250) 2219 @param EAX Lower 32-bits of MSR value. 2220 @param EDX Upper 32-bits of MSR value. 2221 2222 <b>Example usage</b> 2223 @code 2224 UINT64 Msr; 2225 2226 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000); 2227 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr); 2228 @endcode 2229 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM. 2230 **/ 2231 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250 2232 2233 /** 2234 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1. 2235 2236 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258) 2237 @param EAX Lower 32-bits of MSR value. 2238 @param EDX Upper 32-bits of MSR value. 2239 2240 <b>Example usage</b> 2241 @code 2242 UINT64 Msr; 2243 2244 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000); 2245 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr); 2246 @endcode 2247 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM. 2248 **/ 2249 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258 2250 2251 /** 2252 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1. 2253 2254 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259) 2255 @param EAX Lower 32-bits of MSR value. 2256 @param EDX Upper 32-bits of MSR value. 2257 2258 <b>Example usage</b> 2259 @code 2260 UINT64 Msr; 2261 2262 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000); 2263 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr); 2264 @endcode 2265 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM. 2266 **/ 2267 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259 2268 2269 /** 2270 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1. 2271 2272 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268) 2273 @param EAX Lower 32-bits of MSR value. 2274 @param EDX Upper 32-bits of MSR value. 2275 2276 <b>Example usage</b> 2277 @code 2278 UINT64 Msr; 2279 2280 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000); 2281 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr); 2282 @endcode 2283 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM. 2284 **/ 2285 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268 2286 2287 /** 2288 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1. 2289 2290 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269) 2291 @param EAX Lower 32-bits of MSR value. 2292 @param EDX Upper 32-bits of MSR value. 2293 2294 <b>Example usage</b> 2295 @code 2296 UINT64 Msr; 2297 2298 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000); 2299 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr); 2300 @endcode 2301 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM. 2302 **/ 2303 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269 2304 2305 /** 2306 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1. 2307 2308 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A) 2309 @param EAX Lower 32-bits of MSR value. 2310 @param EDX Upper 32-bits of MSR value. 2311 2312 <b>Example usage</b> 2313 @code 2314 UINT64 Msr; 2315 2316 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000); 2317 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr); 2318 @endcode 2319 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM. 2320 **/ 2321 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A 2322 2323 /** 2324 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1. 2325 2326 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B) 2327 @param EAX Lower 32-bits of MSR value. 2328 @param EDX Upper 32-bits of MSR value. 2329 2330 <b>Example usage</b> 2331 @code 2332 UINT64 Msr; 2333 2334 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000); 2335 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr); 2336 @endcode 2337 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM. 2338 **/ 2339 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B 2340 2341 /** 2342 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1. 2343 2344 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C) 2345 @param EAX Lower 32-bits of MSR value. 2346 @param EDX Upper 32-bits of MSR value. 2347 2348 <b>Example usage</b> 2349 @code 2350 UINT64 Msr; 2351 2352 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000); 2353 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr); 2354 @endcode 2355 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM. 2356 **/ 2357 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C 2358 2359 /** 2360 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1. 2361 2362 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D) 2363 @param EAX Lower 32-bits of MSR value. 2364 @param EDX Upper 32-bits of MSR value. 2365 2366 <b>Example usage</b> 2367 @code 2368 UINT64 Msr; 2369 2370 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000); 2371 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr); 2372 @endcode 2373 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM. 2374 **/ 2375 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D 2376 2377 /** 2378 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1. 2379 2380 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E) 2381 @param EAX Lower 32-bits of MSR value. 2382 @param EDX Upper 32-bits of MSR value. 2383 2384 <b>Example usage</b> 2385 @code 2386 UINT64 Msr; 2387 2388 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000); 2389 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr); 2390 @endcode 2391 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM. 2392 **/ 2393 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E 2394 2395 /** 2396 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1. 2397 2398 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F) 2399 @param EAX Lower 32-bits of MSR value. 2400 @param EDX Upper 32-bits of MSR value. 2401 2402 <b>Example usage</b> 2403 @code 2404 UINT64 Msr; 2405 2406 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000); 2407 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr); 2408 @endcode 2409 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM. 2410 **/ 2411 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F 2412 2413 /** 2414 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1. 2415 2416 @param ECX MSR_IA32_PAT (0x00000277) 2417 @param EAX Lower 32-bits of MSR value. 2418 Described by the type MSR_IA32_PAT_REGISTER. 2419 @param EDX Upper 32-bits of MSR value. 2420 Described by the type MSR_IA32_PAT_REGISTER. 2421 2422 <b>Example usage</b> 2423 @code 2424 MSR_IA32_PAT_REGISTER Msr; 2425 2426 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT); 2427 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64); 2428 @endcode 2429 @note MSR_IA32_PAT is defined as IA32_PAT in SDM. 2430 **/ 2431 #define MSR_IA32_PAT 0x00000277 2432 2433 /** 2434 MSR information returned for MSR index #MSR_IA32_PAT 2435 **/ 2436 typedef union { 2437 /// 2438 /// Individual bit fields 2439 /// 2440 struct { 2441 /// 2442 /// [Bits 2:0] PA0. 2443 /// 2444 UINT32 PA0 : 3; 2445 UINT32 Reserved1 : 5; 2446 /// 2447 /// [Bits 10:8] PA1. 2448 /// 2449 UINT32 PA1 : 3; 2450 UINT32 Reserved2 : 5; 2451 /// 2452 /// [Bits 18:16] PA2. 2453 /// 2454 UINT32 PA2 : 3; 2455 UINT32 Reserved3 : 5; 2456 /// 2457 /// [Bits 26:24] PA3. 2458 /// 2459 UINT32 PA3 : 3; 2460 UINT32 Reserved4 : 5; 2461 /// 2462 /// [Bits 34:32] PA4. 2463 /// 2464 UINT32 PA4 : 3; 2465 UINT32 Reserved5 : 5; 2466 /// 2467 /// [Bits 42:40] PA5. 2468 /// 2469 UINT32 PA5 : 3; 2470 UINT32 Reserved6 : 5; 2471 /// 2472 /// [Bits 50:48] PA6. 2473 /// 2474 UINT32 PA6 : 3; 2475 UINT32 Reserved7 : 5; 2476 /// 2477 /// [Bits 58:56] PA7. 2478 /// 2479 UINT32 PA7 : 3; 2480 UINT32 Reserved8 : 5; 2481 } Bits; 2482 /// 2483 /// All bit fields as a 64-bit value 2484 /// 2485 UINT64 Uint64; 2486 } MSR_IA32_PAT_REGISTER; 2487 2488 /** 2489 Provides the programming interface to use corrected MC error signaling 2490 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n. 2491 2492 @param ECX MSR_IA32_MCn_CTL2 2493 @param EAX Lower 32-bits of MSR value. 2494 Described by the type MSR_IA32_MC_CTL2_REGISTER. 2495 @param EDX Upper 32-bits of MSR value. 2496 Described by the type MSR_IA32_MC_CTL2_REGISTER. 2497 2498 <b>Example usage</b> 2499 @code 2500 MSR_IA32_MC_CTL2_REGISTER Msr; 2501 2502 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2); 2503 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64); 2504 @endcode 2505 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. 2506 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. 2507 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. 2508 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. 2509 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. 2510 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. 2511 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. 2512 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. 2513 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. 2514 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. 2515 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. 2516 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. 2517 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. 2518 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. 2519 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. 2520 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. 2521 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. 2522 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. 2523 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. 2524 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. 2525 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. 2526 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. 2527 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. 2528 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. 2529 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. 2530 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. 2531 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. 2532 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. 2533 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. 2534 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. 2535 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. 2536 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM. 2537 @{ 2538 **/ 2539 #define MSR_IA32_MC0_CTL2 0x00000280 2540 #define MSR_IA32_MC1_CTL2 0x00000281 2541 #define MSR_IA32_MC2_CTL2 0x00000282 2542 #define MSR_IA32_MC3_CTL2 0x00000283 2543 #define MSR_IA32_MC4_CTL2 0x00000284 2544 #define MSR_IA32_MC5_CTL2 0x00000285 2545 #define MSR_IA32_MC6_CTL2 0x00000286 2546 #define MSR_IA32_MC7_CTL2 0x00000287 2547 #define MSR_IA32_MC8_CTL2 0x00000288 2548 #define MSR_IA32_MC9_CTL2 0x00000289 2549 #define MSR_IA32_MC10_CTL2 0x0000028A 2550 #define MSR_IA32_MC11_CTL2 0x0000028B 2551 #define MSR_IA32_MC12_CTL2 0x0000028C 2552 #define MSR_IA32_MC13_CTL2 0x0000028D 2553 #define MSR_IA32_MC14_CTL2 0x0000028E 2554 #define MSR_IA32_MC15_CTL2 0x0000028F 2555 #define MSR_IA32_MC16_CTL2 0x00000290 2556 #define MSR_IA32_MC17_CTL2 0x00000291 2557 #define MSR_IA32_MC18_CTL2 0x00000292 2558 #define MSR_IA32_MC19_CTL2 0x00000293 2559 #define MSR_IA32_MC20_CTL2 0x00000294 2560 #define MSR_IA32_MC21_CTL2 0x00000295 2561 #define MSR_IA32_MC22_CTL2 0x00000296 2562 #define MSR_IA32_MC23_CTL2 0x00000297 2563 #define MSR_IA32_MC24_CTL2 0x00000298 2564 #define MSR_IA32_MC25_CTL2 0x00000299 2565 #define MSR_IA32_MC26_CTL2 0x0000029A 2566 #define MSR_IA32_MC27_CTL2 0x0000029B 2567 #define MSR_IA32_MC28_CTL2 0x0000029C 2568 #define MSR_IA32_MC29_CTL2 0x0000029D 2569 #define MSR_IA32_MC30_CTL2 0x0000029E 2570 #define MSR_IA32_MC31_CTL2 0x0000029F 2571 /// @} 2572 2573 /** 2574 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 2575 to #MSR_IA32_MC31_CTL2 2576 **/ 2577 typedef union { 2578 /// 2579 /// Individual bit fields 2580 /// 2581 struct { 2582 /// 2583 /// [Bits 14:0] Corrected error count threshold. 2584 /// 2585 UINT32 CorrectedErrorCountThreshold : 15; 2586 UINT32 Reserved1 : 15; 2587 /// 2588 /// [Bit 30] CMCI_EN. 2589 /// 2590 UINT32 CMCI_EN : 1; 2591 UINT32 Reserved2 : 1; 2592 UINT32 Reserved3 : 32; 2593 } Bits; 2594 /// 2595 /// All bit fields as a 32-bit value 2596 /// 2597 UINT32 Uint32; 2598 /// 2599 /// All bit fields as a 64-bit value 2600 /// 2601 UINT64 Uint64; 2602 } MSR_IA32_MC_CTL2_REGISTER; 2603 2604 /** 2605 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1. 2606 2607 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF) 2608 @param EAX Lower 32-bits of MSR value. 2609 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. 2610 @param EDX Upper 32-bits of MSR value. 2611 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. 2612 2613 <b>Example usage</b> 2614 @code 2615 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr; 2616 2617 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); 2618 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64); 2619 @endcode 2620 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM. 2621 **/ 2622 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF 2623 2624 /** 2625 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE 2626 **/ 2627 typedef union { 2628 /// 2629 /// Individual bit fields 2630 /// 2631 struct { 2632 /// 2633 /// [Bits 2:0] Default Memory Type. 2634 /// 2635 UINT32 Type : 3; 2636 UINT32 Reserved1 : 7; 2637 /// 2638 /// [Bit 10] Fixed Range MTRR Enable. 2639 /// 2640 UINT32 FE : 1; 2641 /// 2642 /// [Bit 11] MTRR Enable. 2643 /// 2644 UINT32 E : 1; 2645 UINT32 Reserved2 : 20; 2646 UINT32 Reserved3 : 32; 2647 } Bits; 2648 /// 2649 /// All bit fields as a 32-bit value 2650 /// 2651 UINT32 Uint32; 2652 /// 2653 /// All bit fields as a 64-bit value 2654 /// 2655 UINT64 Uint64; 2656 } MSR_IA32_MTRR_DEF_TYPE_REGISTER; 2657 2658 /** 2659 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If 2660 CPUID.0AH: EDX[4:0] > 0. 2661 2662 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309) 2663 @param EAX Lower 32-bits of MSR value. 2664 @param EDX Upper 32-bits of MSR value. 2665 2666 <b>Example usage</b> 2667 @code 2668 UINT64 Msr; 2669 2670 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0); 2671 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr); 2672 @endcode 2673 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM. 2674 **/ 2675 #define MSR_IA32_FIXED_CTR0 0x00000309 2676 2677 /** 2678 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If 2679 CPUID.0AH: EDX[4:0] > 1. 2680 2681 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A) 2682 @param EAX Lower 32-bits of MSR value. 2683 @param EDX Upper 32-bits of MSR value. 2684 2685 <b>Example usage</b> 2686 @code 2687 UINT64 Msr; 2688 2689 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1); 2690 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr); 2691 @endcode 2692 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM. 2693 **/ 2694 #define MSR_IA32_FIXED_CTR1 0x0000030A 2695 2696 /** 2697 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If 2698 CPUID.0AH: EDX[4:0] > 2. 2699 2700 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B) 2701 @param EAX Lower 32-bits of MSR value. 2702 @param EDX Upper 32-bits of MSR value. 2703 2704 <b>Example usage</b> 2705 @code 2706 UINT64 Msr; 2707 2708 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2); 2709 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr); 2710 @endcode 2711 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM. 2712 **/ 2713 #define MSR_IA32_FIXED_CTR2 0x0000030B 2714 2715 /** 2716 RO. If CPUID.01H: ECX[15] = 1. 2717 2718 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345) 2719 @param EAX Lower 32-bits of MSR value. 2720 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. 2721 @param EDX Upper 32-bits of MSR value. 2722 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. 2723 2724 <b>Example usage</b> 2725 @code 2726 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr; 2727 2728 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES); 2729 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64); 2730 @endcode 2731 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM. 2732 **/ 2733 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 2734 2735 /** 2736 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES 2737 **/ 2738 typedef union { 2739 /// 2740 /// Individual bit fields 2741 /// 2742 struct { 2743 /// 2744 /// [Bits 5:0] LBR format. 2745 /// 2746 UINT32 LBR_FMT : 6; 2747 /// 2748 /// [Bit 6] PEBS Trap. 2749 /// 2750 UINT32 PEBS_TRAP : 1; 2751 /// 2752 /// [Bit 7] PEBSSaveArchRegs. 2753 /// 2754 UINT32 PEBS_ARCH_REG : 1; 2755 /// 2756 /// [Bits 11:8] PEBS Record Format. 2757 /// 2758 UINT32 PEBS_REC_FMT : 4; 2759 /// 2760 /// [Bit 12] 1: Freeze while SMM is supported. 2761 /// 2762 UINT32 SMM_FREEZE : 1; 2763 /// 2764 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx. 2765 /// 2766 UINT32 FW_WRITE : 1; 2767 UINT32 Reserved1 : 18; 2768 UINT32 Reserved2 : 32; 2769 } Bits; 2770 /// 2771 /// All bit fields as a 32-bit value 2772 /// 2773 UINT32 Uint32; 2774 /// 2775 /// All bit fields as a 64-bit value 2776 /// 2777 UINT64 Uint64; 2778 } MSR_IA32_PERF_CAPABILITIES_REGISTER; 2779 2780 /** 2781 Fixed-Function Performance Counter Control (R/W) Counter increments while 2782 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with 2783 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0] 2784 > 1. 2785 2786 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D) 2787 @param EAX Lower 32-bits of MSR value. 2788 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. 2789 @param EDX Upper 32-bits of MSR value. 2790 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. 2791 2792 <b>Example usage</b> 2793 @code 2794 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr; 2795 2796 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL); 2797 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64); 2798 @endcode 2799 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM. 2800 **/ 2801 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D 2802 2803 /** 2804 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL 2805 **/ 2806 typedef union { 2807 /// 2808 /// Individual bit fields 2809 /// 2810 struct { 2811 /// 2812 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. 2813 /// 2814 UINT32 EN0_OS : 1; 2815 /// 2816 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. 2817 /// 2818 UINT32 EN0_Usr : 1; 2819 /// 2820 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated 2821 /// event conditions occurring across all logical processors sharing a 2822 /// processor core. When set to 0, the counter only increments the 2823 /// associated event conditions occurring in the logical processor which 2824 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2825 /// 2826 UINT32 AnyThread0 : 1; 2827 /// 2828 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows. 2829 /// 2830 UINT32 EN0_PMI : 1; 2831 /// 2832 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0. 2833 /// 2834 UINT32 EN1_OS : 1; 2835 /// 2836 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0. 2837 /// 2838 UINT32 EN1_Usr : 1; 2839 /// 2840 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated 2841 /// event conditions occurring across all logical processors sharing a 2842 /// processor core. When set to 0, the counter only increments the 2843 /// associated event conditions occurring in the logical processor which 2844 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2845 /// 2846 UINT32 AnyThread1 : 1; 2847 /// 2848 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows. 2849 /// 2850 UINT32 EN1_PMI : 1; 2851 /// 2852 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. 2853 /// 2854 UINT32 EN2_OS : 1; 2855 /// 2856 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. 2857 /// 2858 UINT32 EN2_Usr : 1; 2859 /// 2860 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated 2861 /// event conditions occurring across all logical processors sharing a 2862 /// processor core. When set to 0, the counter only increments the 2863 /// associated event conditions occurring in the logical processor which 2864 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2865 /// 2866 UINT32 AnyThread2 : 1; 2867 /// 2868 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows. 2869 /// 2870 UINT32 EN2_PMI : 1; 2871 UINT32 Reserved1 : 20; 2872 UINT32 Reserved2 : 32; 2873 } Bits; 2874 /// 2875 /// All bit fields as a 32-bit value 2876 /// 2877 UINT32 Uint32; 2878 /// 2879 /// All bit fields as a 64-bit value 2880 /// 2881 UINT64 Uint64; 2882 } MSR_IA32_FIXED_CTR_CTRL_REGISTER; 2883 2884 /** 2885 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0. 2886 2887 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E) 2888 @param EAX Lower 32-bits of MSR value. 2889 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. 2890 @param EDX Upper 32-bits of MSR value. 2891 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. 2892 2893 <b>Example usage</b> 2894 @code 2895 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; 2896 2897 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS); 2898 @endcode 2899 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. 2900 **/ 2901 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E 2902 2903 /** 2904 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS 2905 **/ 2906 typedef union { 2907 /// 2908 /// Individual bit fields 2909 /// 2910 struct { 2911 /// 2912 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: 2913 /// EAX[15:8] > 0. 2914 /// 2915 UINT32 Ovf_PMC0 : 1; 2916 /// 2917 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: 2918 /// EAX[15:8] > 1. 2919 /// 2920 UINT32 Ovf_PMC1 : 1; 2921 /// 2922 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: 2923 /// EAX[15:8] > 2. 2924 /// 2925 UINT32 Ovf_PMC2 : 1; 2926 /// 2927 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: 2928 /// EAX[15:8] > 3. 2929 /// 2930 UINT32 Ovf_PMC3 : 1; 2931 UINT32 Reserved1 : 28; 2932 /// 2933 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If 2934 /// CPUID.0AH: EAX[7:0] > 1. 2935 /// 2936 UINT32 Ovf_FixedCtr0 : 1; 2937 /// 2938 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If 2939 /// CPUID.0AH: EAX[7:0] > 1. 2940 /// 2941 UINT32 Ovf_FixedCtr1 : 1; 2942 /// 2943 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If 2944 /// CPUID.0AH: EAX[7:0] > 1. 2945 /// 2946 UINT32 Ovf_FixedCtr2 : 1; 2947 UINT32 Reserved2 : 20; 2948 /// 2949 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory 2950 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) 2951 /// && IA32_RTIT_CTL.ToPA = 1. 2952 /// 2953 UINT32 Trace_ToPA_PMI : 1; 2954 UINT32 Reserved3 : 2; 2955 /// 2956 /// [Bit 58] LBR_Frz: LBRs are frozen due to - 2957 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If 2958 /// CPUID.0AH: EAX[7:0] > 3. 2959 /// 2960 UINT32 LBR_Frz : 1; 2961 /// 2962 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due 2963 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU 2964 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3. 2965 /// 2966 UINT32 CTR_Frz : 1; 2967 /// 2968 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may 2969 /// include contributions from the direct or indirect operation intel SGX 2970 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1. 2971 /// 2972 UINT32 ASCI : 1; 2973 /// 2974 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: 2975 /// EAX[7:0] > 2. 2976 /// 2977 UINT32 Ovf_Uncore : 1; 2978 /// 2979 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: 2980 /// EAX[7:0] > 0. 2981 /// 2982 UINT32 OvfBuf : 1; 2983 /// 2984 /// [Bit 63] CondChgd: status bits of this register has changed. If 2985 /// CPUID.0AH: EAX[7:0] > 0. 2986 /// 2987 UINT32 CondChgd : 1; 2988 } Bits; 2989 /// 2990 /// All bit fields as a 64-bit value 2991 /// 2992 UINT64 Uint64; 2993 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER; 2994 2995 /** 2996 Global Performance Counter Control (R/W) Counter increments while the result 2997 of ANDing respective enable bit in this MSR with the corresponding OS or USR 2998 bits in the general-purpose or fixed counter control MSR is true. If 2999 CPUID.0AH: EAX[7:0] > 0. 3000 3001 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F) 3002 @param EAX Lower 32-bits of MSR value. 3003 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. 3004 @param EDX Upper 32-bits of MSR value. 3005 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. 3006 3007 <b>Example usage</b> 3008 @code 3009 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; 3010 3011 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL); 3012 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); 3013 @endcode 3014 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. 3015 **/ 3016 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F 3017 3018 /** 3019 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL 3020 **/ 3021 typedef union { 3022 /// 3023 /// Individual bit fields 3024 /// 3025 struct { 3026 /// 3027 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. 3028 /// Enable bitmask. Only the first n-1 bits are valid. 3029 /// Bits n..31 are reserved. 3030 /// 3031 UINT32 EN_PMCn : 32; 3032 /// 3033 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. 3034 /// Enable bitmask. Only the first n-1 bits are valid. 3035 /// Bits 31:n are reserved. 3036 /// 3037 UINT32 EN_FIXED_CTRn : 32; 3038 } Bits; 3039 /// 3040 /// All bit fields as a 64-bit value 3041 /// 3042 UINT64 Uint64; 3043 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER; 3044 3045 /** 3046 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > 3047 0 && CPUID.0AH: EAX[7:0] <= 3. 3048 3049 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) 3050 @param EAX Lower 32-bits of MSR value. 3051 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 3052 @param EDX Upper 32-bits of MSR value. 3053 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 3054 3055 <b>Example usage</b> 3056 @code 3057 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; 3058 3059 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL); 3060 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); 3061 @endcode 3062 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. 3063 **/ 3064 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 3065 3066 /** 3067 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL 3068 **/ 3069 typedef union { 3070 /// 3071 /// Individual bit fields 3072 /// 3073 struct { 3074 /// 3075 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. 3076 /// Clear bitmask. Only the first n-1 bits are valid. 3077 /// Bits 31:n are reserved. 3078 /// 3079 UINT32 Ovf_PMCn : 32; 3080 /// 3081 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. 3082 /// If CPUID.0AH: EDX[4:0] > n. 3083 /// Clear bitmask. Only the first n-1 bits are valid. 3084 /// Bits 22:n are reserved. 3085 /// 3086 UINT32 Ovf_FIXED_CTRn : 23; 3087 /// 3088 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, 3089 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1. 3090 /// 3091 UINT32 Trace_ToPA_PMI : 1; 3092 UINT32 Reserved2 : 5; 3093 /// 3094 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / 3095 /// Display Model 06_2EH. 3096 /// 3097 UINT32 Ovf_Uncore : 1; 3098 /// 3099 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. 3100 /// 3101 UINT32 OvfBuf : 1; 3102 /// 3103 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. 3104 /// 3105 UINT32 CondChgd : 1; 3106 } Bits; 3107 /// 3108 /// All bit fields as a 64-bit value 3109 /// 3110 UINT64 Uint64; 3111 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; 3112 3113 /** 3114 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: 3115 EAX[7:0] > 3. 3116 3117 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) 3118 @param EAX Lower 32-bits of MSR value. 3119 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 3120 @param EDX Upper 32-bits of MSR value. 3121 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 3122 3123 <b>Example usage</b> 3124 @code 3125 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; 3126 3127 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET); 3128 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); 3129 @endcode 3130 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. 3131 **/ 3132 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 3133 3134 /** 3135 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET 3136 **/ 3137 typedef union { 3138 /// 3139 /// Individual bit fields 3140 /// 3141 struct { 3142 /// 3143 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. 3144 /// Clear bitmask. Only the first n-1 bits are valid. 3145 /// Bits 31:n are reserved. 3146 /// 3147 UINT32 Ovf_PMCn : 32; 3148 /// 3149 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. 3150 /// If CPUID.0AH: EDX[4:0] > n. 3151 /// Clear bitmask. Only the first n-1 bits are valid. 3152 /// Bits 22:n are reserved. 3153 /// 3154 UINT32 Ovf_FIXED_CTRn : 23; 3155 /// 3156 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, 3157 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1. 3158 /// 3159 UINT32 Trace_ToPA_PMI : 1; 3160 UINT32 Reserved2 : 2; 3161 /// 3162 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. 3163 /// 3164 UINT32 LBR_Frz : 1; 3165 /// 3166 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. 3167 /// 3168 UINT32 CTR_Frz : 1; 3169 /// 3170 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3. 3171 /// 3172 UINT32 ASCI : 1; 3173 /// 3174 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / 3175 /// Display Model 06_2EH. 3176 /// 3177 UINT32 Ovf_Uncore : 1; 3178 /// 3179 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. 3180 /// 3181 UINT32 OvfBuf : 1; 3182 /// 3183 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. 3184 /// 3185 UINT32 CondChgd : 1; 3186 } Bits; 3187 /// 3188 /// All bit fields as a 64-bit value 3189 /// 3190 UINT64 Uint64; 3191 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; 3192 3193 /** 3194 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: 3195 EAX[7:0] > 3. 3196 3197 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) 3198 @param EAX Lower 32-bits of MSR value. 3199 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 3200 @param EDX Upper 32-bits of MSR value. 3201 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 3202 3203 <b>Example usage</b> 3204 @code 3205 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; 3206 3207 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET); 3208 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); 3209 @endcode 3210 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. 3211 **/ 3212 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 3213 3214 /** 3215 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET 3216 **/ 3217 typedef union { 3218 /// 3219 /// Individual bit fields 3220 /// 3221 struct { 3222 /// 3223 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. 3224 /// Set bitmask. Only the first n-1 bits are valid. 3225 /// Bits 31:n are reserved. 3226 /// 3227 UINT32 Ovf_PMCn : 32; 3228 /// 3229 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. 3230 /// If CPUID.0AH: EAX[7:0] > n. 3231 /// Set bitmask. Only the first n-1 bits are valid. 3232 /// Bits 22:n are reserved. 3233 /// 3234 UINT32 Ovf_FIXED_CTRn : 23; 3235 /// 3236 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3. 3237 /// 3238 UINT32 Trace_ToPA_PMI : 1; 3239 UINT32 Reserved2 : 2; 3240 /// 3241 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. 3242 /// 3243 UINT32 LBR_Frz : 1; 3244 /// 3245 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. 3246 /// 3247 UINT32 CTR_Frz : 1; 3248 /// 3249 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3. 3250 /// 3251 UINT32 ASCI : 1; 3252 /// 3253 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3. 3254 /// 3255 UINT32 Ovf_Uncore : 1; 3256 /// 3257 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3. 3258 /// 3259 UINT32 OvfBuf : 1; 3260 UINT32 Reserved3 : 1; 3261 } Bits; 3262 /// 3263 /// All bit fields as a 64-bit value 3264 /// 3265 UINT64 Uint64; 3266 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; 3267 3268 /** 3269 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > 3270 3. 3271 3272 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392) 3273 @param EAX Lower 32-bits of MSR value. 3274 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. 3275 @param EDX Upper 32-bits of MSR value. 3276 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. 3277 3278 <b>Example usage</b> 3279 @code 3280 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr; 3281 3282 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE); 3283 @endcode 3284 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM. 3285 **/ 3286 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392 3287 3288 /** 3289 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE 3290 **/ 3291 typedef union { 3292 /// 3293 /// Individual bit fields 3294 /// 3295 struct { 3296 /// 3297 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. 3298 /// Status bitmask. Only the first n-1 bits are valid. 3299 /// Bits 31:n are reserved. 3300 /// 3301 UINT32 IA32_PERFEVTSELn : 32; 3302 /// 3303 /// [Bits 62:32] IA32_FIXED_CTRn in use. 3304 /// If CPUID.0AH: EAX[7:0] > n. 3305 /// Status bitmask. Only the first n-1 bits are valid. 3306 /// Bits 30:n are reserved. 3307 /// 3308 UINT32 IA32_FIXED_CTRn : 31; 3309 /// 3310 /// [Bit 63] PMI in use. 3311 /// 3312 UINT32 PMI : 1; 3313 } Bits; 3314 /// 3315 /// All bit fields as a 64-bit value 3316 /// 3317 UINT64 Uint64; 3318 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER; 3319 3320 /** 3321 PEBS Control (R/W). 3322 3323 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1) 3324 @param EAX Lower 32-bits of MSR value. 3325 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. 3326 @param EDX Upper 32-bits of MSR value. 3327 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. 3328 3329 <b>Example usage</b> 3330 @code 3331 MSR_IA32_PEBS_ENABLE_REGISTER Msr; 3332 3333 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE); 3334 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64); 3335 @endcode 3336 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM. 3337 **/ 3338 #define MSR_IA32_PEBS_ENABLE 0x000003F1 3339 3340 /** 3341 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE 3342 **/ 3343 typedef union { 3344 /// 3345 /// Individual bit fields 3346 /// 3347 struct { 3348 /// 3349 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / 3350 /// Display Model 06_0FH. 3351 /// 3352 UINT32 Enable : 1; 3353 /// 3354 /// [Bits 3:1] Reserved or Model specific. 3355 /// 3356 UINT32 Reserved1 : 3; 3357 UINT32 Reserved2 : 28; 3358 /// 3359 /// [Bits 35:32] Reserved or Model specific. 3360 /// 3361 UINT32 Reserved3 : 4; 3362 UINT32 Reserved4 : 28; 3363 } Bits; 3364 /// 3365 /// All bit fields as a 64-bit value 3366 /// 3367 UINT64 Uint64; 3368 } MSR_IA32_PEBS_ENABLE_REGISTER; 3369 3370 /** 3371 MCn_CTL. If IA32_MCG_CAP.CNT > n. 3372 3373 @param ECX MSR_IA32_MCn_CTL 3374 @param EAX Lower 32-bits of MSR value. 3375 @param EDX Upper 32-bits of MSR value. 3376 3377 <b>Example usage</b> 3378 @code 3379 UINT64 Msr; 3380 3381 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL); 3382 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr); 3383 @endcode 3384 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. 3385 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. 3386 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. 3387 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. 3388 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. 3389 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. 3390 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. 3391 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. 3392 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. 3393 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. 3394 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. 3395 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. 3396 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. 3397 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. 3398 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. 3399 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. 3400 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. 3401 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. 3402 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. 3403 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. 3404 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. 3405 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. 3406 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. 3407 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. 3408 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. 3409 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. 3410 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. 3411 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. 3412 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM. 3413 @{ 3414 **/ 3415 #define MSR_IA32_MC0_CTL 0x00000400 3416 #define MSR_IA32_MC1_CTL 0x00000404 3417 #define MSR_IA32_MC2_CTL 0x00000408 3418 #define MSR_IA32_MC3_CTL 0x0000040C 3419 #define MSR_IA32_MC4_CTL 0x00000410 3420 #define MSR_IA32_MC5_CTL 0x00000414 3421 #define MSR_IA32_MC6_CTL 0x00000418 3422 #define MSR_IA32_MC7_CTL 0x0000041C 3423 #define MSR_IA32_MC8_CTL 0x00000420 3424 #define MSR_IA32_MC9_CTL 0x00000424 3425 #define MSR_IA32_MC10_CTL 0x00000428 3426 #define MSR_IA32_MC11_CTL 0x0000042C 3427 #define MSR_IA32_MC12_CTL 0x00000430 3428 #define MSR_IA32_MC13_CTL 0x00000434 3429 #define MSR_IA32_MC14_CTL 0x00000438 3430 #define MSR_IA32_MC15_CTL 0x0000043C 3431 #define MSR_IA32_MC16_CTL 0x00000440 3432 #define MSR_IA32_MC17_CTL 0x00000444 3433 #define MSR_IA32_MC18_CTL 0x00000448 3434 #define MSR_IA32_MC19_CTL 0x0000044C 3435 #define MSR_IA32_MC20_CTL 0x00000450 3436 #define MSR_IA32_MC21_CTL 0x00000454 3437 #define MSR_IA32_MC22_CTL 0x00000458 3438 #define MSR_IA32_MC23_CTL 0x0000045C 3439 #define MSR_IA32_MC24_CTL 0x00000460 3440 #define MSR_IA32_MC25_CTL 0x00000464 3441 #define MSR_IA32_MC26_CTL 0x00000468 3442 #define MSR_IA32_MC27_CTL 0x0000046C 3443 #define MSR_IA32_MC28_CTL 0x00000470 3444 /// @} 3445 3446 /** 3447 MCn_STATUS. If IA32_MCG_CAP.CNT > n. 3448 3449 @param ECX MSR_IA32_MCn_STATUS 3450 @param EAX Lower 32-bits of MSR value. 3451 @param EDX Upper 32-bits of MSR value. 3452 3453 <b>Example usage</b> 3454 @code 3455 UINT64 Msr; 3456 3457 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS); 3458 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr); 3459 @endcode 3460 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. 3461 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. 3462 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. 3463 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. 3464 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. 3465 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. 3466 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. 3467 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. 3468 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. 3469 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. 3470 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. 3471 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. 3472 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. 3473 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. 3474 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. 3475 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. 3476 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. 3477 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. 3478 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. 3479 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. 3480 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. 3481 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. 3482 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. 3483 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. 3484 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. 3485 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. 3486 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. 3487 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. 3488 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM. 3489 @{ 3490 **/ 3491 #define MSR_IA32_MC0_STATUS 0x00000401 3492 #define MSR_IA32_MC1_STATUS 0x00000405 3493 #define MSR_IA32_MC2_STATUS 0x00000409 3494 #define MSR_IA32_MC3_STATUS 0x0000040D 3495 #define MSR_IA32_MC4_STATUS 0x00000411 3496 #define MSR_IA32_MC5_STATUS 0x00000415 3497 #define MSR_IA32_MC6_STATUS 0x00000419 3498 #define MSR_IA32_MC7_STATUS 0x0000041D 3499 #define MSR_IA32_MC8_STATUS 0x00000421 3500 #define MSR_IA32_MC9_STATUS 0x00000425 3501 #define MSR_IA32_MC10_STATUS 0x00000429 3502 #define MSR_IA32_MC11_STATUS 0x0000042D 3503 #define MSR_IA32_MC12_STATUS 0x00000431 3504 #define MSR_IA32_MC13_STATUS 0x00000435 3505 #define MSR_IA32_MC14_STATUS 0x00000439 3506 #define MSR_IA32_MC15_STATUS 0x0000043D 3507 #define MSR_IA32_MC16_STATUS 0x00000441 3508 #define MSR_IA32_MC17_STATUS 0x00000445 3509 #define MSR_IA32_MC18_STATUS 0x00000449 3510 #define MSR_IA32_MC19_STATUS 0x0000044D 3511 #define MSR_IA32_MC20_STATUS 0x00000451 3512 #define MSR_IA32_MC21_STATUS 0x00000455 3513 #define MSR_IA32_MC22_STATUS 0x00000459 3514 #define MSR_IA32_MC23_STATUS 0x0000045D 3515 #define MSR_IA32_MC24_STATUS 0x00000461 3516 #define MSR_IA32_MC25_STATUS 0x00000465 3517 #define MSR_IA32_MC26_STATUS 0x00000469 3518 #define MSR_IA32_MC27_STATUS 0x0000046D 3519 #define MSR_IA32_MC28_STATUS 0x00000471 3520 /// @} 3521 3522 /** 3523 MCn_ADDR. If IA32_MCG_CAP.CNT > n. 3524 3525 @param ECX MSR_IA32_MCn_ADDR 3526 @param EAX Lower 32-bits of MSR value. 3527 @param EDX Upper 32-bits of MSR value. 3528 3529 <b>Example usage</b> 3530 @code 3531 UINT64 Msr; 3532 3533 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR); 3534 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr); 3535 @endcode 3536 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. 3537 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. 3538 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. 3539 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. 3540 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. 3541 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. 3542 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. 3543 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. 3544 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. 3545 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. 3546 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. 3547 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. 3548 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. 3549 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. 3550 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. 3551 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. 3552 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. 3553 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. 3554 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. 3555 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. 3556 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. 3557 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. 3558 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. 3559 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. 3560 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. 3561 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. 3562 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. 3563 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. 3564 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM. 3565 @{ 3566 **/ 3567 #define MSR_IA32_MC0_ADDR 0x00000402 3568 #define MSR_IA32_MC1_ADDR 0x00000406 3569 #define MSR_IA32_MC2_ADDR 0x0000040A 3570 #define MSR_IA32_MC3_ADDR 0x0000040E 3571 #define MSR_IA32_MC4_ADDR 0x00000412 3572 #define MSR_IA32_MC5_ADDR 0x00000416 3573 #define MSR_IA32_MC6_ADDR 0x0000041A 3574 #define MSR_IA32_MC7_ADDR 0x0000041E 3575 #define MSR_IA32_MC8_ADDR 0x00000422 3576 #define MSR_IA32_MC9_ADDR 0x00000426 3577 #define MSR_IA32_MC10_ADDR 0x0000042A 3578 #define MSR_IA32_MC11_ADDR 0x0000042E 3579 #define MSR_IA32_MC12_ADDR 0x00000432 3580 #define MSR_IA32_MC13_ADDR 0x00000436 3581 #define MSR_IA32_MC14_ADDR 0x0000043A 3582 #define MSR_IA32_MC15_ADDR 0x0000043E 3583 #define MSR_IA32_MC16_ADDR 0x00000442 3584 #define MSR_IA32_MC17_ADDR 0x00000446 3585 #define MSR_IA32_MC18_ADDR 0x0000044A 3586 #define MSR_IA32_MC19_ADDR 0x0000044E 3587 #define MSR_IA32_MC20_ADDR 0x00000452 3588 #define MSR_IA32_MC21_ADDR 0x00000456 3589 #define MSR_IA32_MC22_ADDR 0x0000045A 3590 #define MSR_IA32_MC23_ADDR 0x0000045E 3591 #define MSR_IA32_MC24_ADDR 0x00000462 3592 #define MSR_IA32_MC25_ADDR 0x00000466 3593 #define MSR_IA32_MC26_ADDR 0x0000046A 3594 #define MSR_IA32_MC27_ADDR 0x0000046E 3595 #define MSR_IA32_MC28_ADDR 0x00000472 3596 /// @} 3597 3598 /** 3599 MCn_MISC. If IA32_MCG_CAP.CNT > n. 3600 3601 @param ECX MSR_IA32_MCn_MISC 3602 @param EAX Lower 32-bits of MSR value. 3603 @param EDX Upper 32-bits of MSR value. 3604 3605 <b>Example usage</b> 3606 @code 3607 UINT64 Msr; 3608 3609 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC); 3610 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr); 3611 @endcode 3612 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. 3613 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. 3614 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. 3615 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. 3616 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. 3617 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. 3618 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. 3619 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. 3620 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. 3621 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. 3622 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. 3623 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. 3624 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. 3625 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. 3626 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. 3627 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. 3628 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. 3629 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. 3630 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. 3631 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. 3632 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. 3633 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. 3634 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. 3635 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. 3636 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. 3637 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. 3638 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. 3639 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. 3640 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM. 3641 @{ 3642 **/ 3643 #define MSR_IA32_MC0_MISC 0x00000403 3644 #define MSR_IA32_MC1_MISC 0x00000407 3645 #define MSR_IA32_MC2_MISC 0x0000040B 3646 #define MSR_IA32_MC3_MISC 0x0000040F 3647 #define MSR_IA32_MC4_MISC 0x00000413 3648 #define MSR_IA32_MC5_MISC 0x00000417 3649 #define MSR_IA32_MC6_MISC 0x0000041B 3650 #define MSR_IA32_MC7_MISC 0x0000041F 3651 #define MSR_IA32_MC8_MISC 0x00000423 3652 #define MSR_IA32_MC9_MISC 0x00000427 3653 #define MSR_IA32_MC10_MISC 0x0000042B 3654 #define MSR_IA32_MC11_MISC 0x0000042F 3655 #define MSR_IA32_MC12_MISC 0x00000433 3656 #define MSR_IA32_MC13_MISC 0x00000437 3657 #define MSR_IA32_MC14_MISC 0x0000043B 3658 #define MSR_IA32_MC15_MISC 0x0000043F 3659 #define MSR_IA32_MC16_MISC 0x00000443 3660 #define MSR_IA32_MC17_MISC 0x00000447 3661 #define MSR_IA32_MC18_MISC 0x0000044B 3662 #define MSR_IA32_MC19_MISC 0x0000044F 3663 #define MSR_IA32_MC20_MISC 0x00000453 3664 #define MSR_IA32_MC21_MISC 0x00000457 3665 #define MSR_IA32_MC22_MISC 0x0000045B 3666 #define MSR_IA32_MC23_MISC 0x0000045F 3667 #define MSR_IA32_MC24_MISC 0x00000463 3668 #define MSR_IA32_MC25_MISC 0x00000467 3669 #define MSR_IA32_MC26_MISC 0x0000046B 3670 #define MSR_IA32_MC27_MISC 0x0000046F 3671 #define MSR_IA32_MC28_MISC 0x00000473 3672 /// @} 3673 3674 /** 3675 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic 3676 VMX Information.". If CPUID.01H:ECX.[5] = 1. 3677 3678 @param ECX MSR_IA32_VMX_BASIC (0x00000480) 3679 @param EAX Lower 32-bits of MSR value. 3680 @param EDX Upper 32-bits of MSR value. 3681 3682 <b>Example usage</b> 3683 @code 3684 MSR_IA32_VMX_BASIC_REGISTER Msr; 3685 3686 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC); 3687 @endcode 3688 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. 3689 **/ 3690 #define MSR_IA32_VMX_BASIC 0x00000480 3691 3692 /** 3693 MSR information returned for MSR index #MSR_IA32_VMX_BASIC 3694 **/ 3695 typedef union { 3696 /// 3697 /// Individual bit fields 3698 /// 3699 struct { 3700 /// 3701 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors 3702 /// that use the same VMCS revision identifier use the same size for VMCS 3703 /// regions (see subsequent item on bits 44:32). 3704 /// 3705 /// @note Earlier versions of this manual specified that the VMCS revision 3706 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all 3707 /// processors produced prior to this change, bit 31 of this MSR was read 3708 /// as 0. 3709 /// 3710 UINT32 VmcsRevisonId : 31; 3711 UINT32 MustBeZero : 1; 3712 /// 3713 /// [Bit 44:32] Reports the number of bytes that software should allocate 3714 /// for the VMXON region and any VMCS region. It is a value greater than 3715 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear). 3716 /// 3717 UINT32 VmcsSize : 13; 3718 UINT32 Reserved1 : 3; 3719 /// 3720 /// [Bit 48] Indicates the width of the physical addresses that may be used 3721 /// for the VMXON region, each VMCS, and data structures referenced by 3722 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX 3723 /// transitions). If the bit is 0, these addresses are limited to the 3724 /// processor's physical-address width. If the bit is 1, these addresses 3725 /// are limited to 32 bits. This bit is always 0 for processors that 3726 /// support Intel 64 architecture. 3727 /// 3728 /// @note On processors that support Intel 64 architecture, the pointer 3729 /// must not set bits beyond the processor's physical address width. 3730 /// 3731 UINT32 VmcsAddressWidth : 1; 3732 /// 3733 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the 3734 /// dual-monitor treatment of system-management interrupts and 3735 /// system-management mode. See Section 34.15 for details of this treatment. 3736 /// 3737 UINT32 DualMonitor : 1; 3738 /// 3739 /// [Bit 53:50] report the memory type that should be used for the VMCS, 3740 /// for data structures referenced by pointers in the VMCS (I/O bitmaps, 3741 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG 3742 /// header. If software needs to access these data structures (e.g., to 3743 /// modify the contents of the MSR bitmaps), it can configure the paging 3744 /// structures to map them into the linear-address space. If it does so, 3745 /// it should establish mappings that use the memory type reported bits 3746 /// 53:50 in this MSR. 3747 /// 3748 /// As of this writing, all processors that support VMX operation indicate 3749 /// the write-back type. 3750 /// 3751 /// If software needs to access these data structures (e.g., to modify 3752 /// the contents of the MSR bitmaps), it can configure the paging 3753 /// structures to map them into the linear-address space. If it does so, 3754 /// it should establish mappings that use the memory type reported in this 3755 /// MSR. 3756 /// 3757 /// @note Alternatively, software may map any of these regions or 3758 /// structures with the UC memory type. (This may be necessary for the MSEG 3759 /// header.) Doing so is discouraged unless necessary as it will cause the 3760 /// performance of software accesses to those structures to suffer. 3761 /// 3762 /// 3763 UINT32 MemoryType : 4; 3764 /// 3765 /// [Bit 54] If bit 54 is read as 1, the processor reports information in 3766 /// the VM-exit instruction-information field on VM exitsdue to execution 3767 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting 3768 /// is done only if this bit is read as 1. 3769 /// 3770 UINT32 InsOutsReporting : 1; 3771 /// 3772 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may 3773 /// be cleared to 0. See Appendix A.2 for details. It also reports support 3774 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, 3775 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and 3776 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, 3777 /// Appendix A.4, and Appendix A.5 for details. 3778 /// 3779 UINT32 VmxControls : 1; 3780 UINT32 Reserved2 : 8; 3781 } Bits; 3782 /// 3783 /// All bit fields as a 64-bit value 3784 /// 3785 UINT64 Uint64; 3786 } MSR_IA32_VMX_BASIC_REGISTER; 3787 3788 /// 3789 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType 3790 /// 3791 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 3792 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 3793 /// 3794 /// @} 3795 /// 3796 3797 /** 3798 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See 3799 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1. 3800 3801 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481) 3802 @param EAX Lower 32-bits of MSR value. 3803 @param EDX Upper 32-bits of MSR value. 3804 3805 <b>Example usage</b> 3806 @code 3807 UINT64 Msr; 3808 3809 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS); 3810 @endcode 3811 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM. 3812 **/ 3813 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 3814 3815 /** 3816 Capability Reporting Register of Primary Processor-based VM-execution 3817 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution 3818 Controls.". If CPUID.01H:ECX.[5] = 1. 3819 3820 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482) 3821 @param EAX Lower 32-bits of MSR value. 3822 @param EDX Upper 32-bits of MSR value. 3823 3824 <b>Example usage</b> 3825 @code 3826 UINT64 Msr; 3827 3828 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS); 3829 @endcode 3830 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM. 3831 **/ 3832 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 3833 3834 /** 3835 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, 3836 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1. 3837 3838 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483) 3839 @param EAX Lower 32-bits of MSR value. 3840 @param EDX Upper 32-bits of MSR value. 3841 3842 <b>Example usage</b> 3843 @code 3844 UINT64 Msr; 3845 3846 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS); 3847 @endcode 3848 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM. 3849 **/ 3850 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 3851 3852 /** 3853 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, 3854 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1. 3855 3856 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484) 3857 @param EAX Lower 32-bits of MSR value. 3858 @param EDX Upper 32-bits of MSR value. 3859 3860 <b>Example usage</b> 3861 @code 3862 UINT64 Msr; 3863 3864 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS); 3865 @endcode 3866 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM. 3867 **/ 3868 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 3869 3870 /** 3871 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, 3872 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1. 3873 3874 @param ECX MSR_IA32_VMX_MISC (0x00000485) 3875 @param EAX Lower 32-bits of MSR value. 3876 @param EDX Upper 32-bits of MSR value. 3877 3878 <b>Example usage</b> 3879 @code 3880 IA32_VMX_MISC_REGISTER Msr; 3881 3882 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); 3883 @endcode 3884 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. 3885 **/ 3886 #define MSR_IA32_VMX_MISC 0x00000485 3887 3888 /** 3889 MSR information returned for MSR index #IA32_VMX_MISC 3890 **/ 3891 typedef union { 3892 /// 3893 /// Individual bit fields 3894 /// 3895 struct { 3896 /// 3897 /// [Bits 4:0] Reports a value X that specifies the relationship between the 3898 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC). 3899 /// Specifically, the VMX-preemption timer (if it is active) counts down by 3900 /// 1 every time bit X in the TSC changes due to a TSC increment. 3901 /// 3902 UINT32 VmxTimerRatio : 5; 3903 /// 3904 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA 3905 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more 3906 /// details. This bit is read as 1 on any logical processor that supports 3907 /// the 1-setting of the "unrestricted guest" VM-execution control. 3908 /// 3909 UINT32 VmExitEferLma : 1; 3910 /// 3911 /// [Bit 6] reports (if set) the support for activity state 1 (HLT). 3912 /// 3913 UINT32 HltActivityStateSupported : 1; 3914 /// 3915 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown). 3916 /// 3917 UINT32 ShutdownActivityStateSupported : 1; 3918 /// 3919 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI). 3920 /// 3921 UINT32 WaitForSipiActivityStateSupported : 1; 3922 UINT32 Reserved1 : 5; 3923 /// 3924 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used 3925 /// in VMX operation. If the processor supports Intel PT but does not allow 3926 /// it to be used in VMX operation, execution of VMXON clears 3927 /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); 3928 /// any attempt to set that bit while in VMX operation (including VMX root 3929 /// operation) using the WRMSR instruction causes a general-protection 3930 /// exception. 3931 /// 3932 UINT32 ProcessorTraceSupported : 1; 3933 /// 3934 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system- 3935 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). 3936 /// See Section 34.15.6.3. 3937 /// 3938 UINT32 SmBaseMsrSupported : 1; 3939 /// 3940 /// [Bits 24:16] Indicate the number of CR3-target values supported by the 3941 /// processor. This number is a value between 0 and 256, inclusive (bit 24 3942 /// is set if and only if bits 23:16 are clear). 3943 /// 3944 UINT32 NumberOfCr3TargetValues : 9; 3945 /// 3946 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum 3947 /// number of MSRs that should appear in the VM-exit MSR-store list, the 3948 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if 3949 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the 3950 /// recommended maximum number of MSRs to be included in each list. If the 3951 /// limit is exceeded, undefined processor behavior may result (including a 3952 /// machine check during the VMX transition). 3953 /// 3954 UINT32 MsrStoreListMaximum : 3; 3955 /// 3956 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set 3957 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 3958 /// (see Section 34.14.4). 3959 /// 3960 UINT32 BlockSmiSupported : 1; 3961 /// 3962 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported 3963 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit 3964 /// information fields. 3965 /// 3966 UINT32 VmWriteSupported : 1; 3967 /// 3968 /// [Bit 30] If read as 1, VM entry allows injection of a software 3969 /// interrupt, software exception, or privileged software exception with an 3970 /// instruction length of 0. 3971 /// 3972 UINT32 VmInjectSupported : 1; 3973 UINT32 Reserved2 : 1; 3974 /// 3975 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the 3976 /// processor. 3977 /// 3978 UINT32 MsegRevisionIdentifier : 32; 3979 } Bits; 3980 /// 3981 /// All bit fields as a 64-bit value 3982 /// 3983 UINT64 Uint64; 3984 } IA32_VMX_MISC_REGISTER; 3985 3986 /** 3987 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, 3988 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. 3989 3990 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486) 3991 @param EAX Lower 32-bits of MSR value. 3992 @param EDX Upper 32-bits of MSR value. 3993 3994 <b>Example usage</b> 3995 @code 3996 UINT64 Msr; 3997 3998 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0); 3999 @endcode 4000 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM. 4001 **/ 4002 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 4003 4004 /** 4005 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, 4006 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. 4007 4008 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487) 4009 @param EAX Lower 32-bits of MSR value. 4010 @param EDX Upper 32-bits of MSR value. 4011 4012 <b>Example usage</b> 4013 @code 4014 UINT64 Msr; 4015 4016 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1); 4017 @endcode 4018 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM. 4019 **/ 4020 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 4021 4022 /** 4023 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, 4024 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. 4025 4026 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488) 4027 @param EAX Lower 32-bits of MSR value. 4028 @param EDX Upper 32-bits of MSR value. 4029 4030 <b>Example usage</b> 4031 @code 4032 UINT64 Msr; 4033 4034 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0); 4035 @endcode 4036 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM. 4037 **/ 4038 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 4039 4040 /** 4041 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, 4042 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. 4043 4044 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489) 4045 @param EAX Lower 32-bits of MSR value. 4046 @param EDX Upper 32-bits of MSR value. 4047 4048 <b>Example usage</b> 4049 @code 4050 UINT64 Msr; 4051 4052 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1); 4053 @endcode 4054 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM. 4055 **/ 4056 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 4057 4058 /** 4059 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix 4060 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1. 4061 4062 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A) 4063 @param EAX Lower 32-bits of MSR value. 4064 @param EDX Upper 32-bits of MSR value. 4065 4066 <b>Example usage</b> 4067 @code 4068 UINT64 Msr; 4069 4070 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM); 4071 @endcode 4072 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM. 4073 **/ 4074 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A 4075 4076 /** 4077 Capability Reporting Register of Secondary Processor-based VM-execution 4078 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution 4079 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]). 4080 4081 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B) 4082 @param EAX Lower 32-bits of MSR value. 4083 @param EDX Upper 32-bits of MSR value. 4084 4085 <b>Example usage</b> 4086 @code 4087 UINT64 Msr; 4088 4089 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2); 4090 @endcode 4091 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM. 4092 **/ 4093 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B 4094 4095 /** 4096 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10, 4097 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C 4098 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ). 4099 4100 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C) 4101 @param EAX Lower 32-bits of MSR value. 4102 @param EDX Upper 32-bits of MSR value. 4103 4104 <b>Example usage</b> 4105 @code 4106 UINT64 Msr; 4107 4108 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP); 4109 @endcode 4110 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM. 4111 **/ 4112 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C 4113 4114 /** 4115 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O) 4116 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If ( 4117 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4118 4119 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D) 4120 @param EAX Lower 32-bits of MSR value. 4121 @param EDX Upper 32-bits of MSR value. 4122 4123 <b>Example usage</b> 4124 @code 4125 UINT64 Msr; 4126 4127 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS); 4128 @endcode 4129 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM. 4130 **/ 4131 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D 4132 4133 /** 4134 Capability Reporting Register of Primary Processor-based VM-execution Flex 4135 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution 4136 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4137 4138 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E) 4139 @param EAX Lower 32-bits of MSR value. 4140 @param EDX Upper 32-bits of MSR value. 4141 4142 <b>Example usage</b> 4143 @code 4144 UINT64 Msr; 4145 4146 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS); 4147 @endcode 4148 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM. 4149 **/ 4150 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E 4151 4152 /** 4153 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix 4154 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4155 4156 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F) 4157 @param EAX Lower 32-bits of MSR value. 4158 @param EDX Upper 32-bits of MSR value. 4159 4160 <b>Example usage</b> 4161 @code 4162 UINT64 Msr; 4163 4164 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS); 4165 @endcode 4166 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM. 4167 **/ 4168 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F 4169 4170 /** 4171 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix 4172 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4173 4174 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490) 4175 @param EAX Lower 32-bits of MSR value. 4176 @param EDX Upper 32-bits of MSR value. 4177 4178 <b>Example usage</b> 4179 @code 4180 UINT64 Msr; 4181 4182 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS); 4183 @endcode 4184 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM. 4185 **/ 4186 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 4187 4188 /** 4189 Capability Reporting Register of VMfunction Controls (R/O). If( 4190 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4191 4192 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491) 4193 @param EAX Lower 32-bits of MSR value. 4194 @param EDX Upper 32-bits of MSR value. 4195 4196 <b>Example usage</b> 4197 @code 4198 UINT64 Msr; 4199 4200 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC); 4201 @endcode 4202 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM. 4203 **/ 4204 #define MSR_IA32_VMX_VMFUNC 0x00000491 4205 4206 /** 4207 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && 4208 IA32_PERF_CAPABILITIES[ 13] = 1. 4209 4210 @param ECX MSR_IA32_A_PMCn 4211 @param EAX Lower 32-bits of MSR value. 4212 @param EDX Upper 32-bits of MSR value. 4213 4214 <b>Example usage</b> 4215 @code 4216 UINT64 Msr; 4217 4218 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0); 4219 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr); 4220 @endcode 4221 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. 4222 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. 4223 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. 4224 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. 4225 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. 4226 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. 4227 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. 4228 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM. 4229 @{ 4230 **/ 4231 #define MSR_IA32_A_PMC0 0x000004C1 4232 #define MSR_IA32_A_PMC1 0x000004C2 4233 #define MSR_IA32_A_PMC2 0x000004C3 4234 #define MSR_IA32_A_PMC3 0x000004C4 4235 #define MSR_IA32_A_PMC4 0x000004C5 4236 #define MSR_IA32_A_PMC5 0x000004C6 4237 #define MSR_IA32_A_PMC6 0x000004C7 4238 #define MSR_IA32_A_PMC7 0x000004C8 4239 /// @} 4240 4241 /** 4242 (R/W). If IA32_MCG_CAP.LMCE_P =1. 4243 4244 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0) 4245 @param EAX Lower 32-bits of MSR value. 4246 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. 4247 @param EDX Upper 32-bits of MSR value. 4248 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. 4249 4250 <b>Example usage</b> 4251 @code 4252 MSR_IA32_MCG_EXT_CTL_REGISTER Msr; 4253 4254 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); 4255 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64); 4256 @endcode 4257 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM. 4258 **/ 4259 #define MSR_IA32_MCG_EXT_CTL 0x000004D0 4260 4261 /** 4262 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL 4263 **/ 4264 typedef union { 4265 /// 4266 /// Individual bit fields 4267 /// 4268 struct { 4269 /// 4270 /// [Bit 0] LMCE_EN. 4271 /// 4272 UINT32 LMCE_EN : 1; 4273 UINT32 Reserved1 : 31; 4274 UINT32 Reserved2 : 32; 4275 } Bits; 4276 /// 4277 /// All bit fields as a 32-bit value 4278 /// 4279 UINT32 Uint32; 4280 /// 4281 /// All bit fields as a 64-bit value 4282 /// 4283 UINT64 Uint64; 4284 } MSR_IA32_MCG_EXT_CTL_REGISTER; 4285 4286 /** 4287 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H, 4288 ECX=0H): EBX[2] = 1. 4289 4290 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500) 4291 @param EAX Lower 32-bits of MSR value. 4292 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. 4293 @param EDX Upper 32-bits of MSR value. 4294 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. 4295 4296 <b>Example usage</b> 4297 @code 4298 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr; 4299 4300 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS); 4301 @endcode 4302 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM. 4303 **/ 4304 #define MSR_IA32_SGX_SVN_STATUS 0x00000500 4305 4306 /** 4307 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS 4308 **/ 4309 typedef union { 4310 /// 4311 /// Individual bit fields 4312 /// 4313 struct { 4314 /// 4315 /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated 4316 /// Code Modules (ACMs)". 4317 /// 4318 UINT32 Lock : 1; 4319 UINT32 Reserved1 : 15; 4320 /// 4321 /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with 4322 /// Authenticated Code Modules (ACMs)". 4323 /// 4324 UINT32 SGX_SVN_SINIT : 8; 4325 UINT32 Reserved2 : 8; 4326 UINT32 Reserved3 : 32; 4327 } Bits; 4328 /// 4329 /// All bit fields as a 32-bit value 4330 /// 4331 UINT32 Uint32; 4332 /// 4333 /// All bit fields as a 64-bit value 4334 /// 4335 UINT64 Uint64; 4336 } MSR_IA32_SGX_SVN_STATUS_REGISTER; 4337 4338 /** 4339 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) 4340 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) 4341 ) ). 4342 4343 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560) 4344 @param EAX Lower 32-bits of MSR value. 4345 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. 4346 @param EDX Upper 32-bits of MSR value. 4347 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. 4348 4349 <b>Example usage</b> 4350 @code 4351 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr; 4352 4353 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); 4354 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64); 4355 @endcode 4356 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM. 4357 **/ 4358 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 4359 4360 /** 4361 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE 4362 **/ 4363 typedef union { 4364 /// 4365 /// Individual bit fields 4366 /// 4367 struct { 4368 UINT32 Reserved : 7; 4369 /// 4370 /// [Bits 31:7] Base physical address. 4371 /// 4372 UINT32 Base : 25; 4373 /// 4374 /// [Bits 63:32] Base physical address. 4375 /// 4376 UINT32 BaseHi : 32; 4377 } Bits; 4378 /// 4379 /// All bit fields as a 64-bit value 4380 /// 4381 UINT64 Uint64; 4382 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER; 4383 4384 /** 4385 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H, 4386 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) 4387 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ). 4388 4389 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561) 4390 @param EAX Lower 32-bits of MSR value. 4391 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. 4392 @param EDX Upper 32-bits of MSR value. 4393 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. 4394 4395 <b>Example usage</b> 4396 @code 4397 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr; 4398 4399 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); 4400 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64); 4401 @endcode 4402 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM. 4403 **/ 4404 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561 4405 4406 /** 4407 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS 4408 **/ 4409 typedef union { 4410 /// 4411 /// Individual bit fields 4412 /// 4413 struct { 4414 UINT32 Reserved : 7; 4415 /// 4416 /// [Bits 31:7] MaskOrTableOffset. 4417 /// 4418 UINT32 MaskOrTableOffset : 25; 4419 /// 4420 /// [Bits 63:32] Output Offset. 4421 /// 4422 UINT32 OutputOffset : 32; 4423 } Bits; 4424 /// 4425 /// All bit fields as a 64-bit value 4426 /// 4427 UINT64 Uint64; 4428 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; 4429 4430 /** 4431 Format of ToPA table entries. 4432 **/ 4433 typedef union { 4434 /// 4435 /// Individual bit fields 4436 /// 4437 struct { 4438 /// 4439 /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". 4440 /// 4441 UINT32 END : 1; 4442 UINT32 Reserved1 : 1; 4443 /// 4444 /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". 4445 /// 4446 UINT32 INT : 1; 4447 UINT32 Reserved2 : 1; 4448 /// 4449 /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". 4450 /// 4451 UINT32 STOP : 1; 4452 UINT32 Reserved3 : 1; 4453 /// 4454 /// [Bit 6:9] Indicates the size of the associated output region. See Section 4455 /// 35.2.6.2, "Table of Physical Addresses (ToPA)". 4456 /// 4457 UINT32 Size : 4; 4458 UINT32 Reserved4 : 2; 4459 /// 4460 /// [Bit 12:31] Output Region Base Physical Address low part. 4461 /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match. 4462 /// ATTENTION: The size of the address field is determined by the processor's 4463 /// physical-address width (MAXPHYADDR) in bits, as reported in 4464 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. 4465 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. 4466 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". 4467 /// 4468 UINT32 Base : 20; 4469 /// 4470 /// [Bit 32:63] Output Region Base Physical Address high part. 4471 /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match. 4472 /// ATTENTION: The size of the address field is determined by the processor's 4473 /// physical-address width (MAXPHYADDR) in bits, as reported in 4474 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. 4475 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. 4476 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". 4477 /// 4478 UINT32 BaseHi : 32; 4479 } Bits; 4480 /// 4481 /// All bit fields as a 64-bit value 4482 /// 4483 UINT64 Uint64; 4484 } RTIT_TOPA_TABLE_ENTRY; 4485 4486 /// 4487 /// The size of the associated output region usd by Topa. 4488 /// 4489 typedef enum { 4490 RtitTopaMemorySize4K = 0, 4491 RtitTopaMemorySize8K, 4492 RtitTopaMemorySize16K, 4493 RtitTopaMemorySize32K, 4494 RtitTopaMemorySize64K, 4495 RtitTopaMemorySize128K, 4496 RtitTopaMemorySize256K, 4497 RtitTopaMemorySize512K, 4498 RtitTopaMemorySize1M, 4499 RtitTopaMemorySize2M, 4500 RtitTopaMemorySize4M, 4501 RtitTopaMemorySize8M, 4502 RtitTopaMemorySize16M, 4503 RtitTopaMemorySize32M, 4504 RtitTopaMemorySize64M, 4505 RtitTopaMemorySize128M 4506 } RTIT_TOPA_MEMORY_SIZE; 4507 4508 /** 4509 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4510 4511 @param ECX MSR_IA32_RTIT_CTL (0x00000570) 4512 @param EAX Lower 32-bits of MSR value. 4513 Described by the type MSR_IA32_RTIT_CTL_REGISTER. 4514 @param EDX Upper 32-bits of MSR value. 4515 Described by the type MSR_IA32_RTIT_CTL_REGISTER. 4516 4517 <b>Example usage</b> 4518 @code 4519 MSR_IA32_RTIT_CTL_REGISTER Msr; 4520 4521 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); 4522 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64); 4523 @endcode 4524 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM. 4525 **/ 4526 #define MSR_IA32_RTIT_CTL 0x00000570 4527 4528 /** 4529 MSR information returned for MSR index #MSR_IA32_RTIT_CTL 4530 **/ 4531 typedef union { 4532 /// 4533 /// Individual bit fields 4534 /// 4535 struct { 4536 /// 4537 /// [Bit 0] TraceEn. 4538 /// 4539 UINT32 TraceEn : 1; 4540 /// 4541 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4542 /// 4543 UINT32 CYCEn : 1; 4544 /// 4545 /// [Bit 2] OS. 4546 /// 4547 UINT32 OS : 1; 4548 /// 4549 /// [Bit 3] User. 4550 /// 4551 UINT32 User : 1; 4552 /// 4553 /// [Bit 4] PwrEvtEn. 4554 /// 4555 UINT32 PwrEvtEn : 1; 4556 /// 4557 /// [Bit 5] FUPonPTW. 4558 /// 4559 UINT32 FUPonPTW : 1; 4560 /// 4561 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1). 4562 /// 4563 UINT32 FabricEn : 1; 4564 /// 4565 /// [Bit 7] CR3 filter. 4566 /// 4567 UINT32 CR3 : 1; 4568 /// 4569 /// [Bit 8] ToPA. 4570 /// 4571 UINT32 ToPA : 1; 4572 /// 4573 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). 4574 /// 4575 UINT32 MTCEn : 1; 4576 /// 4577 /// [Bit 10] TSCEn. 4578 /// 4579 UINT32 TSCEn : 1; 4580 /// 4581 /// [Bit 11] DisRETC. 4582 /// 4583 UINT32 DisRETC : 1; 4584 /// 4585 /// [Bit 12] PTWEn. 4586 /// 4587 UINT32 PTWEn : 1; 4588 /// 4589 /// [Bit 13] BranchEn. 4590 /// 4591 UINT32 BranchEn : 1; 4592 /// 4593 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). 4594 /// 4595 UINT32 MTCFreq : 4; 4596 UINT32 Reserved3 : 1; 4597 /// 4598 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4599 /// 4600 UINT32 CYCThresh : 4; 4601 UINT32 Reserved4 : 1; 4602 /// 4603 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4604 /// 4605 UINT32 PSBFreq : 4; 4606 UINT32 Reserved5 : 4; 4607 /// 4608 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0). 4609 /// 4610 UINT32 ADDR0_CFG : 4; 4611 /// 4612 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1). 4613 /// 4614 UINT32 ADDR1_CFG : 4; 4615 /// 4616 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2). 4617 /// 4618 UINT32 ADDR2_CFG : 4; 4619 /// 4620 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3). 4621 /// 4622 UINT32 ADDR3_CFG : 4; 4623 UINT32 Reserved6 : 16; 4624 } Bits; 4625 /// 4626 /// All bit fields as a 64-bit value 4627 /// 4628 UINT64 Uint64; 4629 } MSR_IA32_RTIT_CTL_REGISTER; 4630 4631 /** 4632 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4633 4634 @param ECX MSR_IA32_RTIT_STATUS (0x00000571) 4635 @param EAX Lower 32-bits of MSR value. 4636 Described by the type MSR_IA32_RTIT_STATUS_REGISTER. 4637 @param EDX Upper 32-bits of MSR value. 4638 Described by the type MSR_IA32_RTIT_STATUS_REGISTER. 4639 4640 <b>Example usage</b> 4641 @code 4642 MSR_IA32_RTIT_STATUS_REGISTER Msr; 4643 4644 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS); 4645 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64); 4646 @endcode 4647 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM. 4648 **/ 4649 #define MSR_IA32_RTIT_STATUS 0x00000571 4650 4651 /** 4652 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS 4653 **/ 4654 typedef union { 4655 /// 4656 /// Individual bit fields 4657 /// 4658 struct { 4659 /// 4660 /// [Bit 0] FilterEn, (writes ignored). 4661 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1). 4662 /// 4663 UINT32 FilterEn : 1; 4664 /// 4665 /// [Bit 1] ContexEn, (writes ignored). 4666 /// 4667 UINT32 ContexEn : 1; 4668 /// 4669 /// [Bit 2] TriggerEn, (writes ignored). 4670 /// 4671 UINT32 TriggerEn : 1; 4672 UINT32 Reserved1 : 1; 4673 /// 4674 /// [Bit 4] Error. 4675 /// 4676 UINT32 Error : 1; 4677 /// 4678 /// [Bit 5] Stopped. 4679 /// 4680 UINT32 Stopped : 1; 4681 UINT32 Reserved2 : 26; 4682 /// 4683 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3). 4684 /// 4685 UINT32 PacketByteCnt : 17; 4686 UINT32 Reserved3 : 15; 4687 } Bits; 4688 /// 4689 /// All bit fields as a 64-bit value 4690 /// 4691 UINT64 Uint64; 4692 } MSR_IA32_RTIT_STATUS_REGISTER; 4693 4694 /** 4695 Trace Filter CR3 Match Register (R/W). 4696 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4697 4698 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572) 4699 @param EAX Lower 32-bits of MSR value. 4700 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. 4701 @param EDX Upper 32-bits of MSR value. 4702 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. 4703 4704 <b>Example usage</b> 4705 @code 4706 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr; 4707 4708 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH); 4709 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64); 4710 @endcode 4711 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM. 4712 **/ 4713 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 4714 4715 /** 4716 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH 4717 **/ 4718 typedef union { 4719 /// 4720 /// Individual bit fields 4721 /// 4722 struct { 4723 UINT32 Reserved : 5; 4724 /// 4725 /// [Bits 31:5] CR3[63:5] value to match. 4726 /// 4727 UINT32 Cr3 : 27; 4728 /// 4729 /// [Bits 63:32] CR3[63:5] value to match. 4730 /// 4731 UINT32 Cr3Hi : 32; 4732 } Bits; 4733 /// 4734 /// All bit fields as a 64-bit value 4735 /// 4736 UINT64 Uint64; 4737 } MSR_IA32_RTIT_CR3_MATCH_REGISTER; 4738 4739 /** 4740 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). 4741 4742 @param ECX MSR_IA32_RTIT_ADDRn_A 4743 @param EAX Lower 32-bits of MSR value. 4744 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4745 @param EDX Upper 32-bits of MSR value. 4746 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4747 4748 <b>Example usage</b> 4749 @code 4750 MSR_IA32_RTIT_ADDR_REGISTER Msr; 4751 4752 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A); 4753 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64); 4754 @endcode 4755 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. 4756 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. 4757 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. 4758 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM. 4759 @{ 4760 **/ 4761 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 4762 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 4763 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 4764 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 4765 /// @} 4766 4767 /** 4768 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). 4769 4770 @param ECX MSR_IA32_RTIT_ADDRn_B 4771 @param EAX Lower 32-bits of MSR value. 4772 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4773 @param EDX Upper 32-bits of MSR value. 4774 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4775 4776 <b>Example usage</b> 4777 @code 4778 MSR_IA32_RTIT_ADDR_REGISTER Msr; 4779 4780 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B); 4781 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64); 4782 @endcode 4783 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. 4784 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. 4785 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. 4786 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM. 4787 @{ 4788 **/ 4789 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 4790 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 4791 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 4792 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 4793 /// @} 4794 4795 /** 4796 MSR information returned for MSR indexes 4797 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and 4798 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B 4799 **/ 4800 typedef union { 4801 /// 4802 /// Individual bit fields 4803 /// 4804 struct { 4805 /// 4806 /// [Bits 31:0] Virtual Address. 4807 /// 4808 UINT32 VirtualAddress : 32; 4809 /// 4810 /// [Bits 47:32] Virtual Address. 4811 /// 4812 UINT32 VirtualAddressHi : 16; 4813 /// 4814 /// [Bits 63:48] SignExt_VA. 4815 /// 4816 UINT32 SignExt_VA : 16; 4817 } Bits; 4818 /// 4819 /// All bit fields as a 64-bit value 4820 /// 4821 UINT64 Uint64; 4822 } MSR_IA32_RTIT_ADDR_REGISTER; 4823 4824 /** 4825 DS Save Area (R/W) Points to the linear address of the first byte of the DS 4826 buffer management area, which is used to manage the BTS and PEBS buffers. 4827 See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If( 4828 CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS 4829 buffer management area, if IA-32e mode is active. 4830 4831 @param ECX MSR_IA32_DS_AREA (0x00000600) 4832 @param EAX Lower 32-bits of MSR value. 4833 Described by the type MSR_IA32_DS_AREA_REGISTER. 4834 @param EDX Upper 32-bits of MSR value. 4835 Described by the type MSR_IA32_DS_AREA_REGISTER. 4836 4837 <b>Example usage</b> 4838 @code 4839 UINT64 Msr; 4840 4841 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA); 4842 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr); 4843 @endcode 4844 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM. 4845 **/ 4846 #define MSR_IA32_DS_AREA 0x00000600 4847 4848 /** 4849 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] = 4850 1. 4851 4852 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0) 4853 @param EAX Lower 32-bits of MSR value. 4854 @param EDX Upper 32-bits of MSR value. 4855 4856 <b>Example usage</b> 4857 @code 4858 UINT64 Msr; 4859 4860 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE); 4861 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr); 4862 @endcode 4863 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM. 4864 **/ 4865 #define MSR_IA32_TSC_DEADLINE 0x000006E0 4866 4867 /** 4868 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1. 4869 4870 @param ECX MSR_IA32_PM_ENABLE (0x00000770) 4871 @param EAX Lower 32-bits of MSR value. 4872 Described by the type MSR_IA32_PM_ENABLE_REGISTER. 4873 @param EDX Upper 32-bits of MSR value. 4874 Described by the type MSR_IA32_PM_ENABLE_REGISTER. 4875 4876 <b>Example usage</b> 4877 @code 4878 MSR_IA32_PM_ENABLE_REGISTER Msr; 4879 4880 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE); 4881 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64); 4882 @endcode 4883 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM. 4884 **/ 4885 #define MSR_IA32_PM_ENABLE 0x00000770 4886 4887 /** 4888 MSR information returned for MSR index #MSR_IA32_PM_ENABLE 4889 **/ 4890 typedef union { 4891 /// 4892 /// Individual bit fields 4893 /// 4894 struct { 4895 /// 4896 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If 4897 /// CPUID.06H:EAX.[7] = 1. 4898 /// 4899 UINT32 HWP_ENABLE : 1; 4900 UINT32 Reserved1 : 31; 4901 UINT32 Reserved2 : 32; 4902 } Bits; 4903 /// 4904 /// All bit fields as a 32-bit value 4905 /// 4906 UINT32 Uint32; 4907 /// 4908 /// All bit fields as a 64-bit value 4909 /// 4910 UINT64 Uint64; 4911 } MSR_IA32_PM_ENABLE_REGISTER; 4912 4913 /** 4914 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1. 4915 4916 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771) 4917 @param EAX Lower 32-bits of MSR value. 4918 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. 4919 @param EDX Upper 32-bits of MSR value. 4920 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. 4921 4922 <b>Example usage</b> 4923 @code 4924 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr; 4925 4926 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES); 4927 @endcode 4928 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM. 4929 **/ 4930 #define MSR_IA32_HWP_CAPABILITIES 0x00000771 4931 4932 /** 4933 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES 4934 **/ 4935 typedef union { 4936 /// 4937 /// Individual bit fields 4938 /// 4939 struct { 4940 /// 4941 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance 4942 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4943 /// 4944 UINT32 Highest_Performance : 8; 4945 /// 4946 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP 4947 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4948 /// 4949 UINT32 Guaranteed_Performance : 8; 4950 /// 4951 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP 4952 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4953 /// 4954 UINT32 Most_Efficient_Performance : 8; 4955 /// 4956 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance 4957 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4958 /// 4959 UINT32 Lowest_Performance : 8; 4960 UINT32 Reserved : 32; 4961 } Bits; 4962 /// 4963 /// All bit fields as a 32-bit value 4964 /// 4965 UINT32 Uint32; 4966 /// 4967 /// All bit fields as a 64-bit value 4968 /// 4969 UINT64 Uint64; 4970 } MSR_IA32_HWP_CAPABILITIES_REGISTER; 4971 4972 /** 4973 Power Management Control Hints for All Logical Processors in a Package 4974 (R/W). If CPUID.06H:EAX.[11] = 1. 4975 4976 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772) 4977 @param EAX Lower 32-bits of MSR value. 4978 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. 4979 @param EDX Upper 32-bits of MSR value. 4980 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. 4981 4982 <b>Example usage</b> 4983 @code 4984 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr; 4985 4986 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG); 4987 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64); 4988 @endcode 4989 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM. 4990 **/ 4991 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772 4992 4993 /** 4994 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG 4995 **/ 4996 typedef union { 4997 /// 4998 /// Individual bit fields 4999 /// 5000 struct { 5001 /// 5002 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If 5003 /// CPUID.06H:EAX.[11] = 1. 5004 /// 5005 UINT32 Minimum_Performance : 8; 5006 /// 5007 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If 5008 /// CPUID.06H:EAX.[11] = 1. 5009 /// 5010 UINT32 Maximum_Performance : 8; 5011 /// 5012 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". 5013 /// If CPUID.06H:EAX.[11] = 1. 5014 /// 5015 UINT32 Desired_Performance : 8; 5016 /// 5017 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, 5018 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1. 5019 /// 5020 UINT32 Energy_Performance_Preference : 8; 5021 /// 5022 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If 5023 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1. 5024 /// 5025 UINT32 Activity_Window : 10; 5026 UINT32 Reserved : 22; 5027 } Bits; 5028 /// 5029 /// All bit fields as a 64-bit value 5030 /// 5031 UINT64 Uint64; 5032 } MSR_IA32_HWP_REQUEST_PKG_REGISTER; 5033 5034 /** 5035 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1. 5036 5037 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773) 5038 @param EAX Lower 32-bits of MSR value. 5039 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. 5040 @param EDX Upper 32-bits of MSR value. 5041 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. 5042 5043 <b>Example usage</b> 5044 @code 5045 MSR_IA32_HWP_INTERRUPT_REGISTER Msr; 5046 5047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT); 5048 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64); 5049 @endcode 5050 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM. 5051 **/ 5052 #define MSR_IA32_HWP_INTERRUPT 0x00000773 5053 5054 /** 5055 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT 5056 **/ 5057 typedef union { 5058 /// 5059 /// Individual bit fields 5060 /// 5061 struct { 5062 /// 5063 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP 5064 /// Notifications". If CPUID.06H:EAX.[8] = 1. 5065 /// 5066 UINT32 EN_Guaranteed_Performance_Change : 1; 5067 /// 5068 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications". 5069 /// If CPUID.06H:EAX.[8] = 1. 5070 /// 5071 UINT32 EN_Excursion_Minimum : 1; 5072 UINT32 Reserved1 : 30; 5073 UINT32 Reserved2 : 32; 5074 } Bits; 5075 /// 5076 /// All bit fields as a 32-bit value 5077 /// 5078 UINT32 Uint32; 5079 /// 5080 /// All bit fields as a 64-bit value 5081 /// 5082 UINT64 Uint64; 5083 } MSR_IA32_HWP_INTERRUPT_REGISTER; 5084 5085 /** 5086 Power Management Control Hints to a Logical Processor (R/W). If 5087 CPUID.06H:EAX.[7] = 1. 5088 5089 @param ECX MSR_IA32_HWP_REQUEST (0x00000774) 5090 @param EAX Lower 32-bits of MSR value. 5091 Described by the type MSR_IA32_HWP_REQUEST_REGISTER. 5092 @param EDX Upper 32-bits of MSR value. 5093 Described by the type MSR_IA32_HWP_REQUEST_REGISTER. 5094 5095 <b>Example usage</b> 5096 @code 5097 MSR_IA32_HWP_REQUEST_REGISTER Msr; 5098 5099 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST); 5100 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64); 5101 @endcode 5102 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM. 5103 **/ 5104 #define MSR_IA32_HWP_REQUEST 0x00000774 5105 5106 /** 5107 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST 5108 **/ 5109 typedef union { 5110 /// 5111 /// Individual bit fields 5112 /// 5113 struct { 5114 /// 5115 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If 5116 /// CPUID.06H:EAX.[7] = 1. 5117 /// 5118 UINT32 Minimum_Performance : 8; 5119 /// 5120 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If 5121 /// CPUID.06H:EAX.[7] = 1. 5122 /// 5123 UINT32 Maximum_Performance : 8; 5124 /// 5125 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". 5126 /// If CPUID.06H:EAX.[7] = 1. 5127 /// 5128 UINT32 Desired_Performance : 8; 5129 /// 5130 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, 5131 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1. 5132 /// 5133 UINT32 Energy_Performance_Preference : 8; 5134 /// 5135 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If 5136 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1. 5137 /// 5138 UINT32 Activity_Window : 10; 5139 /// 5140 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If 5141 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1. 5142 /// 5143 UINT32 Package_Control : 1; 5144 UINT32 Reserved : 21; 5145 } Bits; 5146 /// 5147 /// All bit fields as a 64-bit value 5148 /// 5149 UINT64 Uint64; 5150 } MSR_IA32_HWP_REQUEST_REGISTER; 5151 5152 /** 5153 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If 5154 CPUID.06H:EAX.[7] = 1. 5155 5156 @param ECX MSR_IA32_HWP_STATUS (0x00000777) 5157 @param EAX Lower 32-bits of MSR value. 5158 Described by the type MSR_IA32_HWP_STATUS_REGISTER. 5159 @param EDX Upper 32-bits of MSR value. 5160 Described by the type MSR_IA32_HWP_STATUS_REGISTER. 5161 5162 <b>Example usage</b> 5163 @code 5164 MSR_IA32_HWP_STATUS_REGISTER Msr; 5165 5166 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS); 5167 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64); 5168 @endcode 5169 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM. 5170 **/ 5171 #define MSR_IA32_HWP_STATUS 0x00000777 5172 5173 /** 5174 MSR information returned for MSR index #MSR_IA32_HWP_STATUS 5175 **/ 5176 typedef union { 5177 /// 5178 /// Individual bit fields 5179 /// 5180 struct { 5181 /// 5182 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5, 5183 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1. 5184 /// 5185 UINT32 Guaranteed_Performance_Change : 1; 5186 UINT32 Reserved1 : 1; 5187 /// 5188 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP 5189 /// Feedback". If CPUID.06H:EAX.[7] = 1. 5190 /// 5191 UINT32 Excursion_To_Minimum : 1; 5192 UINT32 Reserved2 : 29; 5193 UINT32 Reserved3 : 32; 5194 } Bits; 5195 /// 5196 /// All bit fields as a 32-bit value 5197 /// 5198 UINT32 Uint32; 5199 /// 5200 /// All bit fields as a 64-bit value 5201 /// 5202 UINT64 Uint64; 5203 } MSR_IA32_HWP_STATUS_REGISTER; 5204 5205 /** 5206 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1 5207 && IA32_APIC_BASE.[10] = 1. 5208 5209 @param ECX MSR_IA32_X2APIC_APICID (0x00000802) 5210 @param EAX Lower 32-bits of MSR value. 5211 @param EDX Upper 32-bits of MSR value. 5212 5213 <b>Example usage</b> 5214 @code 5215 UINT64 Msr; 5216 5217 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID); 5218 @endcode 5219 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM. 5220 **/ 5221 #define MSR_IA32_X2APIC_APICID 0x00000802 5222 5223 /** 5224 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5225 IA32_APIC_BASE.[10] = 1. 5226 5227 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803) 5228 @param EAX Lower 32-bits of MSR value. 5229 @param EDX Upper 32-bits of MSR value. 5230 5231 <b>Example usage</b> 5232 @code 5233 UINT64 Msr; 5234 5235 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION); 5236 @endcode 5237 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM. 5238 **/ 5239 #define MSR_IA32_X2APIC_VERSION 0x00000803 5240 5241 /** 5242 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5243 IA32_APIC_BASE.[10] = 1. 5244 5245 @param ECX MSR_IA32_X2APIC_TPR (0x00000808) 5246 @param EAX Lower 32-bits of MSR value. 5247 @param EDX Upper 32-bits of MSR value. 5248 5249 <b>Example usage</b> 5250 @code 5251 UINT64 Msr; 5252 5253 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR); 5254 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr); 5255 @endcode 5256 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM. 5257 **/ 5258 #define MSR_IA32_X2APIC_TPR 0x00000808 5259 5260 /** 5261 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5262 IA32_APIC_BASE.[10] = 1. 5263 5264 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A) 5265 @param EAX Lower 32-bits of MSR value. 5266 @param EDX Upper 32-bits of MSR value. 5267 5268 <b>Example usage</b> 5269 @code 5270 UINT64 Msr; 5271 5272 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR); 5273 @endcode 5274 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM. 5275 **/ 5276 #define MSR_IA32_X2APIC_PPR 0x0000080A 5277 5278 /** 5279 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] 5280 = 1. 5281 5282 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B) 5283 @param EAX Lower 32-bits of MSR value. 5284 @param EDX Upper 32-bits of MSR value. 5285 5286 <b>Example usage</b> 5287 @code 5288 UINT64 Msr; 5289 5290 Msr = 0; 5291 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr); 5292 @endcode 5293 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM. 5294 **/ 5295 #define MSR_IA32_X2APIC_EOI 0x0000080B 5296 5297 /** 5298 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5299 IA32_APIC_BASE.[10] = 1. 5300 5301 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D) 5302 @param EAX Lower 32-bits of MSR value. 5303 @param EDX Upper 32-bits of MSR value. 5304 5305 <b>Example usage</b> 5306 @code 5307 UINT64 Msr; 5308 5309 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR); 5310 @endcode 5311 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM. 5312 **/ 5313 #define MSR_IA32_X2APIC_LDR 0x0000080D 5314 5315 /** 5316 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1 5317 && IA32_APIC_BASE.[10] = 1. 5318 5319 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F) 5320 @param EAX Lower 32-bits of MSR value. 5321 @param EDX Upper 32-bits of MSR value. 5322 5323 <b>Example usage</b> 5324 @code 5325 UINT64 Msr; 5326 5327 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR); 5328 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr); 5329 @endcode 5330 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM. 5331 **/ 5332 #define MSR_IA32_X2APIC_SIVR 0x0000080F 5333 5334 /** 5335 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). 5336 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5337 5338 @param ECX MSR_IA32_X2APIC_ISRn 5339 @param EAX Lower 32-bits of MSR value. 5340 @param EDX Upper 32-bits of MSR value. 5341 5342 <b>Example usage</b> 5343 @code 5344 UINT64 Msr; 5345 5346 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0); 5347 @endcode 5348 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. 5349 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. 5350 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. 5351 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. 5352 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. 5353 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. 5354 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. 5355 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM. 5356 @{ 5357 **/ 5358 #define MSR_IA32_X2APIC_ISR0 0x00000810 5359 #define MSR_IA32_X2APIC_ISR1 0x00000811 5360 #define MSR_IA32_X2APIC_ISR2 0x00000812 5361 #define MSR_IA32_X2APIC_ISR3 0x00000813 5362 #define MSR_IA32_X2APIC_ISR4 0x00000814 5363 #define MSR_IA32_X2APIC_ISR5 0x00000815 5364 #define MSR_IA32_X2APIC_ISR6 0x00000816 5365 #define MSR_IA32_X2APIC_ISR7 0x00000817 5366 /// @} 5367 5368 /** 5369 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). 5370 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5371 5372 @param ECX MSR_IA32_X2APIC_TMRn 5373 @param EAX Lower 32-bits of MSR value. 5374 @param EDX Upper 32-bits of MSR value. 5375 5376 <b>Example usage</b> 5377 @code 5378 UINT64 Msr; 5379 5380 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0); 5381 @endcode 5382 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. 5383 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. 5384 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. 5385 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. 5386 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. 5387 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. 5388 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. 5389 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM. 5390 @{ 5391 **/ 5392 #define MSR_IA32_X2APIC_TMR0 0x00000818 5393 #define MSR_IA32_X2APIC_TMR1 0x00000819 5394 #define MSR_IA32_X2APIC_TMR2 0x0000081A 5395 #define MSR_IA32_X2APIC_TMR3 0x0000081B 5396 #define MSR_IA32_X2APIC_TMR4 0x0000081C 5397 #define MSR_IA32_X2APIC_TMR5 0x0000081D 5398 #define MSR_IA32_X2APIC_TMR6 0x0000081E 5399 #define MSR_IA32_X2APIC_TMR7 0x0000081F 5400 /// @} 5401 5402 /** 5403 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). 5404 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5405 5406 @param ECX MSR_IA32_X2APIC_IRRn 5407 @param EAX Lower 32-bits of MSR value. 5408 @param EDX Upper 32-bits of MSR value. 5409 5410 <b>Example usage</b> 5411 @code 5412 UINT64 Msr; 5413 5414 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0); 5415 @endcode 5416 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. 5417 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. 5418 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. 5419 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. 5420 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. 5421 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. 5422 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. 5423 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM. 5424 @{ 5425 **/ 5426 #define MSR_IA32_X2APIC_IRR0 0x00000820 5427 #define MSR_IA32_X2APIC_IRR1 0x00000821 5428 #define MSR_IA32_X2APIC_IRR2 0x00000822 5429 #define MSR_IA32_X2APIC_IRR3 0x00000823 5430 #define MSR_IA32_X2APIC_IRR4 0x00000824 5431 #define MSR_IA32_X2APIC_IRR5 0x00000825 5432 #define MSR_IA32_X2APIC_IRR6 0x00000826 5433 #define MSR_IA32_X2APIC_IRR7 0x00000827 5434 /// @} 5435 5436 /** 5437 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5438 IA32_APIC_BASE.[10] = 1. 5439 5440 @param ECX MSR_IA32_X2APIC_ESR (0x00000828) 5441 @param EAX Lower 32-bits of MSR value. 5442 @param EDX Upper 32-bits of MSR value. 5443 5444 <b>Example usage</b> 5445 @code 5446 UINT64 Msr; 5447 5448 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR); 5449 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr); 5450 @endcode 5451 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM. 5452 **/ 5453 #define MSR_IA32_X2APIC_ESR 0x00000828 5454 5455 /** 5456 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If 5457 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5458 5459 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F) 5460 @param EAX Lower 32-bits of MSR value. 5461 @param EDX Upper 32-bits of MSR value. 5462 5463 <b>Example usage</b> 5464 @code 5465 UINT64 Msr; 5466 5467 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI); 5468 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr); 5469 @endcode 5470 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM. 5471 **/ 5472 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F 5473 5474 /** 5475 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5476 IA32_APIC_BASE.[10] = 1. 5477 5478 @param ECX MSR_IA32_X2APIC_ICR (0x00000830) 5479 @param EAX Lower 32-bits of MSR value. 5480 @param EDX Upper 32-bits of MSR value. 5481 5482 <b>Example usage</b> 5483 @code 5484 UINT64 Msr; 5485 5486 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR); 5487 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr); 5488 @endcode 5489 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM. 5490 **/ 5491 #define MSR_IA32_X2APIC_ICR 0x00000830 5492 5493 /** 5494 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5495 IA32_APIC_BASE.[10] = 1. 5496 5497 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832) 5498 @param EAX Lower 32-bits of MSR value. 5499 @param EDX Upper 32-bits of MSR value. 5500 5501 <b>Example usage</b> 5502 @code 5503 UINT64 Msr; 5504 5505 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER); 5506 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr); 5507 @endcode 5508 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM. 5509 **/ 5510 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832 5511 5512 /** 5513 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 5514 1 && IA32_APIC_BASE.[10] = 1. 5515 5516 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833) 5517 @param EAX Lower 32-bits of MSR value. 5518 @param EDX Upper 32-bits of MSR value. 5519 5520 <b>Example usage</b> 5521 @code 5522 UINT64 Msr; 5523 5524 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL); 5525 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr); 5526 @endcode 5527 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM. 5528 **/ 5529 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833 5530 5531 /** 5532 x2APIC LVT Performance Monitor Interrupt Register (R/W). If 5533 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5534 5535 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834) 5536 @param EAX Lower 32-bits of MSR value. 5537 @param EDX Upper 32-bits of MSR value. 5538 5539 <b>Example usage</b> 5540 @code 5541 UINT64 Msr; 5542 5543 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI); 5544 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr); 5545 @endcode 5546 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM. 5547 **/ 5548 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834 5549 5550 /** 5551 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5552 IA32_APIC_BASE.[10] = 1. 5553 5554 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835) 5555 @param EAX Lower 32-bits of MSR value. 5556 @param EDX Upper 32-bits of MSR value. 5557 5558 <b>Example usage</b> 5559 @code 5560 UINT64 Msr; 5561 5562 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0); 5563 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr); 5564 @endcode 5565 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM. 5566 **/ 5567 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835 5568 5569 /** 5570 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5571 IA32_APIC_BASE.[10] = 1. 5572 5573 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836) 5574 @param EAX Lower 32-bits of MSR value. 5575 @param EDX Upper 32-bits of MSR value. 5576 5577 <b>Example usage</b> 5578 @code 5579 UINT64 Msr; 5580 5581 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1); 5582 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr); 5583 @endcode 5584 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM. 5585 **/ 5586 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836 5587 5588 /** 5589 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5590 IA32_APIC_BASE.[10] = 1. 5591 5592 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837) 5593 @param EAX Lower 32-bits of MSR value. 5594 @param EDX Upper 32-bits of MSR value. 5595 5596 <b>Example usage</b> 5597 @code 5598 UINT64 Msr; 5599 5600 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR); 5601 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr); 5602 @endcode 5603 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM. 5604 **/ 5605 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837 5606 5607 /** 5608 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5609 IA32_APIC_BASE.[10] = 1. 5610 5611 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838) 5612 @param EAX Lower 32-bits of MSR value. 5613 @param EDX Upper 32-bits of MSR value. 5614 5615 <b>Example usage</b> 5616 @code 5617 UINT64 Msr; 5618 5619 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT); 5620 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr); 5621 @endcode 5622 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM. 5623 **/ 5624 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838 5625 5626 /** 5627 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5628 IA32_APIC_BASE.[10] = 1. 5629 5630 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839) 5631 @param EAX Lower 32-bits of MSR value. 5632 @param EDX Upper 32-bits of MSR value. 5633 5634 <b>Example usage</b> 5635 @code 5636 UINT64 Msr; 5637 5638 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT); 5639 @endcode 5640 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM. 5641 **/ 5642 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839 5643 5644 /** 5645 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5646 IA32_APIC_BASE.[10] = 1. 5647 5648 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E) 5649 @param EAX Lower 32-bits of MSR value. 5650 @param EDX Upper 32-bits of MSR value. 5651 5652 <b>Example usage</b> 5653 @code 5654 UINT64 Msr; 5655 5656 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF); 5657 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr); 5658 @endcode 5659 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM. 5660 **/ 5661 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E 5662 5663 /** 5664 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 && 5665 IA32_APIC_BASE.[10] = 1. 5666 5667 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F) 5668 @param EAX Lower 32-bits of MSR value. 5669 @param EDX Upper 32-bits of MSR value. 5670 5671 <b>Example usage</b> 5672 @code 5673 UINT64 Msr; 5674 5675 Msr = 0; 5676 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr); 5677 @endcode 5678 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM. 5679 **/ 5680 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F 5681 5682 /** 5683 Memory Encryption Activation MSR. If CPUID.07H:ECX.[13] = 1. 5684 5685 @param ECX MSR_IA32_TME_ACTIVATE (0x00000982) 5686 @param EAX Lower 32-bits of MSR value. 5687 Described by the type MSR_IA32_TME_ACTIVATE_REGISTER. 5688 @param EDX Upper 32-bits of MSR value. 5689 Described by the type MSR_IA32_TME_ACTIVATE_REGISTER. 5690 5691 <b>Example usage</b> 5692 @code 5693 MSR_IA32_TME_ACTIVATE_REGISTER Msr; 5694 5695 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); 5696 AsmWriteMsr64 (MSR_IA32_TME_ACTIVATE, Msr.Uint64); 5697 @endcode 5698 @note MSR_IA32_TME_ACTIVATE is defined as IA32_TME_ACTIVATE in SDM. 5699 **/ 5700 #define MSR_IA32_TME_ACTIVATE 0x00000982 5701 5702 /** 5703 MSR information returned for MSR index #MSR_IA32_TME_ACTIVATE 5704 **/ 5705 typedef union { 5706 /// 5707 /// Individual bit fields 5708 /// 5709 struct { 5710 /// 5711 /// [Bit 0] Lock R/O: Will be set upon successful WRMSR (or first SMI); 5712 /// written value ignored.. 5713 /// 5714 UINT32 Lock : 1; 5715 /// 5716 /// [Bit 1] Hardware Encryption Enable: This bit also enables MKTME; MKTME 5717 /// cannot be enabled without enabling encryption hardware. 5718 /// 5719 UINT32 TmeEnable : 1; 5720 /// 5721 /// [Bit 2] Key Select: 5722 /// 0: Create a new TME key (expected cold/warm boot). 5723 /// 1: Restore the TME key from storage (Expected when resume from standby). 5724 /// 5725 UINT32 KeySelect : 1; 5726 /// 5727 /// [Bit 3] Save TME Key for Standby: Save key into storage to be used when 5728 /// resume from standby. 5729 /// Note: This may not be supported in all processors. 5730 /// 5731 UINT32 SaveKeyForStandby : 1; 5732 /// 5733 /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumerated in 5734 /// IA32_TME_CAPABILITY are allowed. 5735 /// For example: 5736 /// 0000 – AES-XTS-128. 5737 /// 0001 – AES-XTS-128 with integrity. 5738 /// 0010 – AES-XTS-256. 5739 /// Other values are invalid. 5740 /// 5741 UINT32 TmePolicy : 4; 5742 UINT32 Reserved : 23; 5743 /// 5744 /// [Bit 31] TME Encryption Bypass Enable: When encryption hardware is enabled: 5745 /// * Total Memory Encryption is enabled using a CPU generated ephemeral key 5746 /// based on a hardware random number generator when this bit is set to 0. 5747 /// * Total Memory Encryption is bypassed (no encryption/decryption for KeyID0) 5748 /// when this bit is set to 1. 5749 /// Software must inspect Hardware Encryption Enable (bit 1) and TME encryption 5750 /// bypass Enable (bit 31) to determine if TME encryption is enabled. 5751 /// 5752 UINT32 TmeBypassMode : 1; 5753 /// 5754 /// [Bit 35:32] MK_TME_KEYID_BITS: Reserved if MKTME is not enumerated, otherwise: 5755 /// The number of key identifier bits to allocate to MKTME usage. 5756 /// Similar to enumeration, this is an encoded value. 5757 /// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in #GP. 5758 /// Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware 5759 /// Encryption Enable) is not also set to ‘1, as encryption hardware must be 5760 /// enabled to use MKTME. 5761 /// Example: To support 255 keys, this field would be set to a value of 8. 5762 /// 5763 UINT32 MkTmeKeyidBits : 4; 5764 UINT32 Reserved2 : 12; 5765 /// 5766 /// [Bit 63:48] MK_TME_CRYPTO_ALGS: Reserved if MKTME is not enumerated, otherwise: 5767 /// Bit 48: AES-XTS 128. 5768 /// Bit 49: AES-XTS 128 with integrity. 5769 /// Bit 50: AES-XTS 256. 5770 /// Bit 63:51: Reserved (#GP) 5771 /// Bitmask for BIOS to set which encryption algorithms are allowed for MKTME, would 5772 /// be later enforced by the key loading ISA ('1= allowed) 5773 /// 5774 UINT32 MkTmeCryptoAlgs : 16; 5775 } Bits; 5776 /// 5777 /// All bit fields as a 32-bit value 5778 /// 5779 UINT32 Uint32[2]; 5780 /// 5781 /// All bit fields as a 64-bit value 5782 /// 5783 UINT64 Uint64; 5784 } MSR_IA32_TME_ACTIVATE_REGISTER; 5785 5786 /** 5787 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1. 5788 5789 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80) 5790 @param EAX Lower 32-bits of MSR value. 5791 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. 5792 @param EDX Upper 32-bits of MSR value. 5793 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. 5794 5795 <b>Example usage</b> 5796 @code 5797 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr; 5798 5799 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE); 5800 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64); 5801 @endcode 5802 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM. 5803 **/ 5804 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80 5805 5806 /** 5807 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE 5808 **/ 5809 typedef union { 5810 /// 5811 /// Individual bit fields 5812 /// 5813 struct { 5814 /// 5815 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features. 5816 /// Default is 0. If CPUID.01H:ECX.[11] = 1. 5817 /// 5818 UINT32 Enable : 1; 5819 UINT32 Reserved1 : 29; 5820 /// 5821 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The 5822 /// lock bit is set automatically on the first SMI assertion even if not 5823 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1. 5824 /// 5825 UINT32 Lock : 1; 5826 /// 5827 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to 5828 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1. 5829 /// 5830 UINT32 DebugOccurred : 1; 5831 UINT32 Reserved2 : 32; 5832 } Bits; 5833 /// 5834 /// All bit fields as a 32-bit value 5835 /// 5836 UINT32 Uint32; 5837 /// 5838 /// All bit fields as a 64-bit value 5839 /// 5840 UINT64 Uint64; 5841 } MSR_IA32_DEBUG_INTERFACE_REGISTER; 5842 5843 /** 5844 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ). 5845 5846 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81) 5847 @param EAX Lower 32-bits of MSR value. 5848 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. 5849 @param EDX Upper 32-bits of MSR value. 5850 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. 5851 5852 <b>Example usage</b> 5853 @code 5854 MSR_IA32_L3_QOS_CFG_REGISTER Msr; 5855 5856 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG); 5857 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64); 5858 @endcode 5859 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. 5860 **/ 5861 #define MSR_IA32_L3_QOS_CFG 0x00000C81 5862 5863 /** 5864 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG 5865 **/ 5866 typedef union { 5867 /// 5868 /// Individual bit fields 5869 /// 5870 struct { 5871 /// 5872 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate 5873 /// in Code and Data Prioritization (CDP) mode. 5874 /// 5875 UINT32 Enable : 1; 5876 UINT32 Reserved1 : 31; 5877 UINT32 Reserved2 : 32; 5878 } Bits; 5879 /// 5880 /// All bit fields as a 32-bit value 5881 /// 5882 UINT32 Uint32; 5883 /// 5884 /// All bit fields as a 64-bit value 5885 /// 5886 UINT64 Uint64; 5887 } MSR_IA32_L3_QOS_CFG_REGISTER; 5888 5889 /** 5890 L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ). 5891 5892 @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82) 5893 @param EAX Lower 32-bits of MSR value. 5894 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER. 5895 @param EDX Upper 32-bits of MSR value. 5896 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER. 5897 5898 <b>Example usage</b> 5899 @code 5900 MSR_IA32_L2_QOS_CFG_REGISTER Msr; 5901 5902 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG); 5903 AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64); 5904 @endcode 5905 @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM. 5906 **/ 5907 #define MSR_IA32_L2_QOS_CFG 0x00000C82 5908 5909 /** 5910 MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG 5911 **/ 5912 typedef union { 5913 /// 5914 /// Individual bit fields 5915 /// 5916 struct { 5917 /// 5918 /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate 5919 /// in Code and Data Prioritization (CDP) mode. 5920 /// 5921 UINT32 Enable : 1; 5922 UINT32 Reserved1 : 31; 5923 UINT32 Reserved2 : 32; 5924 } Bits; 5925 /// 5926 /// All bit fields as a 32-bit value 5927 /// 5928 UINT32 Uint32; 5929 /// 5930 /// All bit fields as a 64-bit value 5931 /// 5932 UINT64 Uint64; 5933 } MSR_IA32_L2_QOS_CFG_REGISTER; 5934 5935 /** 5936 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] 5937 = 1 ). 5938 5939 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D) 5940 @param EAX Lower 32-bits of MSR value. 5941 Described by the type MSR_IA32_QM_EVTSEL_REGISTER. 5942 @param EDX Upper 32-bits of MSR value. 5943 Described by the type MSR_IA32_QM_EVTSEL_REGISTER. 5944 5945 <b>Example usage</b> 5946 @code 5947 MSR_IA32_QM_EVTSEL_REGISTER Msr; 5948 5949 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL); 5950 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64); 5951 @endcode 5952 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. 5953 **/ 5954 #define MSR_IA32_QM_EVTSEL 0x00000C8D 5955 5956 /** 5957 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL 5958 **/ 5959 typedef union { 5960 /// 5961 /// Individual bit fields 5962 /// 5963 struct { 5964 /// 5965 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via 5966 /// IA32_QM_CTR. 5967 /// 5968 UINT32 EventID : 8; 5969 UINT32 Reserved : 24; 5970 /// 5971 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to 5972 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` ( 5973 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). 5974 /// 5975 UINT32 ResourceMonitoringID : 32; 5976 } Bits; 5977 /// 5978 /// All bit fields as a 64-bit value 5979 /// 5980 UINT64 Uint64; 5981 } MSR_IA32_QM_EVTSEL_REGISTER; 5982 5983 /** 5984 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 5985 ). 5986 5987 @param ECX MSR_IA32_QM_CTR (0x00000C8E) 5988 @param EAX Lower 32-bits of MSR value. 5989 Described by the type MSR_IA32_QM_CTR_REGISTER. 5990 @param EDX Upper 32-bits of MSR value. 5991 Described by the type MSR_IA32_QM_CTR_REGISTER. 5992 5993 <b>Example usage</b> 5994 @code 5995 MSR_IA32_QM_CTR_REGISTER Msr; 5996 5997 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR); 5998 @endcode 5999 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM. 6000 **/ 6001 #define MSR_IA32_QM_CTR 0x00000C8E 6002 6003 /** 6004 MSR information returned for MSR index #MSR_IA32_QM_CTR 6005 **/ 6006 typedef union { 6007 /// 6008 /// Individual bit fields 6009 /// 6010 struct { 6011 /// 6012 /// [Bits 31:0] Resource Monitored Data. 6013 /// 6014 UINT32 ResourceMonitoredData : 32; 6015 /// 6016 /// [Bits 61:32] Resource Monitored Data. 6017 /// 6018 UINT32 ResourceMonitoredDataHi : 30; 6019 /// 6020 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not 6021 /// available or not monitored for this resource or RMID. 6022 /// 6023 UINT32 Unavailable : 1; 6024 /// 6025 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was 6026 /// written to IA32_PQR_QM_EVTSEL. 6027 /// 6028 UINT32 Error : 1; 6029 } Bits; 6030 /// 6031 /// All bit fields as a 64-bit value 6032 /// 6033 UINT64 Uint64; 6034 } MSR_IA32_QM_CTR_REGISTER; 6035 6036 /** 6037 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12] 6038 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ). 6039 6040 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F) 6041 @param EAX Lower 32-bits of MSR value. 6042 Described by the type MSR_IA32_PQR_ASSOC_REGISTER. 6043 @param EDX Upper 32-bits of MSR value. 6044 Described by the type MSR_IA32_PQR_ASSOC_REGISTER. 6045 6046 <b>Example usage</b> 6047 @code 6048 MSR_IA32_PQR_ASSOC_REGISTER Msr; 6049 6050 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC); 6051 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64); 6052 @endcode 6053 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. 6054 **/ 6055 #define MSR_IA32_PQR_ASSOC 0x00000C8F 6056 6057 /** 6058 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC 6059 **/ 6060 typedef union { 6061 /// 6062 /// Individual bit fields 6063 /// 6064 struct { 6065 /// 6066 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware 6067 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2` 6068 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). 6069 /// 6070 UINT32 ResourceMonitoringID : 32; 6071 /// 6072 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on 6073 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H, 6074 /// ECX=0):EBX.[15] = 1 ). 6075 /// 6076 UINT32 COS : 32; 6077 } Bits; 6078 /// 6079 /// All bit fields as a 64-bit value 6080 /// 6081 UINT64 Uint64; 6082 } MSR_IA32_PQR_ASSOC_REGISTER; 6083 6084 /** 6085 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H, 6086 ECX=0H):EBX[14] = 1). 6087 6088 @param ECX MSR_IA32_BNDCFGS (0x00000D90) 6089 @param EAX Lower 32-bits of MSR value. 6090 Described by the type MSR_IA32_BNDCFGS_REGISTER. 6091 @param EDX Upper 32-bits of MSR value. 6092 Described by the type MSR_IA32_BNDCFGS_REGISTER. 6093 6094 <b>Example usage</b> 6095 @code 6096 MSR_IA32_BNDCFGS_REGISTER Msr; 6097 6098 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS); 6099 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64); 6100 @endcode 6101 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM. 6102 **/ 6103 #define MSR_IA32_BNDCFGS 0x00000D90 6104 6105 /** 6106 MSR information returned for MSR index #MSR_IA32_BNDCFGS 6107 **/ 6108 typedef union { 6109 /// 6110 /// Individual bit fields 6111 /// 6112 struct { 6113 /// 6114 /// [Bit 0] EN: Enable Intel MPX in supervisor mode. 6115 /// 6116 UINT32 EN : 1; 6117 /// 6118 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch 6119 /// instructions in the absence of the BND prefix. 6120 /// 6121 UINT32 BNDPRESERVE : 1; 6122 UINT32 Reserved : 10; 6123 /// 6124 /// [Bits 31:12] Base Address of Bound Directory. 6125 /// 6126 UINT32 Base : 20; 6127 /// 6128 /// [Bits 63:32] Base Address of Bound Directory. 6129 /// 6130 UINT32 BaseHi : 32; 6131 } Bits; 6132 /// 6133 /// All bit fields as a 64-bit value 6134 /// 6135 UINT64 Uint64; 6136 } MSR_IA32_BNDCFGS_REGISTER; 6137 6138 /** 6139 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1. 6140 6141 @param ECX MSR_IA32_XSS (0x00000DA0) 6142 @param EAX Lower 32-bits of MSR value. 6143 Described by the type MSR_IA32_XSS_REGISTER. 6144 @param EDX Upper 32-bits of MSR value. 6145 Described by the type MSR_IA32_XSS_REGISTER. 6146 6147 <b>Example usage</b> 6148 @code 6149 MSR_IA32_XSS_REGISTER Msr; 6150 6151 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS); 6152 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64); 6153 @endcode 6154 @note MSR_IA32_XSS is defined as IA32_XSS in SDM. 6155 **/ 6156 #define MSR_IA32_XSS 0x00000DA0 6157 6158 /** 6159 MSR information returned for MSR index #MSR_IA32_XSS 6160 **/ 6161 typedef union { 6162 /// 6163 /// Individual bit fields 6164 /// 6165 struct { 6166 UINT32 Reserved1 : 8; 6167 /// 6168 /// [Bit 8] Trace Packet Configuration State (R/W). 6169 /// 6170 UINT32 TracePacketConfigurationState : 1; 6171 UINT32 Reserved2 : 23; 6172 UINT32 Reserved3 : 32; 6173 } Bits; 6174 /// 6175 /// All bit fields as a 32-bit value 6176 /// 6177 UINT32 Uint32; 6178 /// 6179 /// All bit fields as a 64-bit value 6180 /// 6181 UINT64 Uint64; 6182 } MSR_IA32_XSS_REGISTER; 6183 6184 /** 6185 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1. 6186 6187 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0) 6188 @param EAX Lower 32-bits of MSR value. 6189 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. 6190 @param EDX Upper 32-bits of MSR value. 6191 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. 6192 6193 <b>Example usage</b> 6194 @code 6195 MSR_IA32_PKG_HDC_CTL_REGISTER Msr; 6196 6197 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL); 6198 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64); 6199 @endcode 6200 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM. 6201 **/ 6202 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0 6203 6204 /** 6205 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL 6206 **/ 6207 typedef union { 6208 /// 6209 /// Individual bit fields 6210 /// 6211 struct { 6212 /// 6213 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled 6214 /// logical processors in the package. See Section 14.5.2, "Package level 6215 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1. 6216 /// 6217 UINT32 HDC_Pkg_Enable : 1; 6218 UINT32 Reserved1 : 31; 6219 UINT32 Reserved2 : 32; 6220 } Bits; 6221 /// 6222 /// All bit fields as a 32-bit value 6223 /// 6224 UINT32 Uint32; 6225 /// 6226 /// All bit fields as a 64-bit value 6227 /// 6228 UINT64 Uint64; 6229 } MSR_IA32_PKG_HDC_CTL_REGISTER; 6230 6231 /** 6232 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1. 6233 6234 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1) 6235 @param EAX Lower 32-bits of MSR value. 6236 Described by the type MSR_IA32_PM_CTL1_REGISTER. 6237 @param EDX Upper 32-bits of MSR value. 6238 Described by the type MSR_IA32_PM_CTL1_REGISTER. 6239 6240 <b>Example usage</b> 6241 @code 6242 MSR_IA32_PM_CTL1_REGISTER Msr; 6243 6244 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1); 6245 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64); 6246 @endcode 6247 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM. 6248 **/ 6249 #define MSR_IA32_PM_CTL1 0x00000DB1 6250 6251 /** 6252 MSR information returned for MSR index #MSR_IA32_PM_CTL1 6253 **/ 6254 typedef union { 6255 /// 6256 /// Individual bit fields 6257 /// 6258 struct { 6259 /// 6260 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for 6261 /// package level HDC control. See Section 14.5.3. 6262 /// If CPUID.06H:EAX.[13] = 1. 6263 /// 6264 UINT32 HDC_Allow_Block : 1; 6265 UINT32 Reserved1 : 31; 6266 UINT32 Reserved2 : 32; 6267 } Bits; 6268 /// 6269 /// All bit fields as a 32-bit value 6270 /// 6271 UINT32 Uint32; 6272 /// 6273 /// All bit fields as a 64-bit value 6274 /// 6275 UINT64 Uint64; 6276 } MSR_IA32_PM_CTL1_REGISTER; 6277 6278 /** 6279 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1. 6280 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical 6281 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1. 6282 6283 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2) 6284 @param EAX Lower 32-bits of MSR value. 6285 @param EDX Upper 32-bits of MSR value. 6286 6287 <b>Example usage</b> 6288 @code 6289 UINT64 Msr; 6290 6291 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL); 6292 @endcode 6293 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM. 6294 **/ 6295 #define MSR_IA32_THREAD_STALL 0x00000DB2 6296 6297 /** 6298 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0] 6299 CPUID.80000001H:EDX.[2 9]). 6300 6301 @param ECX MSR_IA32_EFER (0xC0000080) 6302 @param EAX Lower 32-bits of MSR value. 6303 Described by the type MSR_IA32_EFER_REGISTER. 6304 @param EDX Upper 32-bits of MSR value. 6305 Described by the type MSR_IA32_EFER_REGISTER. 6306 6307 <b>Example usage</b> 6308 @code 6309 MSR_IA32_EFER_REGISTER Msr; 6310 6311 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); 6312 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64); 6313 @endcode 6314 @note MSR_IA32_EFER is defined as IA32_EFER in SDM. 6315 **/ 6316 #define MSR_IA32_EFER 0xC0000080 6317 6318 /** 6319 MSR information returned for MSR index #MSR_IA32_EFER 6320 **/ 6321 typedef union { 6322 /// 6323 /// Individual bit fields 6324 /// 6325 struct { 6326 /// 6327 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET 6328 /// instructions in 64-bit mode. 6329 /// 6330 UINT32 SCE : 1; 6331 UINT32 Reserved1 : 7; 6332 /// 6333 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode 6334 /// operation. 6335 /// 6336 UINT32 LME : 1; 6337 UINT32 Reserved2 : 1; 6338 /// 6339 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode 6340 /// is active when set. 6341 /// 6342 UINT32 LMA : 1; 6343 /// 6344 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W). 6345 /// 6346 UINT32 NXE : 1; 6347 UINT32 Reserved3 : 20; 6348 UINT32 Reserved4 : 32; 6349 } Bits; 6350 /// 6351 /// All bit fields as a 32-bit value 6352 /// 6353 UINT32 Uint32; 6354 /// 6355 /// All bit fields as a 64-bit value 6356 /// 6357 UINT64 Uint64; 6358 } MSR_IA32_EFER_REGISTER; 6359 6360 /** 6361 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. 6362 6363 @param ECX MSR_IA32_STAR (0xC0000081) 6364 @param EAX Lower 32-bits of MSR value. 6365 @param EDX Upper 32-bits of MSR value. 6366 6367 <b>Example usage</b> 6368 @code 6369 UINT64 Msr; 6370 6371 Msr = AsmReadMsr64 (MSR_IA32_STAR); 6372 AsmWriteMsr64 (MSR_IA32_STAR, Msr); 6373 @endcode 6374 @note MSR_IA32_STAR is defined as IA32_STAR in SDM. 6375 **/ 6376 #define MSR_IA32_STAR 0xC0000081 6377 6378 /** 6379 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. 6380 6381 @param ECX MSR_IA32_LSTAR (0xC0000082) 6382 @param EAX Lower 32-bits of MSR value. 6383 @param EDX Upper 32-bits of MSR value. 6384 6385 <b>Example usage</b> 6386 @code 6387 UINT64 Msr; 6388 6389 Msr = AsmReadMsr64 (MSR_IA32_LSTAR); 6390 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr); 6391 @endcode 6392 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM. 6393 **/ 6394 #define MSR_IA32_LSTAR 0xC0000082 6395 6396 /** 6397 IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL 6398 instruction is not recognized in compatibility mode. If 6399 CPUID.80000001:EDX.[29] = 1. 6400 6401 @param ECX MSR_IA32_CSTAR (0xC0000083) 6402 @param EAX Lower 32-bits of MSR value. 6403 @param EDX Upper 32-bits of MSR value. 6404 6405 <b>Example usage</b> 6406 @code 6407 UINT64 Msr; 6408 6409 Msr = AsmReadMsr64 (MSR_IA32_CSTAR); 6410 AsmWriteMsr64 (MSR_IA32_CSTAR, Msr); 6411 @endcode 6412 @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM. 6413 **/ 6414 #define MSR_IA32_CSTAR 0xC0000083 6415 6416 /** 6417 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1. 6418 6419 @param ECX MSR_IA32_FMASK (0xC0000084) 6420 @param EAX Lower 32-bits of MSR value. 6421 @param EDX Upper 32-bits of MSR value. 6422 6423 <b>Example usage</b> 6424 @code 6425 UINT64 Msr; 6426 6427 Msr = AsmReadMsr64 (MSR_IA32_FMASK); 6428 AsmWriteMsr64 (MSR_IA32_FMASK, Msr); 6429 @endcode 6430 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM. 6431 **/ 6432 #define MSR_IA32_FMASK 0xC0000084 6433 6434 /** 6435 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1. 6436 6437 @param ECX MSR_IA32_FS_BASE (0xC0000100) 6438 @param EAX Lower 32-bits of MSR value. 6439 @param EDX Upper 32-bits of MSR value. 6440 6441 <b>Example usage</b> 6442 @code 6443 UINT64 Msr; 6444 6445 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE); 6446 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr); 6447 @endcode 6448 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM. 6449 **/ 6450 #define MSR_IA32_FS_BASE 0xC0000100 6451 6452 /** 6453 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. 6454 6455 @param ECX MSR_IA32_GS_BASE (0xC0000101) 6456 @param EAX Lower 32-bits of MSR value. 6457 @param EDX Upper 32-bits of MSR value. 6458 6459 <b>Example usage</b> 6460 @code 6461 UINT64 Msr; 6462 6463 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE); 6464 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr); 6465 @endcode 6466 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM. 6467 **/ 6468 #define MSR_IA32_GS_BASE 0xC0000101 6469 6470 /** 6471 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. 6472 6473 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102) 6474 @param EAX Lower 32-bits of MSR value. 6475 @param EDX Upper 32-bits of MSR value. 6476 6477 <b>Example usage</b> 6478 @code 6479 UINT64 Msr; 6480 6481 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE); 6482 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr); 6483 @endcode 6484 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM. 6485 **/ 6486 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102 6487 6488 /** 6489 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1. 6490 6491 @param ECX MSR_IA32_TSC_AUX (0xC0000103) 6492 @param EAX Lower 32-bits of MSR value. 6493 Described by the type MSR_IA32_TSC_AUX_REGISTER. 6494 @param EDX Upper 32-bits of MSR value. 6495 Described by the type MSR_IA32_TSC_AUX_REGISTER. 6496 6497 <b>Example usage</b> 6498 @code 6499 MSR_IA32_TSC_AUX_REGISTER Msr; 6500 6501 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX); 6502 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64); 6503 @endcode 6504 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM. 6505 **/ 6506 #define MSR_IA32_TSC_AUX 0xC0000103 6507 6508 /** 6509 MSR information returned for MSR index #MSR_IA32_TSC_AUX 6510 **/ 6511 typedef union { 6512 /// 6513 /// Individual bit fields 6514 /// 6515 struct { 6516 /// 6517 /// [Bits 31:0] AUX: Auxiliary signature of TSC. 6518 /// 6519 UINT32 AUX : 32; 6520 UINT32 Reserved : 32; 6521 } Bits; 6522 /// 6523 /// All bit fields as a 32-bit value 6524 /// 6525 UINT32 Uint32; 6526 /// 6527 /// All bit fields as a 64-bit value 6528 /// 6529 UINT64 Uint64; 6530 } MSR_IA32_TSC_AUX_REGISTER; 6531 6532 #endif 6533