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/dports/devel/plan9port/plan9port-1f098efb7370a0b28306d10681e21883fb1c1507/font/lucsans/
H A Dboldlatin1.6.font2 0x0000 0x00FF lsb.10
H A Dboldlatin1.7.font2 0x0000 0x00FF lsb.12
H A Dboldunicode.6.font2 0x0000 0x00FF lsb.10
H A Dboldunicode.7.font2 0x0000 0x00FF lsb.12
H A Dboldlatin1.10.font2 0x0000 0x00FF lsb.18
H A Dlatin1b.7.font2 0x0000 0x00FF lsb.12
H A Dboldlatin1.13.font2 0x0000 0x00FF lsb.24
H A Dboldunicode.10.font2 0x0000 0x00FF lsb.18
/dports/devel/icestorm/icestorm-710470f9/icebox/
H A Dicebox_vlog.py733 def get_ram_wire(name, msb, lsb, default="1'b0"): argument
735 for i in range(msb, lsb-1, -1):
736 if msb != lsb:
/dports/devel/p5-subversion/subversion-1.14.1/tools/server-side/svnpubsub/rc.d/
H A Dsvnwcsub.debian13 . /lib/lsb/init-functions
H A Dsvnpubsub.debian13 . /lib/lsb/init-functions
/dports/devel/py-subversion/subversion-1.14.1/tools/server-side/svnpubsub/rc.d/
H A Dsvnwcsub.debian13 . /lib/lsb/init-functions
H A Dsvnpubsub.debian13 . /lib/lsb/init-functions
/dports/deskutils/calibre/calibre-src-5.34.0/src/calibre/utils/fonts/sfnt/
H A Dhead.py121 lsb = self.left_side_bearings[glyph_id]
124 return self.advance_widths[glyph_id], lsb
/dports/deskutils/calibre/calibre-src-5.34.0/src/calibre/gui2/tweak_book/diff/
H A Dview.py757 lsb, lcb = self.left_insert(alo, ahi)
760 rtop=rsb, rbot=rcb, ltop=lsb, lbot=lcb, kind='equal'))
869 lsb, lcb = self.left_insert(alo, ahi)
872 rtop=rsb, rbot=rcb, ltop=lsb, lbot=lcb, kind='replace'))
877 …lsb, rsb = self.left.document().findBlockByNumber(lsb), self.right.document().findBlockByNumber(rs…
897 lsb, lpos, lfmts = do_tag(lsb, ll, llo, lhi, lpos, lfmts)
899 for block, fmts in ((lsb, lfmts), (rsb, rfmts)):
/dports/databases/rrdtool/rrdtool-1.7.2/
H A Dconfigure27303 "etc/rrdcached-default-lsb") CONFIG_FILES="$CONFIG_FILES etc/rrdcached-default-lsb" ;;
/dports/databases/rrdtool/rrdtool-1.7.2/etc/
H A DMakefile.in110 rrdcached-default-lsb
162 $(srcdir)/rrdcached-default-lsb.in \
367 EXTRA_DIST = rrdcached-default-redhat rrdcached-init-redhat rrdcached-default-lsb.in \
368 rrdcached-init-lsb rrdcached.socket.in rrdcached.service.in
410 rrdcached-default-lsb: $(top_builddir)/config.status $(srcdir)/rrdcached-default-lsb.in
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/firmware/fx2/utils/
H A Dbuild_eeprom.py38 def lsb (x): function
63 lsb (VID),
65 lsb (PID),
67 lsb (devid),
76 lsb (len (out_bytes)),
78 lsb (start_addr)
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/rtl/verilog/
H A Dspi_shift.v43 module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
53 input lsb; // lbs first on the line port
79 assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
80 …assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} :…
H A Dspi_top.v93 wire lsb; // lsb first on line net
233 assign lsb = ctrl[`SPI_CTRL_LSB];
282 .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb),
H A Dspi_top16.v72 wire lsb; // lsb first on line net
150 assign lsb = ctrl[`SPI_CTRL_LSB];
177 .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/
H A Dxwr_streamers.vhd433 -- Otherwise, during the transition (e.g. between writing lsb and msb of MAC), the
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/common/
H A Dgc_crc_gen.vhd160 report "g_polynomial must have lsb set to 1!"
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/cpld/
H A DTopCpld.vhd748 -- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before
892 -- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/rtl/verilog/
H A Dspi_top.v91 wire lsb; // lsb first on line net
231 assign lsb = ctrl[`SPI_CTRL_LSB];
280 .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb),

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