| /dports/x11-toolkits/p5-Prima/Prima-1.63/win32/ |
| H A D | widgets.c | 1661 Bool ena = true; in apc_widget_is_responsive() local
|
| /dports/x11-toolkits/p5-Prima/Prima-1.63/unix/ |
| H A D | apc_widget.c | 827 Bool ena = true; in apc_widget_is_responsive() local
|
| /dports/print/scribus-devel/scribus-1.5.7/scribus/ |
| H A D | canvasmode_editarc.cpp | 243 QLineF ena = bb.map(inp); in applyValues() local
|
| /dports/multimedia/libv4l/v4l-utils-4l-utils-1.20.0/utils/common/ |
| H A D | cv4l-helpers.h | 567 int ena = enable; in overlay() local
|
| /dports/multimedia/v4l_compat/v4l-utils-4l-utils-1.20.0/utils/common/ |
| H A D | cv4l-helpers.h | 567 int ena = enable; in overlay() local
|
| /dports/multimedia/v4l-utils/v4l-utils-4l-utils-1.20.0/utils/common/ |
| H A D | cv4l-helpers.h | 567 int ena = enable; in overlay() local
|
| /dports/misc/rump/buildrump.sh-b914579/src/sys/netinet/ |
| H A D | ip_carp.c | 1378 u_int8_t *ena; in carp_ourether() local
|
| /dports/graphics/opencollada/OpenCOLLADA-1.6.68/Externals/MayaDataModel/include/ |
| H A D | MayaDMDynamicConstraint.h | 54 void setEnable(bool ena) in setEnable()
|
| H A D | MayaDMNucleus.h | 37 void setEnable(bool ena) in setEnable()
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | ram_2port.v | 63 input wire ena, port
|
| H A D | ram_2port_impl.vh | 18 input wire ena, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | i2c_master_byte_ctrl.v | 85 input ena; // core enable signal port
|
| H A D | i2c_master_bit_ctrl.v | 145 input ena; // core enable signal port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | ram_2port.v | 24 input ena, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/i2c/rtl/vhdl/ |
| H A D | i2c_master_byte_ctrl.vhd | 86 ena : in std_logic; -- core enable signal port
121 ena : in std_logic; -- core enable signal port in i2c_master_byte_ctrl.structural.i2c_master_bit_ctrl
|
| H A D | i2c_master_top.vhd | 109 ena : in std_logic; -- core enable signal port in i2c_master_top.structural.i2c_master_byte_ctrl
|
| H A D | i2c_master_bit_ctrl.vhd | 145 ena : in std_logic; -- core enable signal port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/i2c/rtl/verilog/ |
| H A D | i2c_master_byte_ctrl.v | 85 input ena; // core enable signal port
|
| H A D | i2c_master_bit_ctrl.v | 145 input ena; // core enable signal port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_2k.v | 2234 wire ena; net
2361 wire ena; net
|
| H A D | fifo_4k.v | 2326 wire ena; net
2461 wire ena; net
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/latency/lib/ |
| H A D | Responder.cpp | 285 void Responder::set_usrp_rx_dc_offset(uhd::usrp::multi_usrp::sptr usrp, bool ena) in set_usrp_rx_dc_offset()
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm.c | 720 LLVMValueRef ena, count = initial[3]; in si_build_wrapper_function() local
798 LLVMValueRef ena, count = initial[3]; in si_build_wrapper_function() local
|
| /dports/sysutils/py-salt/salt-3004.1/salt/modules/ |
| H A D | slackware_service.py | 270 def _rcd_mode(name, ena): argument
|
| /dports/devel/umbrello/umbrello-21.12.3/lib/cppparser/ |
| H A D | parser.cpp | 2254 EnumeratorAST::Node ena = CreateNode<EnumeratorAST>(); in parseEnumerator() local
|