| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 101 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
124 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
354 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
421 const MCOperand &MO1 = MI->getOperand(Op); in printAM2PreOrOffsetIndexOp() local
450 const MCOperand &MO1 = MI->getOperand(Op); in printAddrModeTBB() local
462 const MCOperand &MO1 = MI->getOperand(Op); in printAddrModeTBH() local
474 const MCOperand &MO1 = MI->getOperand(Op); in printAddrMode2Operand() local
519 const MCOperand &MO1 = MI->getOperand(Op); in printAM3PreOrOffsetIndexOp() local
548 const MCOperand &MO1 = MI->getOperand(Op); in printAddrMode3Operand() local
1090 const MCOperand &MO1 = MI->getOperand(Op); in printThumbAddrModeRROperand() local
[all …]
|
| H A D | ARMMCCodeEmitter.cpp | 595 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local
930 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local
1185 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local
1252 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getLdStSORegOpValue() local
1289 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode2OffsetOpValue() local
1311 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getPostIdxRegOpValue() local
1325 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode3OffsetOpValue() local
1346 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode3OpValue() local
1593 const MCOperand &MO1 = MI.getOperand(OpNum); in getT2AddrModeSORegOpValue() local
1613 const MCOperand &MO1 = MI.getOperand(OpNum); in getT2AddrModeImmOpValue() local
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCCodeEmitter.cpp | 123 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp()
214 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp()
|
| H A D | X86RegisterInfo.cpp | 901 MachineOperand &MO1 = MI->getOperand(1); in getTileShape() local
|
| H A D | X86FloatingPoint.cpp | 1463 const MachineOperand &MO1 = MI.getOperand(1); in handleSpecialFP() local
|
| H A D | X86InstrInfo.cpp | 6359 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 200 auto MO1 = *L1->memoperands().begin(); in getHazardType() local
|
| H A D | ARMAsmPrinter.cpp | 956 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableAddrs() local
1002 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableInsts() local
1032 const MachineOperand &MO1 = MI->getOperand(1); in emitJumpTableTBInst() local
|
| H A D | ARMExpandPseudoInsts.cpp | 2392 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
2450 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI() local
|
| H A D | ARMBaseInstrInfo.cpp | 1850 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue() local
1906 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 462 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1234 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst()
1596 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1611 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
|
| H A D | AArch64InstPrinter.cpp | 1111 const MCOperand MO1 = MI->getOperand(OpNum + 1); in printAMIndexedWB() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 902 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1187 const MachineOperand &MO1 = MI.getOperand(I1); in allocateInstruction() local
|
| H A D | MachineVerifier.cpp | 2562 const MachineOperand &MO1 = Phi.getOperand(I + 1); in checkPHIOps() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 409 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1114 MachineOperand &MO1 = MI.getOperand(1); in narrowScalar() local
|