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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1640 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd()
1662 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor()
1670 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot()
1678 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) { in buildNeg()
1684 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { in buildCTPOP()
1689 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ()
1699 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ()
1840 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, in buildSMin()
1846 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, in buildSMax()
1852 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, in buildUMin()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp97 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
223 const MachineOperand &Src0 = MI.getOperand(0); in shrinkScalarCompare() local
392 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma() local
486 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
819 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
H A DSIPeepholeSDWA.cpp539 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
579 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
647 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
663 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
959 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { in isConvertibleToSDWA() local
1011 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA() local
H A DAMDGPUInstCombineIntrinsic.cpp44 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN()
423 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
507 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
536 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
639 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
712 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
H A DR600ExpandSpecialInstrs.cpp146 Register Src0 = in runOnMachineFunction() local
198 Register Src0 = in runOnMachineFunction() local
H A DSIOptimizeExecMasking.cpp516 MachineOperand &Src0 = SaveExecInst->getOperand(1); in optimizeExecSequence() local
563 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence() local
658 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence() local
H A DSIFoldOperands.cpp1029 MachineOperand *Src0 = getImmOrMaterializedImm(MI->getOperand(Src0Idx)); in tryConstantFoldOp() local
1127 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask() local
1165 MachineOperand *Src0 = getImmOrMaterializedImm(MI.getOperand(1)); in tryFoldZeroHighBits() local
1335 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp() local
1462 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
1496 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
H A DSIModeRegister.cpp182 MachineOperand Src0 = MI.getOperand(1); in getInstructionMode() local
199 MachineOperand Src0 = MI.getOperand(1); in getInstructionMode() local
H A DGCNDPPCombine.cpp279 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst() local
647 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov() local
H A DSIInstrInfo.cpp2414 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
5946 Register Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
6616 MachineOperand &Src0 = Inst.getOperand(1); in lowerSelect() local
6718 MachineOperand &Src0 = Inst.getOperand(1); in lowerScalarXnor() local
6784 MachineOperand &Src0 = Inst.getOperand(1); in splitScalarNotBinop() local
6813 MachineOperand &Src0 = Inst.getOperand(1); in splitScalarBinOpN2() local
6840 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitUnaryOp() local
6909 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitAddSub() local
6973 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitBinaryOp() local
7040 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitXnor() local
[all …]
H A DGCNVOPDUtils.cpp83 const MachineOperand &Src0 = MI.getOperand(VOPD::Component::SRC0); in checkVOPDRegConstraints() local
H A DSILoadStoreOptimizer.cpp1543 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair() local
1641 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeFlatStorePair() local
1867 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair() local
2035 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset() local
H A DAMDGPUPostLegalizerCombiner.cpp256 Register Src0; in matchCvtF32UByteN() local
H A DAMDGPURegBankCombiner.cpp279 MachineInstr *Src0 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in matchFPMed3ToClamp() local
H A DSIISelLowering.cpp4016 MachineOperand &Src0 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
4040 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
4080 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
4966 SDValue Src0 = N->getOperand(1); in lowerFCMPIntrinsic() local
5042 SDValue Src0 = N->getOperand(1); in ReplaceNodeResults() local
5054 SDValue Src0 = N->getOperand(1); in ReplaceNodeResults() local
8043 SDValue Src0 = Op.getOperand(4); in LowerINTRINSIC_VOID() local
9003 SDValue Src0 = Op.getOperand(0); in LowerFDIV16() local
10691 SDValue Src0 = N->getOperand(0); in performFMed3Combine() local
10728 SDValue Src0 = N->getOperand(0); in performCvtPkRTZCombine() local
[all …]
H A DAMDGPUPromoteAlloca.cpp1040 Value *Src0 = CI->getOperand(0); in handleAlloca() local
H A DSIFixSGPRCopies.cpp699 MachineOperand &Src0 = MI.getOperand(Src0Idx); in runOnMachineFunction() local
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp103 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1, in computeKnownBitsMin()
597 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1, in computeNumSignBitsMin()
H A DCSEMIRBuilder.cpp242 const SrcOp &Src0 = SrcOps[0]; in buildInstr() local
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp53 Register Dest0, Register Dest1, Register Src0, in PairedCopy()
/openbsd/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp148 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedLoad() local
418 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedGather() local
H A DInferAddressSpaces.cpp698 Constant *Src0 = CE->getOperand(1); in cloneConstantExprWithNewAddressSpace() local
909 Value *Src0 = Op.getOperand(1); in updateAddressSpace() local
/openbsd/gnu/llvm/clang/lib/CodeGen/
H A DCGBuiltin.cpp481 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitUnaryMaybeConstrainedFPBuiltin() local
498 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitBinaryMaybeConstrainedFPBuiltin() local
516 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitTernaryMaybeConstrainedFPBuiltin() local
554 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitUnaryBuiltin() local
564 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitBinaryBuiltin() local
575 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitTernaryBuiltin() local
587 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitFPIntBuiltin() local
600 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitMaybeConstrainedFPToIntRoundBuiltin() local
16965 Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitAMDGPUBuiltinExpr() local
16971 Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitAMDGPUBuiltinExpr() local
[all …]
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4360 auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, in visitMaskedStore()
4361 MaybeAlign &Alignment) { in visitMaskedStore()
4377 SDValue Src0 = getValue(Src0Operand); in visitMaskedStore() local
4471 SDValue Src0 = getValue(I.getArgOperand(0)); in visitMaskedScatter() local
4524 auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, in visitMaskedLoad()
4525 MaybeAlign &Alignment) { in visitMaskedLoad()
4541 SDValue Src0 = getValue(Src0Operand); in visitMaskedLoad() local
4575 SDValue Src0 = getValue(I.getArgOperand(3)); in visitMaskedGather() local

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