1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
netname(std::set<std::string> & conntypes_code,std::set<std::string> & celltypes_code,std::set<std::string> & constcells_code,RTLIL::SigSpec sig)30 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
31 {
32 if (!sig.is_fully_const() && !sig.is_wire())
33 log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
34
35 conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
36
37 if (sig.is_fully_const()) {
38 celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size()));
39 constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n",
40 sig.size(), sig.as_int(), sig.size(), sig.size(), sig.as_int(), sig.as_int()));
41 return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
42 }
43
44 return RTLIL::unescape_id(sig.as_wire()->name);
45 }
46
47 struct IntersynthBackend : public Backend {
IntersynthBackendIntersynthBackend48 IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
helpIntersynthBackend49 void help() override
50 {
51 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
52 log("\n");
53 log(" write_intersynth [options] [filename]\n");
54 log("\n");
55 log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
56 log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
57 log("\n");
58 log(" -notypes\n");
59 log(" do not generate celltypes and conntypes commands. i.e. just output\n");
60 log(" the netlists. this is used for postsilicon synthesis.\n");
61 log("\n");
62 log(" -lib <verilog_or_rtlil_file>\n");
63 log(" Use the specified library file for determining whether cell ports are\n");
64 log(" inputs or outputs. This option can be used multiple times to specify\n");
65 log(" more than one library.\n");
66 log("\n");
67 log(" -selected\n");
68 log(" only write selected modules. modules must be selected entirely or\n");
69 log(" not at all.\n");
70 log("\n");
71 log("http://bygone.clairexen.net/intersynth/\n");
72 log("\n");
73 }
executeIntersynthBackend74 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
75 {
76 log_header(design, "Executing INTERSYNTH backend.\n");
77 log_push();
78
79 std::vector<std::string> libfiles;
80 std::vector<RTLIL::Design*> libs;
81 bool flag_notypes = false;
82 bool selected = false;
83
84 size_t argidx;
85 for (argidx = 1; argidx < args.size(); argidx++)
86 {
87 if (args[argidx] == "-notypes") {
88 flag_notypes = true;
89 continue;
90 }
91 if (args[argidx] == "-lib" && argidx+1 < args.size()) {
92 libfiles.push_back(args[++argidx]);
93 continue;
94 }
95 if (args[argidx] == "-selected") {
96 selected = true;
97 continue;
98 }
99 break;
100 }
101 extra_args(f, filename, args, argidx);
102
103 log("Output filename: %s\n", filename.c_str());
104
105 for (auto filename : libfiles) {
106 std::ifstream f;
107 f.open(filename.c_str());
108 if (f.fail())
109 log_error("Can't open lib file `%s'.\n", filename.c_str());
110 RTLIL::Design *lib = new RTLIL::Design;
111 Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
112 libs.push_back(lib);
113 }
114
115 if (libs.size() > 0)
116 log_header(design, "Continuing INTERSYNTH backend.\n");
117
118 std::set<std::string> conntypes_code, celltypes_code;
119 std::string netlists_code;
120 CellTypes ct(design);
121
122 for (auto lib : libs)
123 ct.setup_design(lib);
124
125 for (auto module : design->modules())
126 {
127 SigMap sigmap(module);
128
129 if (module->get_blackbox_attribute())
130 continue;
131 if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells().size() == 0)
132 continue;
133
134 if (selected && !design->selected_whole_module(module->name)) {
135 if (design->selected_module(module->name))
136 log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
137 continue;
138 }
139
140 log("Generating netlist %s.\n", log_id(module->name));
141
142 if (module->memories.size() != 0 || module->processes.size() != 0)
143 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
144
145 std::set<std::string> constcells_code;
146 netlists_code += stringf("# Netlist of module %s\n", log_id(module->name));
147 netlists_code += stringf("netlist %s\n", log_id(module->name));
148
149 // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
150 for (auto wire : module->wires()) {
151 if (wire->port_input || wire->port_output) {
152 celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
153 log_id(wire->name), wire->width, wire->port_input ? "*" : "",
154 wire->port_input ? "input" : "output", log_id(wire->name), wire->width, log_id(wire->name)));
155 netlists_code += stringf("node %s %s PORT %s\n", log_id(wire->name), log_id(wire->name),
156 netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
157 }
158 }
159
160 // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
161 for (auto cell : module->cells())
162 {
163 std::string celltype_code, node_code;
164
165 if (!ct.cell_known(cell->type))
166 log_error("Found unknown cell type %s in module!\n", log_id(cell->type));
167
168 celltype_code = stringf("celltype %s", log_id(cell->type));
169 node_code = stringf("node %s %s", log_id(cell->name), log_id(cell->type));
170 for (auto &port : cell->connections()) {
171 RTLIL::SigSpec sig = sigmap(port.second);
172 if (sig.size() != 0) {
173 conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
174 celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", log_id(port.first));
175 node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
176 }
177 }
178 for (auto ¶m : cell->parameters) {
179 celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
180 if (param.second.bits.size() != 32) {
181 node_code += stringf(" %s '", log_id(param.first));
182 for (int i = param.second.bits.size()-1; i >= 0; i--)
183 node_code += param.second.bits[i] == State::S1 ? "1" : "0";
184 } else
185 node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int());
186 }
187
188 celltypes_code.insert(celltype_code + "\n");
189 netlists_code += node_code + "\n";
190 }
191
192 if (constcells_code.size() > 0)
193 netlists_code += "# constant cells\n";
194 for (auto code : constcells_code)
195 netlists_code += code;
196 netlists_code += "\n";
197 }
198
199 if (!flag_notypes) {
200 *f << stringf("### Connection Types\n");
201 for (auto code : conntypes_code)
202 *f << stringf("%s", code.c_str());
203 *f << stringf("\n### Cell Types\n");
204 for (auto code : celltypes_code)
205 *f << stringf("%s", code.c_str());
206 }
207 *f << stringf("\n### Netlists\n");
208 *f << stringf("%s", netlists_code.c_str());
209
210 for (auto lib : libs)
211 delete lib;
212
213 log_pop();
214 }
215 } IntersynthBackend;
216
217 PRIVATE_NAMESPACE_END
218