| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/riscv/kernel/ |
| H A D | head.S | 394 csrr t0, CSR_MISA
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 295 #define CSR_MISA 0x301 macro
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/riscv/kernel/ |
| H A D | head.S | 394 csrr t0, CSR_MISA
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 295 #define CSR_MISA 0x301 macro
|
| /dports/multimedia/libv4l/linux-5.13-rc2/arch/riscv/kernel/ |
| H A D | head.S | 394 csrr t0, CSR_MISA
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/opensbi/firmware/ |
| H A D | fw_base.S | 420 csrr a5, CSR_MISA
431 csrr a5, CSR_MISA
|
| /dports/sysutils/opensbi/opensbi-0.9/firmware/ |
| H A D | fw_base.S | 420 csrr a5, CSR_MISA
431 csrr a5, CSR_MISA
|
| /dports/emulators/qemu/qemu-6.2.0/roms/opensbi/firmware/ |
| H A D | fw_base.S | 420 csrr a5, CSR_MISA
431 csrr a5, CSR_MISA
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 248 #define CSR_MISA 0x301 macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 233 #define CSR_MISA 0x301 macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 324 #define CSR_MISA 0x301 macro
|
| /dports/sysutils/opensbi/opensbi-0.9/include/sbi/ |
| H A D | riscv_encoding.h | 324 #define CSR_MISA 0x301 macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/opensbi/include/sbi/ |
| H A D | riscv_encoding.h | 324 #define CSR_MISA 0x301 macro
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.h | 613 #define CSR_MISA 0x301 macro
1102 DECLARE_CSR(misa, CSR_MISA)
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 662 #define CSR_MISA 0x301 macro
1203 DECLARE_CSR(misa, CSR_MISA)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | processor.cc | 354 csrmap[CSR_MISA] = misa = std::make_shared<misa_csr_t>(proc, CSR_MISA, max_isa); in reset()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/ |
| H A D | csr.c | 915 [CSR_MISA] = { any, read_misa, write_misa },
|
| /dports/emulators/qemu42/qemu-4.2.1/target/riscv/ |
| H A D | csr.c | 915 [CSR_MISA] = { any, read_misa, write_misa },
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 714 #define CSR_MISA 0x301 macro
1257 DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 714 #define CSR_MISA 0x301 macro
1257 DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 714 #define CSR_MISA 0x301 macro
1257 DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 714 #define CSR_MISA 0x301 macro
1257 DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | riscv-011.c | 1570 if (read_remote_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) { in examine()
1572 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA, in examine()
|
| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | csr.c | 1406 [CSR_MISA] = { any, read_misa, write_misa },
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/ |
| H A D | csr.c | 1305 [CSR_MISA] = { any, read_misa, write_misa },
|