/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF548-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF549-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF548-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF549-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF548-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF549-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF548-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF549-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF548-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 1422 #define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count … 1423 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 1424 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf548/ |
H A D | ADSP-EDN-BF542-extended_cdef.h | 951 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 952 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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H A D | ADSP-EDN-BF544-extended_cdef.h | 951 #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) 952 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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