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Searched refs:SPORT0_MRCS1 (Results 76 – 100 of 126) sorted by relevance

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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_def.h1762 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1… macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_def.h1758 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1… macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/
H A DADSP-EDN-BF549-extended_def.h1762 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1… macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/
H A DcdefBF539.h320 #define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
H A DdefBF534.h185 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ macro
H A DdefBF549.h86 #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Regis… macro
H A DcdefBF50x_base.h207 #define pSPORT0_MRCS1 ((volatile uint32_t *)SPORT0_MRCS1)
H A DdefBF50x_base.h202 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf561/
H A DBF561_cdef.h1232 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
1233 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DADSP-EDN-BF534-extended_cdef.h350 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel …
351 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
352 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf537/
H A DBF534_cdef.h238 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
239 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf506/
H A DBF504_cdef.h242 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
243 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)

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