/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | Register.h | 20 unsigned Reg; variable 45 return MCRegister::isStackSlot(Reg); in isStackSlot() 52 static int stackSlot2Index(Register Reg) { in stackSlot2Index() argument 111 assert(Reg == MCRegister::NoRegister || in asMCReg() 113 return MCRegister(Reg); in asMCReg() 120 return Reg == Other.Reg; 123 return Reg != Other.Reg; 126 return Reg == Other.id(); 129 return Reg != Other.id(); 142 return Reg == unsigned(Other); [all …]
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H A D | MachineRegisterInfo.h | 129 return MO->Contents.Reg.Next; in getNextOperandForReg() 453 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; in getVRegName() 461 VReg2Name.grow(Reg); in insertVRegByName() 462 VReg2Name[Reg] = Name.str(); in insertVRegByName() 475 def_iterator DI = def_begin(Reg); in getOneDef() 698 return VRegInfo[Reg].first; in getRegClassOrRegBank() 709 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank() 761 LLT getType(Register Reg) const { in getType() argument 762 if (Reg.isVirtual() && VRegToType.inBounds(Reg)) in getType() 763 return VRegToType[Reg]; in getType() [all …]
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H A D | LiveIntervals.h | 113 if (hasInterval(Reg)) in getInterval() 114 return *VirtRegIntervals[Reg.id()]; in getInterval() 123 bool hasInterval(Register Reg) const { in hasInterval() argument 125 VirtRegIntervals[Reg.id()]; in hasInterval() 131 VirtRegIntervals.grow(Reg.id()); in createEmptyInterval() 132 VirtRegIntervals[Reg.id()] = createInterval(Reg); in createEmptyInterval() 133 return *VirtRegIntervals[Reg.id()]; in createEmptyInterval() 146 return hasInterval(Reg) ? getInterval(Reg) : createEmptyInterval(Reg); in getOrCreateEmptyInterval() 150 void removeInterval(Register Reg) { in removeInterval() argument 151 delete VirtRegIntervals[Reg]; in removeInterval() [all …]
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H A D | LiveVariables.h | 147 bool HandlePhysRegKill(Register Reg, MachineInstr *MI); 152 void HandlePhysRegUse(Register Reg, MachineInstr &MI); 153 void HandlePhysRegDef(Register Reg, MachineInstr *MI, 159 MachineInstr *FindLastRefOrPartRef(Register Reg); 164 MachineInstr *FindLastPartialDef(Register Reg, 188 void recomputeForSingleDefVirtReg(Register Reg); 210 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterKilled() 245 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterDead() 250 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) { in removeVirtualRegisterDead() 269 VarInfo &getVarInfo(Register Reg); [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64TargetStreamer.h | 50 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument 51 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument 52 virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegP() argument 53 virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegPX() argument 55 virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFReg() argument 56 virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegX() argument 57 virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegP() argument 117 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override; 118 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override; 119 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override; [all …]
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H A D | AArch64WinCOFFStreamer.cpp | 107 emitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in emitARM64WinCFISaveReg() 112 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in emitARM64WinCFISaveRegX() 117 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in emitARM64WinCFISaveRegP() 122 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in emitARM64WinCFISaveRegPX() 127 emitARM64WinUnwindCode(Win64EH::UOP_SaveLRPair, Reg, Offset); in emitARM64WinCFISaveLRPair() 134 emitARM64WinUnwindCode(Win64EH::UOP_SaveFReg, Reg, Offset); in emitARM64WinCFISaveFReg() 139 emitARM64WinUnwindCode(Win64EH::UOP_SaveFRegX, Reg, Offset); in emitARM64WinCFISaveFRegX() 144 emitARM64WinUnwindCode(Win64EH::UOP_SaveFRegP, Reg, Offset); in emitARM64WinCFISaveFRegP() 149 emitARM64WinUnwindCode(Win64EH::UOP_SaveFRegPX, Reg, Offset); in emitARM64WinCFISaveFRegPX() 236 emitARM64WinUnwindCode(Win64EH::UOP_SaveAnyRegI, Reg, Offset); in emitARM64WinCFISaveAnyRegI() [all …]
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H A D | AArch64ELFStreamer.cpp | 68 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override { in emitARM64WinCFISaveReg() argument 69 OS << "\t.seh_save_reg\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveReg() 71 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegX() argument 72 OS << "\t.seh_save_reg_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegX() 74 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegP() argument 75 OS << "\t.seh_save_regp\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegP() 78 OS << "\t.seh_save_regp_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegPX() 81 OS << "\t.seh_save_lrpair\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveLRPair() 83 void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) override { in emitARM64WinCFISaveFReg() argument 84 OS << "\t.seh_save_freg\td" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveFReg() [all …]
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H A D | AArch64InstPrinter.cpp | 1351 if (Reg < AArch64::PN0 || Reg > AArch64::PN15) in printPredicateAsCounter() 1601 return Reg; in getNextVectorRegister() 1638 if (Reg == 0) in printMatrixTileList() 1696 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList() 1704 Reg < getNextVectorRegister(Reg, NumRegs - 1)) { in printVectorList() 1716 ++i, Reg = getNextVectorRegister(Reg, Stride)) { in printVectorList() 1866 return (Reg && (Read ? Reg->Readable : Reg->Writeable) && in isValidSysReg() 1880 if (Reg && !isValidSysReg(Reg, Read, STI)) in lookupSysReg() 1881 Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName); in lookupSysReg() 1883 return Reg; in lookupSysReg() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 85 if (Reg.isPhysical()) in constrainRegClass() 87 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass() 147 VRegInfo.grow(Reg); in createIncompleteVirtualRegister() 150 return Reg; in createIncompleteVirtualRegister() 167 return Reg; in createVirtualRegister() 176 return Reg; in cloneVirtualRegister() 190 setType(Reg, Ty); in createGenericVirtualRegister() 192 return Reg; in createGenericVirtualRegister() 204 verifyUseList(Reg); in clearVirtRegs() 442 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn() [all …]
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H A D | AggressiveAntiDepBreaker.cpp | 83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local 84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs() 85 Regs.push_back(Reg); in GetGroupRegs() 117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive() 172 unsigned Reg = *I; in StartBlock() local 203 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local 212 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe() 229 if (Reg == 0) in IsImplicitDefUse() 313 RegRefs.erase(Reg); in HandleLastUse() 502 FirstReg = Reg; in ScanInstruction() [all …]
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H A D | LiveVariables.cpp | 86 VirtRegInfo.grow(Reg); in getVarInfo() 87 return VirtRegInfo[Reg]; in getVarInfo() 353 if (!PhysRegUse[Reg]) { in HandlePhysRegKill() 358 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill() 413 for (unsigned Reg = 1; Reg != NumRegs; ++Reg) { in HandleRegMask() local 415 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) in HandleRegMask() 435 if (PhysRegDef[Reg] || PhysRegUse[Reg]) { in HandlePhysRegDef() 634 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction() 635 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); in runOnMachineFunction() 637 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); in runOnMachineFunction() [all …]
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H A D | CriticalAntiDepBreaker.cpp | 70 unsigned Reg = *AI; in StartBlock() local 84 unsigned Reg = *I; in StartBlock() local 88 unsigned Reg = *AI; in StartBlock() local 91 DefIndices[Reg] = ~0u; in StartBlock() 114 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local 121 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { in Observe() 185 if (Reg == 0) continue; in PrescanInstruction() 194 Classes[Reg] = NewRC; in PrescanInstruction() 226 if (!Reg.isValid()) in PrescanInstruction() 311 if (Reg == 0) continue; in ScanInstruction() [all …]
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H A D | FixupStatepointCallerSaved.cpp | 118 return Reg; in performCopyPropagation() 122 return Reg; in performCopyPropagation() 137 return Reg; in performCopyPropagation() 141 return Reg; in performCopyPropagation() 146 return Reg; in performCopyPropagation() 257 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() 367 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; } in isCalleeSaved() argument 391 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !GCRegs.contains(Reg))) in findRegistersToSpill() 420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters() 462 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) { in insertReloads() [all …]
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H A D | RegisterScavenging.cpp | 65 SI.Reg = 0; in init() 89 I.Reg = 0; in backward() 96 if (isReserved(Reg)) in isRegUsed() 106 return Reg; in FindUnusedReg() 115 if (!isRegUsed(Reg)) in getRegsAvailable() 116 Mask.set(Reg); in getRegsAvailable() 153 if (!MRI.isReserved(Reg) && Used.available(Reg) && in findSurvivorBackwards() 178 if (!MRI.isReserved(Reg) && Used.available(Reg)) { in findSurvivorBackwards() 266 Scavenged[SI].Reg = Reg; in spill() 314 return Reg; in scavengeRegisterBackwards() [all …]
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H A D | MachineInstrBundle.cpp | 159 Register Reg = MO.getReg(); in finalizeBundle() local 160 if (!Reg) in finalizeBundle() 163 if (LocalDefSet.count(Reg)) { in finalizeBundle() 182 Register Reg = MO.getReg(); in finalizeBundle() local 183 if (!Reg) in finalizeBundle() 187 LocalDefs.push_back(Reg); in finalizeBundle() 189 DeadDefSet.insert(Reg); in finalizeBundle() 193 KilledDefSet.erase(Reg); in finalizeBundle() 196 DeadDefSet.erase(Reg); in finalizeBundle() 211 for (Register Reg : LocalDefs) { in finalizeBundle() local [all …]
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H A D | LivePhysRegs.cpp | 88 if (!Reg.isPhysical()) in stepForward() 97 removeReg(Reg); in stepForward() 108 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward() 111 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward() 113 addReg(Reg.first); in stepForward() 143 if (LiveRegs.count(Reg)) in available() 145 if (MRI.isReserved(Reg)) in available() 162 addReg(Reg); in addBlockLiveIns() 272 MBB.addLiveIn(Reg); in addLiveIns() 294 if (Reg == 0) in recomputeLivenessFlags() [all …]
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H A D | MachineLateInstrsCleanup.cpp | 47 MachineInstr *MI = lookup(Reg); in hasIdentical() 126 KillMI->clearRegisterKills(Reg, TRI); in clearKillsForDef() 136 if (!MBB->isLiveIn(Reg)) in clearKillsForDef() 137 MBB->addLiveIn(Reg); in clearKillsForDef() 193 [&, &Reg = Reg, &DefMI = DefMI](const MachineBasicBlock *Pred) { in processBlock() 196 MBBDefs[Reg] = DefMI; in processBlock() 229 Register Reg = DefI.first; in processBlock() local 230 if (MI.modifiesRegister(Reg, TRI)) { in processBlock() 231 MBBDefs.erase(Reg); in processBlock() 232 MBBKills.erase(Reg); in processBlock() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonVectorPrint.cpp | 74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg() 75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg() 76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg() 77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg() 113 if (isVecReg(Reg)) in getInstrVecReg() 119 if (isVecReg(Reg)) in getInstrVecReg() 125 if (isVecReg(Reg)) in getInstrVecReg() 168 unsigned Reg = 0; in runOnMachineFunction() local 183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction() 186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCRegister.h | 35 unsigned Reg; variable 38 constexpr MCRegister(unsigned Val = 0) : Reg(Val) {} in Reg() function 61 static constexpr bool isStackSlot(unsigned Reg) { in isStackSlot() argument 62 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot() 68 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister() 79 constexpr unsigned id() const { return Reg; } in id() 85 return Reg == Other.Reg; 88 return Reg != Other.Reg; 101 return Reg == unsigned(Other); 104 return Reg != unsigned(Other); [all …]
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H A D | MCRegisterInfo.h | 72 bool contains(MCRegister Reg) const { in contains() argument 73 unsigned RegNo = unsigned(Reg); in contains() 524 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs); 553 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator() 593 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 641 unsigned RU = MCRI->get(Reg).RegUnits; in MCRegUnitIterator() 673 : RUIter(Reg, MCRI) { in MCRegUnitMaskIterator() 739 MCRegister Reg; 750 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { in MCRegAliasIterator() 755 if (!(!IncludeSelf && Reg == *SI)) in MCRegAliasIterator() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUResourceUsageAnalysis.cpp | 214 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage() 215 HighestVGPRReg = Reg; in analyzeResourceUsage() 223 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage() 224 HighestAGPRReg = Reg; in analyzeResourceUsage() 235 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage() 236 HighestSGPRReg = Reg; in analyzeResourceUsage() 269 Register Reg = MO.getReg(); in analyzeResourceUsage() local 270 switch (Reg) { in analyzeResourceUsage() 343 if (AMDGPU::SGPR_32RegClass.contains(Reg) || in analyzeResourceUsage() 495 !TRI.getPhysRegBaseClass(Reg)) && in analyzeResourceUsage() [all …]
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H A D | SIProgramInfo.cpp | 31 Reg |= S_00B848_DX10_CLAMP(DX10Clamp); in getComputePGMRSrc1() 34 Reg |= S_00B848_IEEE_MODE(IEEEMode); in getComputePGMRSrc1() 37 Reg |= S_00B848_RR_WG_MODE(RrWgMode); in getComputePGMRSrc1() 39 return Reg; in getComputePGMRSrc1() 52 Reg |= S_00B848_DX10_CLAMP(DX10Clamp); in getPGMRSrc1() 55 Reg |= S_00B848_IEEE_MODE(IEEEMode); in getPGMRSrc1() 58 Reg |= S_00B848_RR_WG_MODE(RrWgMode); in getPGMRSrc1() 62 Reg |= S_00B028_MEM_ORDERED(MemOrdered); in getPGMRSrc1() 76 return Reg; in getPGMRSrc1() 80 uint64_t Reg = in getComputePGMRSrc2() local [all …]
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H A D | SIOptimizeVGPRLiveRange.cpp | 279 Register Reg = MO.getReg(); in collectCandidateRegisters() local 280 if (Reg.isPhysical() || !TRI->isVectorRegister(*MRI, Reg)) in collectCandidateRegisters() 296 KillsInElse.insert(Reg); in collectCandidateRegisters() 322 for (auto Reg : KillsInElse) { in collectCandidateRegisters() local 323 if (!IsLiveThroughThen(Reg)) in collectCandidateRegisters() 324 CandidateRegs.push_back(Reg); in collectCandidateRegisters() 465 MI->addRegisterKilled(Reg, TRI); in updateLiveRangeInThenRegion() 513 PHI.addReg(Reg).addMBB(Pred); in optimizeLiveRange() 579 PHI.addReg(Reg).addMBB(Pred); in optimizeWaterfallLiveRange() 679 for (auto Reg : CandidateRegs) in runOnMachineFunction() local [all …]
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/freebsd/sys/contrib/dev/acpica/components/hardware/ |
H A D | hwregs.c | 168 ACPI_GENERIC_ADDRESS *Reg, 223 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth() 229 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth() 236 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth() 298 if (!Reg) in AcpiHwValidateRegister() 326 if (Reg->AccessWidth > 4) in AcpiHwValidateRegister() 336 BitWidth = ACPI_ROUND_UP (Reg->BitOffset + Reg->BitWidth, AccessWidth); in AcpiHwValidateRegister() 398 BitWidth = Reg->BitOffset + Reg->BitWidth; in AcpiHwRead() 399 BitOffset = Reg->BitOffset; in AcpiHwRead() 492 BitWidth = Reg->BitOffset + Reg->BitWidth; in AcpiHwWrite() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 90 if (Reg.isPhysical()) in getAccDefMI() 100 if (Reg.isVirtual()) { in getAccDefMI() 106 if (Reg.isVirtual()) { in getAccDefMI() 118 if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg)) in getDefReg() 119 return Reg; in getDefReg() 124 return Reg; in getDefReg() 128 if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg)) in getDefReg() 129 return Reg; in getDefReg() 132 return Reg; in getDefReg() 135 return Reg; in getDefReg() [all …]
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