| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZOperators.td | 455 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>;
|
| H A D | SystemZInstrInfo.td | 1472 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>;
2312 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
|
| H A D | SystemZScheduleZ196.td | 463 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRA(G|K)?$")>;
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 808 enum BinaryOp : uint8_t { ADD, SUB, MUL, AND, OR, XOR, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.td | 297 defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA57.td | 413 def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
|
| H A D | AArch64SchedExynosM5.td | 807 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
|
| H A D | AArch64SchedExynosM4.td | 761 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1200 case ISD::SRA: in LegalizeOp()
2915 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); in ExpandNode()
3741 case ISD::SRA: in ExpandNode()
|
| H A D | LegalizeVectorTypes.cpp | 147 case ISD::SRA: in ScalarizeVectorResult()
1029 case ISD::SRA: in SplitVectorResult()
3016 case ISD::SRA: in WidenVectorResult()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1769 case AShr: return ISD::SRA; in InstructionOpcodeToISD()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3254 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB)) in tryV6T2BitfieldExtractOp()
3291 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA) in tryABSOp()
3568 case ISD::SRA: in Select()
|
| /netbsd/sys/external/bsd/sljit/dist/sljit_src/ |
| H A D | sljitNativeMIPS_common.c | 166 #define SRA (HI(0) | LO(3)) macro
|
| /netbsd/external/gpl3/gdb/dist/cpu/ |
| H A D | or1korbis.cpu | 236 ("SRA" #x2 )
|
| H A D | iq2000.cpu | 263 …(("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7…
|
| /netbsd/external/gpl3/binutils/dist/cpu/ |
| H A D | iq2000.cpu | 263 …(("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7…
|
| H A D | or1korbis.cpu | 236 ("SRA" #x2 )
|
| /netbsd/external/gpl3/binutils.old/dist/cpu/ |
| H A D | iq2000.cpu | 263 …(("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7…
|
| H A D | or1korbis.cpu | 236 ("SRA" #x2 )
|
| /netbsd/external/gpl3/gdb.old/dist/cpu/ |
| H A D | or1korbis.cpu | 236 ("SRA" #x2 )
|
| H A D | iq2000.cpu | 263 …(("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7…
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1484 case ISD::SRA: { in DetectUseSxtw()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2461 case ISD::SRA: in isBinOp()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 670 setOperationAction(ISD::SRA, MVT::v2i16, Legal); in SITargetLowering()
697 setOperationAction(ISD::SRA, MVT::v4i16, Custom); in SITargetLowering()
4534 case ISD::SRA: in LowerOperation()
5148 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL, in lowerXMULO()
5160 ? DAG.getNode(ISD::SRA, SL, VT, Result, in lowerXMULO()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips64InstrInfo.td | 940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
|