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Searched refs:PLLE_BASE_LOCK_OVERRIDE (Results 1 – 25 of 63) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c852 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
875 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c944 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
967 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c944 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
967 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c944 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
967 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c944 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
967 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-tegra/tegra124/
H A Dclock.c947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) macro
970 value &= ~PLLE_BASE_LOCK_OVERRIDE; in tegra_plle_enable()

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