Home
last modified time | relevance | path

Searched refs:mtvsrdd (Results 1 – 25 of 299) sorted by relevance

12345678910>>...12

/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll198 ; CHECK-NEXT: mtvsrdd v2, r8, r7
202 ; CHECK-BE: mtvsrdd v2, r8, r7
214 ; CHECK-NEXT: mtvsrdd v2, r6, r5
218 ; CHECK-BE: mtvsrdd v2, r6, r5
232 ; CHECK: mtvsrdd v3, r6, r5
291 ; CHECK-NEXT: mtvsrdd v2, r4, r3
295 ; CHECK-BE: mtvsrdd v2, r4, r3
307 ; CHECK-NEXT: mtvsrdd v2, r4, r3
311 ; CHECK-BE: mtvsrdd v2, r4, r3
323 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
233 ; CHECK: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
233 ; CHECK: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll198 ; CHECK-NEXT: mtvsrdd v2, r8, r7
202 ; CHECK-BE: mtvsrdd v2, r8, r7
214 ; CHECK-NEXT: mtvsrdd v2, r6, r5
218 ; CHECK-BE: mtvsrdd v2, r6, r5
232 ; CHECK: mtvsrdd v3, r6, r5
291 ; CHECK-NEXT: mtvsrdd v2, r4, r3
295 ; CHECK-BE: mtvsrdd v2, r4, r3
307 ; CHECK-NEXT: mtvsrdd v2, r4, r3
311 ; CHECK-BE: mtvsrdd v2, r4, r3
323 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll214 ; CHECK-NEXT: mtvsrdd v2, r8, r7
219 ; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
232 ; CHECK-NEXT: mtvsrdd v2, r6, r5
237 ; CHECK-BE-NEXT: mtvsrdd v2, r6, r5
251 ; CHECK-NEXT: mtvsrdd v3, r6, r5
262 ; CHECK-BE-NEXT: mtvsrdd v3, r6, r5
323 ; CHECK-NEXT: mtvsrdd v2, r4, r3
328 ; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
341 ; CHECK-NEXT: mtvsrdd v2, r4, r3
346 ; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
233 ; CHECK: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
233 ; CHECK: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
H A Df128-aggregates.ll199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
232 ; CHECK-DAG: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmtvsrdd.ll4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/ppc/
H A Dvsx3.s19 mtvsrdd 12,6,5
20 mtvsrdd 38,0,21
/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/ppc/
H A Dvsx3.s19 mtvsrdd 12,6,5
20 mtvsrdd 38,0,21

12345678910>>...12