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Searched refs:_REG (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1159 _REG(ENCI_VFIFO2VD_PIXEL_START)) in meson_venc_hdmi_mode_set()
1238 + _REG(ENCI_DVI_VSO_ELINE_EVN)); in meson_venc_hdmi_mode_set()
1241 + _REG(ENCI_DVI_VSO_END_EVN)); in meson_venc_hdmi_mode_set()
1247 + _REG(ENCI_DVI_VSO_ELINE_ODD)); in meson_venc_hdmi_mode_set()
1250 + _REG(ENCI_DVI_VSO_END_ODD)); in meson_venc_hdmi_mode_set()
1287 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); in meson_venc_hdmi_mode_set()
1295 + _REG(ENCI_DVI_VSO_ELINE_ODD)); in meson_venc_hdmi_mode_set()
1298 + _REG(ENCI_DVI_VSO_END_ODD)); in meson_venc_hdmi_mode_set()
1303 + _REG(ENCI_DVI_VSO_ELINE_EVN)); in meson_venc_hdmi_mode_set()
1306 + _REG(ENCI_DVI_VSO_END_EVN)); in meson_venc_hdmi_mode_set()
[all …]
H A Dmeson_viu.c131 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
134 _REG(VIU_OSD1_MATRIX_COEF31_32)); in meson_viu_set_osd_matrix()
142 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
166 _REG(VIU_OSD1_EOTF_CTL + i + 1)); in meson_viu_set_osd_matrix()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
[all …]
H A Dmeson_crtc.c478 _REG(VD1_IF0_GEN_REG)); in meson_crtc_irq()
481 _REG(VD2_IF0_GEN_REG)); in meson_crtc_irq()
493 _REG(VIU_VD1_FMT_W)); in meson_crtc_irq()
496 _REG(VIU_VD2_FMT_W)); in meson_crtc_irq()
499 _REG(VD1_IF0_CANVAS0)); in meson_crtc_irq()
502 _REG(VD1_IF0_CANVAS1)); in meson_crtc_irq()
505 _REG(VD2_IF0_CANVAS0)); in meson_crtc_irq()
508 _REG(VD2_IF0_CANVAS1)); in meson_crtc_irq()
511 _REG(VD1_IF0_LUMA_X0)); in meson_crtc_irq()
514 _REG(VD1_IF0_LUMA_X1)); in meson_crtc_irq()
[all …]
H A Dmeson_vpp.c63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
114 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpp_init()
121 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
125 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
131 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
[all …]
H A Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
H A Dmeson_osd_afbcd.c85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
302 priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); in meson_g12a_afbcd_init()
[all …]
H A Dmeson_encoder_dsi.c71 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_encoder_dsi_atomic_enable()
74 priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); in meson_encoder_dsi_atomic_enable()
75 writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN)); in meson_encoder_dsi_atomic_enable()
77 writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_encoder_dsi_atomic_enable()
79 writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_encoder_dsi_atomic_enable()
89 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_encoder_dsi_atomic_disable()
91 writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_encoder_dsi_atomic_disable()
H A Dmeson_encoder_hdmi.c235 priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
239 priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
242 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_encoder_hdmi_atomic_enable()
247 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_encoder_hdmi_atomic_enable()
249 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_encoder_hdmi_atomic_enable()
259 priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_encoder_hdmi_atomic_disable()
261 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_encoder_hdmi_atomic_disable()
262 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_encoder_hdmi_atomic_disable()
H A Dmeson_dw_hdmi.c380 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
426 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
428 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
432 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
434 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
438 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
440 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
444 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
449 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
452 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
H A Dmeson_drv.c75 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); in meson_irq()
146 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
150 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
155 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
159 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
H A Dmeson_overlay.c737 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
738 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
739 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
740 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
743 priv->io_base + _REG(VPP_MISC)); in meson_overlay_atomic_disable()
H A Dmeson_plane.c176 _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
413 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_plane_atomic_disable()
416 priv->io_base + _REG(VPP_MISC)); in meson_plane_atomic_disable()
H A Dmeson_encoder_cvbs.c178 priv->io_base + _REG(VENC_VDAC_DACSEL0)); in meson_encoder_cvbs_atomic_enable()
H A Dmeson_registers.h12 #define _REG(reg) ((reg) << 2) macro
/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h149 LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
150 LPAIF_RDMA##reg##_REG(v, chan))
155 LPAIF_WRDMA##reg##_REG(v, chan))
242 (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
243 LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
246 (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
247 LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_output_7a2000.c84 .name = __stringify_1(LSDC_HDMI##i##_##reg##_REG), \
85 .offset = LSDC_HDMI##i##_##reg##_REG, \
H A Dlsdc_crtc.c477 .name = __stringify_1(LSDC_##reg##_REG), \
478 .offset = LSDC_##reg##_REG, \
/linux/drivers/iommu/intel/
H A Ddebugfs.c39 { DMAR_##_reg_##_REG, __stringify(_reg_) }