Searched refs:VCGT (Results 1 – 8 of 8) sorted by relevance
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/ |
H A D | vfcmp.ll | 17 ; olt is implemented with VCGT 39 ; uge is implemented with VCGT/VMVN 51 ; ule is implemented with VCGT/VMVN 87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN 101 ; one is implemented with VCGT/VCGT/VORR 114 ; uno is implemented with VCGT/VCGE/VORR/VMVN 128 ; ord is implemented with VCGT/VCGE/VORR
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H A D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 106 VCGT, // Vector compare greater than. enumerator
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H A D | ARMISelLowering.cpp | 1072 case ARMISD::VCGT: return "ARMISD::VCGT"; in getTargetNodeName() 4510 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC() 4516 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC() 4525 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC() 4526 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC() 4534 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC() 4545 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC() 4587 else if (Opc == ARMISD::VCGT) in LowerVSETCC() 4601 case ARMISD::VCGT: in LowerVSETCC()
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H A D | ARMScheduleSwift.td | 1585 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
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H A D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
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H A D | ARMInstrNEON.td | 501 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; 4514 // VCGT : Vector Compare Greater Than 7507 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed. 7539 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
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/minix/external/bsd/llvm/dist/clang/include/clang/Basic/ |
H A D | arm_neon.td | 539 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
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