/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_hubp.c | 1058 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common() 1071 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common() 1074 REG_GET(DST_DIMENSIONS, in hubp2_read_state_common() 1112 REG_GET(NOM_PARAMETERS_4, in hubp2_read_state_common() 1115 REG_GET(NOM_PARAMETERS_5, in hubp2_read_state_common() 1147 REG_GET(NOM_PARAMETERS_6, in hubp2_read_state_common() 1150 REG_GET(NOM_PARAMETERS_7, in hubp2_read_state_common() 1212 REG_GET(HUBP_CLK_CNTL, in hubp2_read_state_common() 1268 REG_GET(HUBPRET_CONTROL, in hubp2_validate_dml_output() 1364 REG_GET(BLANK_OFFSET_1, in hubp2_validate_dml_output() [all …]
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H A D | amdgpu_dcn20_stream_encoder.c | 355 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state() 357 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state() 358 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state() 360 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state() 361 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state() 363 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state() 364 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state() 435 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
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H A D | amdgpu_dcn20_link_encoder.c | 193 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); in enc2_fec_is_active() 205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state() 206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state() 207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state() 208 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); in link_enc2_read_state()
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H A D | amdgpu_dcn20_dwb.c | 182 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update() 209 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled() 210 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
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H A D | amdgpu_dcn20_dpp.c | 61 REG_GET(DPP_CONTROL, in dpp20_read_state() 63 REG_GET(CM_DGAM_CONTROL, in dpp20_read_state() 68 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp20_read_state()
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H A D | amdgpu_dcn20_dsc.c | 162 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state() 163 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state() 164 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); in dsc2_read_state() 238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable() 263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
H A D | amdgpu_dcn21_hubp.c | 94 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline() 369 REG_GET(HUBPRET_CONTROL, in hubp21_validate_dml_output() 462 REG_GET(BLANK_OFFSET_1, in hubp21_validate_dml_output() 464 REG_GET(DST_DIMENSIONS, in hubp21_validate_dml_output() 498 REG_GET(NOM_PARAMETERS_0, in hubp21_validate_dml_output() 501 REG_GET(NOM_PARAMETERS_1, in hubp21_validate_dml_output() 503 REG_GET(NOM_PARAMETERS_4, in hubp21_validate_dml_output() 505 REG_GET(NOM_PARAMETERS_5, in hubp21_validate_dml_output() 516 REG_GET(NOM_PARAMETERS_2, in hubp21_validate_dml_output() 521 REG_GET(NOM_PARAMETERS_6, in hubp21_validate_dml_output() [all …]
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H A D | amdgpu_dcn21_hubbub.c | 569 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state() 572 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state() 575 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state() 583 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state() 586 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state() 589 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state() 597 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state() 600 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, in hubbub21_wm_read_state() 603 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, in hubbub21_wm_read_state() 611 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, in hubbub21_wm_read_state() [all …]
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H A D | amdgpu_dcn21_link_encoder.c | 217 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value); in dcn21_link_encoder_get_max_link_cap() 228 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value); in dcn21_link_encoder_is_in_alt_mode() 240 REG_GET(RDPCSTX_PHY_CNTL6, in dcn21_link_encoder_acquire_phy() 252 REG_GET(RDPCSTX_PHY_CNTL6, in dcn21_link_encoder_acquire_phy()
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H A D | amdgpu_dcn21_hwseq.c | 60 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_update_page_table_config() 62 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_update_page_table_config()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
H A D | amdgpu_dcn10_hubp.c | 100 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status() 866 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common() 879 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common() 882 REG_GET(DST_DIMENSIONS, in hubp1_read_state_common() 913 REG_GET(NOM_PARAMETERS_0, in hubp1_read_state_common() 917 REG_GET(NOM_PARAMETERS_1, in hubp1_read_state_common() 920 REG_GET(NOM_PARAMETERS_4, in hubp1_read_state_common() 923 REG_GET(NOM_PARAMETERS_5, in hubp1_read_state_common() 955 REG_GET(NOM_PARAMETERS_6, in hubp1_read_state_common() 958 REG_GET(NOM_PARAMETERS_7, in hubp1_read_state_common() [all …]
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H A D | amdgpu_dcn10_mpc.c | 145 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle() 146 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle() 147 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle() 159 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect() 384 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst() 410 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw() 414 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw() 415 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw() 416 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw() 450 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state() [all …]
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H A D | amdgpu_dcn10_optc.c | 688 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger() 1238 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye() 1275 REG_GET(OTG_CONTROL, in optc1_read_otg_state() 1282 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state() 1285 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state() 1288 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state() 1291 REG_GET(OTG_V_TOTAL_MIN, in optc1_read_otg_state() 1312 REG_GET(OTG_H_SYNC_A_CNTL, in optc1_read_otg_state() 1315 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state() 1334 REG_GET(OTG_CONTROL, in optc1_get_otg_active_size() [all …]
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H A D | amdgpu_dcn10_dpp.c | 104 REG_GET(DPP_CONTROL, in dpp_read_state() 106 REG_GET(CM_IGAM_CONTROL, in dpp_read_state() 108 REG_GET(CM_IGAM_CONTROL, in dpp_read_state() 110 REG_GET(CM_DGAM_CONTROL, in dpp_read_state() 112 REG_GET(CM_RGAM_CONTROL, in dpp_read_state() 114 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
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H A D | amdgpu_dcn10_link_encoder.c | 461 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); in dcn10_get_dig_frontend() 546 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dcn10_is_dig_enabled() 1307 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table() 1310 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table() 1330 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dcn10_link_encoder_connect_dig_be_to_fe() 1412 REG_GET(DIG_BE_CNTL, DIG_MODE, &value); in dcn10_get_dig_mode()
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H A D | amdgpu_dcn10_dpp_cm.c | 209 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix() 466 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc() 649 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse() 741 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse() 811 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
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H A D | amdgpu_dcn10_hw_sequencer.c | 1821 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in mmhub_read_vm_system_aperture_settings() 1823 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_read_vm_system_aperture_settings() 1826 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_read_vm_system_aperture_settings() 1829 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_read_vm_system_aperture_settings() 1850 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_read_vm_context0_settings() 1852 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_read_vm_context0_settings() 1855 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_read_vm_context0_settings() 1857 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_read_vm_context0_settings() 1860 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_read_vm_context0_settings() 1862 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_read_vm_context0_settings() [all …]
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
H A D | amdgpu_dce_abm.c | 100 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in calculate_16_bit_backlight_from_pwm() 101 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in calculate_16_bit_backlight_from_pwm() 104 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in calculate_16_bit_backlight_from_pwm() 105 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in calculate_16_bit_backlight_from_pwm() 355 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_immediate_disable() 369 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_abm_init_backlight() 397 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_init_backlight()
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H A D | amdgpu_dce_i2c_hw.c | 82 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status() 129 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply() 141 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available() 145 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available() 156 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy() 275 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); in set_speed() 353 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
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H A D | amdgpu_dce_aux.c | 287 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply() 303 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply() 321 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
H A D | amdgpu_hw_gpio.c | 50 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers() 51 REG_GET(A_reg, A, &gpio->store.a); in store_registers() 52 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers() 91 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
H A D | amdgpu_dmub_dcn20.c | 68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset() 71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset() 221 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
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/netbsd/external/gpl3/gdb/dist/sim/msp430/ |
H A D | msp430-sim.c | 253 #define REG_GET(N) trace_reg_get (sd, N) macro 292 rv = REG_GET (op->reg); in get_op() 299 int reg = REG_GET (op->reg); in get_op() 459 REG_PUT (op->reg, REG_GET (op->reg) + incval); in get_op() 500 int reg = REG_GET (op->reg); in put_op() 729 int new_val = REG_GET (op->reg) + incval; in put_op() 1376 new_sp = REG_GET (MSR_SP) - op_bytes; in msp430_step_once() 1397 new_sp = REG_GET (MSR_SP) + op_bytes; in msp430_step_once() 1411 REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes); in msp430_step_once()
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/netbsd/external/gpl3/gdb.old/dist/sim/msp430/ |
H A D | msp430-sim.c | 253 #define REG_GET(N) trace_reg_get (sd, N) macro 292 rv = REG_GET (op->reg); in get_op() 299 int reg = REG_GET (op->reg); in get_op() 459 REG_PUT (op->reg, REG_GET (op->reg) + incval); in get_op() 500 int reg = REG_GET (op->reg); in put_op() 729 int new_val = REG_GET (op->reg) + incval; in put_op() 1376 new_sp = REG_GET (MSR_SP) - op_bytes; in msp430_step_once() 1397 new_sp = REG_GET (MSR_SP) + op_bytes; in msp430_step_once() 1411 REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes); in msp430_step_once()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
H A D | amdgpu_bios_parser_helper.c | 66 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()
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