1;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2;* File Name          : startup_stm32f030xc.s
3;* Author             : MCD Application Team
4;* Version            : V1.5.0
5;* Date               : 05-December-2014
6;* Description        : STM32F030CC/STM32F030RC devices vector table for MDK-ARM toolchain.
7;*                      This module performs:
8;*                      - Set the initial SP
9;*                      - Set the initial PC == Reset_Handler
10;*                      - Set the vector table entries with the exceptions ISR address
11;*                      - Configure the system clock
12;*                      - Branches to __main in the C library (which eventually
13;*                        calls main()).
14;*                      After Reset the CortexM0 processor is in Thread mode,
15;*                      priority is Privileged, and the Stack is set to Main.
16;* <<< Use Configuration Wizard in Context Menu >>>
17;*******************************************************************************
18;  @attention
19;
20;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
21;  You may not use this file except in compliance with the License.
22;  You may obtain a copy of the License at:
23;
24;         http://www.st.com/software_license_agreement_liberty_v2
25;
26;  Unless required by applicable law or agreed to in writing, software
27;  distributed under the License is distributed on an "AS IS" BASIS,
28;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
29;  See the License for the specific language governing permissions and
30;  limitations under the License.
31;
32;*******************************************************************************
33;
34; Amount of memory (in bytes) allocated for Stack
35; Tailor this value to your application needs
36; <h> Stack Configuration
37;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
38; </h>
39
40Stack_Size      EQU     0x00000400
41
42                AREA    STACK, NOINIT, READWRITE, ALIGN=3
43Stack_Mem       SPACE   Stack_Size
44__initial_sp
45
46
47; <h> Heap Configuration
48;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
49; </h>
50
51Heap_Size       EQU     0x00000200
52
53                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
54__heap_base
55Heap_Mem        SPACE   Heap_Size
56__heap_limit
57
58                PRESERVE8
59                THUMB
60
61
62; Vector Table Mapped to Address 0 at Reset
63                AREA    RESET, DATA, READONLY
64                EXPORT  __Vectors
65                EXPORT  __Vectors_End
66                EXPORT  __Vectors_Size
67
68__Vectors       DCD     __initial_sp                   ; Top of Stack
69                DCD     Reset_Handler                  ; Reset Handler
70                DCD     NMI_Handler                    ; NMI Handler
71                DCD     HardFault_Handler              ; Hard Fault Handler
72                DCD     0                              ; Reserved
73                DCD     0                              ; Reserved
74                DCD     0                              ; Reserved
75                DCD     0                              ; Reserved
76                DCD     0                              ; Reserved
77                DCD     0                              ; Reserved
78                DCD     0                              ; Reserved
79                DCD     SVC_Handler                    ; SVCall Handler
80                DCD     0                              ; Reserved
81                DCD     0                              ; Reserved
82                DCD     PendSV_Handler                 ; PendSV Handler
83                DCD     SysTick_Handler                ; SysTick Handler
84
85                ; External Interrupts
86                DCD     WWDG_IRQHandler                ; Window Watchdog
87                DCD     0                              ; Reserved
88                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
89                DCD     FLASH_IRQHandler               ; FLASH
90                DCD     RCC_IRQHandler                 ; RCC
91                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
92                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
93                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
94                DCD     0                              ; Reserved
95                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
96                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
97                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
98                DCD     ADC1_IRQHandler                ; ADC1
99                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
100                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
101                DCD     0                              ; Reserved
102                DCD     TIM3_IRQHandler                ; TIM3
103                DCD     TIM6_IRQHandler                ; TIM6
104                DCD     TIM7_IRQHandler                ; TIM7
105                DCD     TIM14_IRQHandler               ; TIM14
106                DCD     TIM15_IRQHandler               ; TIM15
107                DCD     TIM16_IRQHandler               ; TIM16
108                DCD     TIM17_IRQHandler               ; TIM17
109                DCD     I2C1_IRQHandler                ; I2C1
110                DCD     I2C2_IRQHandler                ; I2C2
111                DCD     SPI1_IRQHandler                ; SPI1
112                DCD     SPI2_IRQHandler                ; SPI2
113                DCD     USART1_IRQHandler              ; USART1
114                DCD     USART2_IRQHandler              ; USART2
115                DCD     USART3_6_IRQHandler            ; USART3, USART4, USART5, USART6
116
117__Vectors_End
118
119__Vectors_Size  EQU  __Vectors_End - __Vectors
120
121                AREA    |.text|, CODE, READONLY
122
123; Reset handler routine
124Reset_Handler    PROC
125                 EXPORT  Reset_Handler                 [WEAK]
126        IMPORT  __main
127        IMPORT  SystemInit
128
129
130
131        LDR     R0, =__initial_sp          ; set stack pointer
132        MSR     MSP, R0
133
134;;Check if boot space corresponds to test memory
135
136        LDR R0,=0x00000004
137        LDR R1, [R0]
138        LSRS R1, R1, #24
139        LDR R2,=0x1F
140        CMP R1, R2
141
142        BNE ApplicationStart
143
144;; SYSCFG clock enable
145
146        LDR R0,=0x40021018
147        LDR R1,=0x00000001
148        STR R1, [R0]
149
150;; Set CFGR1 register with flash memory remap at address 0
151
152        LDR R0,=0x40010000
153        LDR R1,=0x00000000
154        STR R1, [R0]
155ApplicationStart
156                 LDR     R0, =SystemInit
157                 BLX     R0
158                 LDR     R0, =__main
159                 BX      R0
160                 ENDP
161
162; Dummy Exception Handlers (infinite loops which can be modified)
163
164NMI_Handler     PROC
165                EXPORT  NMI_Handler                    [WEAK]
166                B       .
167                ENDP
168HardFault_Handler\
169                PROC
170                EXPORT  HardFault_Handler              [WEAK]
171                B       .
172                ENDP
173SVC_Handler     PROC
174                EXPORT  SVC_Handler                    [WEAK]
175                B       .
176                ENDP
177PendSV_Handler  PROC
178                EXPORT  PendSV_Handler                 [WEAK]
179                B       .
180                ENDP
181SysTick_Handler PROC
182                EXPORT  SysTick_Handler                [WEAK]
183                B       .
184                ENDP
185
186Default_Handler PROC
187
188                EXPORT  WWDG_IRQHandler                [WEAK]
189                EXPORT  RTC_IRQHandler                 [WEAK]
190                EXPORT  FLASH_IRQHandler               [WEAK]
191                EXPORT  RCC_IRQHandler                 [WEAK]
192                EXPORT  EXTI0_1_IRQHandler             [WEAK]
193                EXPORT  EXTI2_3_IRQHandler             [WEAK]
194                EXPORT  EXTI4_15_IRQHandler            [WEAK]
195                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
196                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
197                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
198                EXPORT  ADC1_IRQHandler                [WEAK]
199                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
200                EXPORT  TIM1_CC_IRQHandler             [WEAK]
201                EXPORT  TIM3_IRQHandler                [WEAK]
202                EXPORT  TIM6_IRQHandler                [WEAK]
203                EXPORT  TIM7_IRQHandler                [WEAK]
204                EXPORT  TIM14_IRQHandler               [WEAK]
205                EXPORT  TIM15_IRQHandler               [WEAK]
206                EXPORT  TIM16_IRQHandler               [WEAK]
207                EXPORT  TIM17_IRQHandler               [WEAK]
208                EXPORT  I2C1_IRQHandler                [WEAK]
209                EXPORT  I2C2_IRQHandler                [WEAK]
210                EXPORT  SPI1_IRQHandler                [WEAK]
211                EXPORT  SPI2_IRQHandler                [WEAK]
212                EXPORT  USART1_IRQHandler              [WEAK]
213                EXPORT  USART2_IRQHandler              [WEAK]
214                EXPORT  USART3_6_IRQHandler            [WEAK]
215
216
217WWDG_IRQHandler
218RTC_IRQHandler
219FLASH_IRQHandler
220RCC_IRQHandler
221EXTI0_1_IRQHandler
222EXTI2_3_IRQHandler
223EXTI4_15_IRQHandler
224DMA1_Channel1_IRQHandler
225DMA1_Channel2_3_IRQHandler
226DMA1_Channel4_5_IRQHandler
227ADC1_IRQHandler
228TIM1_BRK_UP_TRG_COM_IRQHandler
229TIM1_CC_IRQHandler
230TIM3_IRQHandler
231TIM6_IRQHandler
232TIM7_IRQHandler
233TIM14_IRQHandler
234TIM15_IRQHandler
235TIM16_IRQHandler
236TIM17_IRQHandler
237I2C1_IRQHandler
238I2C2_IRQHandler
239SPI1_IRQHandler
240SPI2_IRQHandler
241USART1_IRQHandler
242USART2_IRQHandler
243USART3_6_IRQHandler
244
245                B       .
246
247                ENDP
248
249                ALIGN
250
251;*******************************************************************************
252; User Stack and Heap initialization
253;*******************************************************************************
254                 IF      :DEF:__MICROLIB
255
256                 EXPORT  __initial_sp
257                 EXPORT  __heap_base
258                 EXPORT  __heap_limit
259
260                 ELSE
261
262                 IMPORT  __use_two_region_memory
263                 EXPORT  __user_initial_stackheap
264
265__user_initial_stackheap
266
267                 LDR     R0, =  Heap_Mem
268                 LDR     R1, =(Stack_Mem + Stack_Size)
269                 LDR     R2, = (Heap_Mem +  Heap_Size)
270                 LDR     R3, = Stack_Mem
271                 BX      LR
272
273                 ALIGN
274
275                 ENDIF
276
277                 END
278
279;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
280