1;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** 2;* File Name : startup_stm32f091.s 3;* Author : MCD Application Team 4;* Version : V1.5.0 5;* Date : 05-December-2014 6;* Description : STM32F091 Devices vector table for 7;* for MDK-ARM toolchain. 8;* This module performs: 9;* - Set the initial SP 10;* - Set the initial PC == Reset_Handler 11;* - Set the vector table entries with the exceptions ISR address 12;* - Configure the system clock 13;* - Branches to __main in the C library (which eventually 14;* calls main()). 15;* After Reset the CortexM0 processor is in Thread mode, 16;* priority is Privileged, and the Stack is set to Main. 17;* <<< Use Configuration Wizard in Context Menu >>> 18;******************************************************************************* 19; @attention 20; 21; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 22; You may not use this file except in compliance with the License. 23; You may obtain a copy of the License at: 24; 25; http://www.st.com/software_license_agreement_liberty_v2 26; 27; Unless required by applicable law or agreed to in writing, software 28; distributed under the License is distributed on an "AS IS" BASIS, 29; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30; See the License for the specific language governing permissions and 31; limitations under the License. 32; 33;******************************************************************************* 34; 35; Amount of memory (in bytes) allocated for Stack 36; Tailor this value to your application needs 37; <h> Stack Configuration 38; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 39; </h> 40 41Stack_Size EQU 0x00000400 42 43 AREA STACK, NOINIT, READWRITE, ALIGN=3 44Stack_Mem SPACE Stack_Size 45__initial_sp 46 47 48; <h> Heap Configuration 49; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 50; </h> 51 52Heap_Size EQU 0x00000200 53 54 AREA HEAP, NOINIT, READWRITE, ALIGN=3 55__heap_base 56Heap_Mem SPACE Heap_Size 57__heap_limit 58 59 PRESERVE8 60 THUMB 61 62 63; Vector Table Mapped to Address 0 at Reset 64 AREA RESET, DATA, READONLY 65 EXPORT __Vectors 66 EXPORT __Vectors_End 67 EXPORT __Vectors_Size 68 69__Vectors DCD __initial_sp ; Top of Stack 70 DCD Reset_Handler ; Reset Handler 71 DCD NMI_Handler ; NMI Handler 72 DCD HardFault_Handler ; Hard Fault Handler 73 DCD 0 ; Reserved 74 DCD 0 ; Reserved 75 DCD 0 ; Reserved 76 DCD 0 ; Reserved 77 DCD 0 ; Reserved 78 DCD 0 ; Reserved 79 DCD 0 ; Reserved 80 DCD SVC_Handler ; SVCall Handler 81 DCD 0 ; Reserved 82 DCD 0 ; Reserved 83 DCD PendSV_Handler ; PendSV Handler 84 DCD SysTick_Handler ; SysTick Handler 85 86 ; External Interrupts 87 DCD WWDG_IRQHandler ; Window Watchdog 88 DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect 89 DCD RTC_IRQHandler ; RTC through EXTI Line 90 DCD FLASH_IRQHandler ; FLASH 91 DCD RCC_CRS_IRQHandler ; RCC and CRS 92 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 93 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 94 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 95 DCD TSC_IRQHandler ; TS 96 DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1 97 DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 98 DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 99 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 100 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 101 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 102 DCD TIM2_IRQHandler ; TIM2 103 DCD TIM3_IRQHandler ; TIM3 104 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC 105 DCD TIM7_IRQHandler ; TIM7 106 DCD TIM14_IRQHandler ; TIM14 107 DCD TIM15_IRQHandler ; TIM15 108 DCD TIM16_IRQHandler ; TIM16 109 DCD TIM17_IRQHandler ; TIM17 110 DCD I2C1_IRQHandler ; I2C1 111 DCD I2C2_IRQHandler ; I2C2 112 DCD SPI1_IRQHandler ; SPI1 113 DCD SPI2_IRQHandler ; SPI2 114 DCD USART1_IRQHandler ; USART1 115 DCD USART2_IRQHandler ; USART2 116 DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8 117 DCD CEC_CAN_IRQHandler ; CEC and CAN 118 119__Vectors_End 120 121__Vectors_Size EQU __Vectors_End - __Vectors 122 123 AREA |.text|, CODE, READONLY 124 125; Reset handler routine 126Reset_Handler PROC 127 EXPORT Reset_Handler [WEAK] 128 IMPORT __main 129 IMPORT SystemInit 130 131 132 133 LDR R0, =__initial_sp ; set stack pointer 134 MSR MSP, R0 135 136;;Check if boot space corresponds to test memory 137 138 LDR R0,=0x00000004 139 LDR R1, [R0] 140 LSRS R1, R1, #24 141 LDR R2,=0x1F 142 CMP R1, R2 143 144 BNE ApplicationStart 145 146;; SYSCFG clock enable 147 148 LDR R0,=0x40021018 149 LDR R1,=0x00000001 150 STR R1, [R0] 151 152;; Set CFGR1 register with flash memory remap at address 0 153 154 LDR R0,=0x40010000 155 LDR R1,=0x00000000 156 STR R1, [R0] 157ApplicationStart 158 LDR R0, =SystemInit 159 BLX R0 160 LDR R0, =__main 161 BX R0 162 ENDP 163 164; Dummy Exception Handlers (infinite loops which can be modified) 165 166NMI_Handler PROC 167 EXPORT NMI_Handler [WEAK] 168 B . 169 ENDP 170HardFault_Handler\ 171 PROC 172 EXPORT HardFault_Handler [WEAK] 173 B . 174 ENDP 175SVC_Handler PROC 176 EXPORT SVC_Handler [WEAK] 177 B . 178 ENDP 179PendSV_Handler PROC 180 EXPORT PendSV_Handler [WEAK] 181 B . 182 ENDP 183SysTick_Handler PROC 184 EXPORT SysTick_Handler [WEAK] 185 B . 186 ENDP 187 188Default_Handler PROC 189 190 EXPORT WWDG_IRQHandler [WEAK] 191 EXPORT PVD_VDDIO2_IRQHandler [WEAK] 192 EXPORT RTC_IRQHandler [WEAK] 193 EXPORT FLASH_IRQHandler [WEAK] 194 EXPORT RCC_CRS_IRQHandler [WEAK] 195 EXPORT EXTI0_1_IRQHandler [WEAK] 196 EXPORT EXTI2_3_IRQHandler [WEAK] 197 EXPORT EXTI4_15_IRQHandler [WEAK] 198 EXPORT TSC_IRQHandler [WEAK] 199 EXPORT DMA1_Ch1_IRQHandler [WEAK] 200 EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK] 201 EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK] 202 EXPORT ADC1_COMP_IRQHandler [WEAK] 203 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 204 EXPORT TIM1_CC_IRQHandler [WEAK] 205 EXPORT TIM2_IRQHandler [WEAK] 206 EXPORT TIM3_IRQHandler [WEAK] 207 EXPORT TIM6_DAC_IRQHandler [WEAK] 208 EXPORT TIM7_IRQHandler [WEAK] 209 EXPORT TIM14_IRQHandler [WEAK] 210 EXPORT TIM15_IRQHandler [WEAK] 211 EXPORT TIM16_IRQHandler [WEAK] 212 EXPORT TIM17_IRQHandler [WEAK] 213 EXPORT I2C1_IRQHandler [WEAK] 214 EXPORT I2C2_IRQHandler [WEAK] 215 EXPORT SPI1_IRQHandler [WEAK] 216 EXPORT SPI2_IRQHandler [WEAK] 217 EXPORT USART1_IRQHandler [WEAK] 218 EXPORT USART2_IRQHandler [WEAK] 219 EXPORT USART3_8_IRQHandler [WEAK] 220 EXPORT CEC_CAN_IRQHandler [WEAK] 221 222 223WWDG_IRQHandler 224PVD_VDDIO2_IRQHandler 225RTC_IRQHandler 226FLASH_IRQHandler 227RCC_CRS_IRQHandler 228EXTI0_1_IRQHandler 229EXTI2_3_IRQHandler 230EXTI4_15_IRQHandler 231TSC_IRQHandler 232DMA1_Ch1_IRQHandler 233DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 234DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler 235ADC1_COMP_IRQHandler 236TIM1_BRK_UP_TRG_COM_IRQHandler 237TIM1_CC_IRQHandler 238TIM2_IRQHandler 239TIM3_IRQHandler 240TIM6_DAC_IRQHandler 241TIM7_IRQHandler 242TIM14_IRQHandler 243TIM15_IRQHandler 244TIM16_IRQHandler 245TIM17_IRQHandler 246I2C1_IRQHandler 247I2C2_IRQHandler 248SPI1_IRQHandler 249SPI2_IRQHandler 250USART1_IRQHandler 251USART2_IRQHandler 252USART3_8_IRQHandler 253CEC_CAN_IRQHandler 254 255 B . 256 257 ENDP 258 259 ALIGN 260 261;******************************************************************************* 262; User Stack and Heap initialization 263;******************************************************************************* 264 IF :DEF:__MICROLIB 265 266 EXPORT __initial_sp 267 EXPORT __heap_base 268 EXPORT __heap_limit 269 270 ELSE 271 272 IMPORT __use_two_region_memory 273 EXPORT __user_initial_stackheap 274 275__user_initial_stackheap 276 277 LDR R0, = Heap_Mem 278 LDR R1, =(Stack_Mem + Stack_Size) 279 LDR R2, = (Heap_Mem + Heap_Size) 280 LDR R3, = Stack_Mem 281 BX LR 282 283 ALIGN 284 285 ENDIF 286 287 END 288 289;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 290