1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_DMA_H 22 #define STM32H7xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Configuration Structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the request selected for the specified stream. 52 This parameter can be a value of @ref DMA_Request_selection */ 53 54 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 55 from memory to memory or from peripheral to memory. 56 This parameter can be a value of @ref DMA_Data_transfer_direction */ 57 58 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 60 61 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 62 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 63 64 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 65 This parameter can be a value of @ref DMA_Peripheral_data_size */ 66 67 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 68 This parameter can be a value of @ref DMA_Memory_data_size */ 69 70 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 71 This parameter can be a value of @ref DMA_mode 72 @note The circular buffer mode cannot be used if the memory-to-memory 73 data transfer is configured on the selected Stream */ 74 75 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 76 This parameter can be a value of @ref DMA_Priority_level */ 77 78 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 79 This parameter can be a value of @ref DMA_FIFO_direct_mode 80 @note The Direct mode (FIFO mode disabled) cannot be used if the 81 memory-to-memory data transfer is configured on the selected stream */ 82 83 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 84 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 85 86 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 87 It specifies the amount of data to be transferred in a single non interruptible 88 transaction. 89 This parameter can be a value of @ref DMA_Memory_burst 90 @note The burst mode is possible only if the address Increment mode is enabled. */ 91 92 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 93 It specifies the amount of data to be transferred in a single non interruptible 94 transaction. 95 This parameter can be a value of @ref DMA_Peripheral_burst 96 @note The burst mode is possible only if the address Increment mode is enabled. */ 97 }DMA_InitTypeDef; 98 99 /** 100 * @brief HAL DMA State structures definition 101 */ 102 typedef enum 103 { 104 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 105 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 106 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 107 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 108 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 109 }HAL_DMA_StateTypeDef; 110 111 /** 112 * @brief HAL DMA Transfer complete level structure definition 113 */ 114 typedef enum 115 { 116 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 117 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 118 }HAL_DMA_LevelCompleteTypeDef; 119 120 /** 121 * @brief HAL DMA Callbacks IDs structure definition 122 */ 123 typedef enum 124 { 125 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 126 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 127 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 128 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 129 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 130 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 131 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 132 }HAL_DMA_CallbackIDTypeDef; 133 134 /** 135 * @brief DMA handle Structure definition 136 */ 137 typedef struct __DMA_HandleTypeDef 138 { 139 void *Instance; /*!< Register base address */ 140 141 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 142 143 HAL_LockTypeDef Lock; /*!< DMA locking object */ 144 145 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 146 147 void *Parent; /*!< Parent object state */ 148 149 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 150 151 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 152 153 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 154 155 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 156 157 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 158 159 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 160 161 __IO uint32_t ErrorCode; /*!< DMA Error code */ 162 163 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 164 165 uint32_t StreamIndex; /*!< DMA Stream Index */ 166 167 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ 168 169 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 170 171 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 172 173 174 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 175 176 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ 177 178 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 179 180 }DMA_HandleTypeDef; 181 182 /** 183 * @} 184 */ 185 186 187 /* Exported constants --------------------------------------------------------*/ 188 189 /** @defgroup DMA_Exported_Constants DMA Exported Constants 190 * @brief DMA Exported constants 191 * @{ 192 */ 193 194 /** @defgroup DMA_Error_Code DMA Error Code 195 * @brief DMA Error Code 196 * @{ 197 */ 198 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 199 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 200 #define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ 201 #define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ 202 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 203 #define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ 204 #define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ 205 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 206 #define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ 207 #define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ 208 #define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ 209 210 /** 211 * @} 212 */ 213 214 /** @defgroup DMA_Request_selection DMA Request selection 215 * @brief DMA Request selection 216 * @{ 217 */ 218 /* DMAMUX1 requests */ 219 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 220 221 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 222 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 223 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 224 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 225 #define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ 226 #define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ 227 #define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ 228 #define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ 229 230 #define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ 231 #define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ 232 233 #define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ 234 #define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ 235 #define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ 236 #define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ 237 #define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ 238 #define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ 239 #define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ 240 241 #define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ 242 #define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ 243 #define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ 244 #define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ 245 #define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ 246 247 #define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ 248 #define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ 249 #define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ 250 #define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ 251 #define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ 252 #define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ 253 254 #define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ 255 #define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ 256 #define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ 257 #define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ 258 259 #define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ 260 #define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ 261 #define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ 262 #define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ 263 264 #define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ 265 #define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ 266 #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ 267 #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ 268 269 #define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ 270 #define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ 271 #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ 272 #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ 273 #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ 274 #define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ 275 276 #define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ 277 #define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ 278 #define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ 279 #define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ 280 #define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ 281 #define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ 282 #define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ 283 284 #define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ 285 #define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ 286 #define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ 287 #define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ 288 #define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ 289 #define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ 290 291 #define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ 292 #define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ 293 294 #define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ 295 #define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ 296 #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ 297 #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ 298 299 #define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ 300 #define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ 301 302 #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ 303 #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ 304 305 #define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ 306 #define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ 307 308 #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ 309 #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ 310 311 #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ 312 313 #define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ 314 #define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ 315 316 #define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ 317 318 #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ 319 #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ 320 #define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ 321 #define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ 322 323 #define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ 324 #define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ 325 #define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ 326 #define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ 327 328 #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ 329 #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ 330 #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ 331 #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ 332 333 #define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ 334 #define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ 335 336 #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ 337 #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ 338 339 #define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ 340 #define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */ 341 #define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */ 342 #define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */ 343 #define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */ 344 #define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */ 345 346 #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ 347 #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ 348 #define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ 349 #define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ 350 351 #define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ 352 #define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ 353 #define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ 354 #define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ 355 356 #define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ 357 #define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ 358 359 #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ 360 #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ 361 362 #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ 363 #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ 364 365 #define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ 366 367 368 /* DMAMUX2 requests */ 369 #define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 370 #define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ 371 #define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ 372 #define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ 373 #define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ 374 #define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ 375 #define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ 376 #define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ 377 #define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ 378 #define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ 379 #define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ 380 #define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ 381 #define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ 382 #define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ 383 #define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ 384 #define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ 385 #define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ 386 #define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ 387 388 /** 389 * @} 390 */ 391 392 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 393 * @brief DMA data transfer direction 394 * @{ 395 */ 396 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 397 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 398 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 404 * @brief DMA peripheral incremented mode 405 * @{ 406 */ 407 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 408 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 414 * @brief DMA memory incremented mode 415 * @{ 416 */ 417 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 418 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 424 * @brief DMA peripheral data size 425 * @{ 426 */ 427 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ 428 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 429 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup DMA_Memory_data_size DMA Memory data size 435 * @brief DMA memory data size 436 * @{ 437 */ 438 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ 439 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 440 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup DMA_mode DMA mode 446 * @brief DMA mode 447 * @{ 448 */ 449 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 450 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 451 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 452 #define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */ 453 #define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */ 454 /** 455 * @} 456 */ 457 458 /** @defgroup DMA_Priority_level DMA Priority level 459 * @brief DMA priority levels 460 * @{ 461 */ 462 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 463 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 464 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 465 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 466 /** 467 * @} 468 */ 469 470 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 471 * @brief DMA FIFO direct mode 472 * @{ 473 */ 474 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ 475 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 481 * @brief DMA FIFO level 482 * @{ 483 */ 484 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ 485 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 486 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 487 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup DMA_Memory_burst DMA Memory burst 493 * @brief DMA memory burst 494 * @{ 495 */ 496 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) 497 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 498 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 499 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 500 /** 501 * @} 502 */ 503 504 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 505 * @brief DMA peripheral burst 506 * @{ 507 */ 508 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) 509 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 510 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 511 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 512 /** 513 * @} 514 */ 515 516 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 517 * @brief DMA interrupts definition 518 * @{ 519 */ 520 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 521 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 522 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 523 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 524 #define DMA_IT_FE ((uint32_t)0x00000080U) 525 /** 526 * @} 527 */ 528 529 /** @defgroup DMA_flag_definitions DMA flag definitions 530 * @brief DMA flag definitions 531 * @{ 532 */ 533 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) 534 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) 535 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) 536 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) 537 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) 538 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) 539 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) 540 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) 541 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) 542 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) 543 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) 544 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) 545 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) 546 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) 547 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) 548 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) 549 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) 550 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) 551 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) 552 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) 553 /** 554 * @} 555 */ 556 557 /** @defgroup BDMA_flag_definitions BDMA flag definitions 558 * @brief BDMA flag definitions 559 * @{ 560 */ 561 #define BDMA_FLAG_GL0 ((uint32_t)0x00000001) 562 #define BDMA_FLAG_TC0 ((uint32_t)0x00000002) 563 #define BDMA_FLAG_HT0 ((uint32_t)0x00000004) 564 #define BDMA_FLAG_TE0 ((uint32_t)0x00000008) 565 #define BDMA_FLAG_GL1 ((uint32_t)0x00000010) 566 #define BDMA_FLAG_TC1 ((uint32_t)0x00000020) 567 #define BDMA_FLAG_HT1 ((uint32_t)0x00000040) 568 #define BDMA_FLAG_TE1 ((uint32_t)0x00000080) 569 #define BDMA_FLAG_GL2 ((uint32_t)0x00000100) 570 #define BDMA_FLAG_TC2 ((uint32_t)0x00000200) 571 #define BDMA_FLAG_HT2 ((uint32_t)0x00000400) 572 #define BDMA_FLAG_TE2 ((uint32_t)0x00000800) 573 #define BDMA_FLAG_GL3 ((uint32_t)0x00001000) 574 #define BDMA_FLAG_TC3 ((uint32_t)0x00002000) 575 #define BDMA_FLAG_HT3 ((uint32_t)0x00004000) 576 #define BDMA_FLAG_TE3 ((uint32_t)0x00008000) 577 #define BDMA_FLAG_GL4 ((uint32_t)0x00010000) 578 #define BDMA_FLAG_TC4 ((uint32_t)0x00020000) 579 #define BDMA_FLAG_HT4 ((uint32_t)0x00040000) 580 #define BDMA_FLAG_TE4 ((uint32_t)0x00080000) 581 #define BDMA_FLAG_GL5 ((uint32_t)0x00100000) 582 #define BDMA_FLAG_TC5 ((uint32_t)0x00200000) 583 #define BDMA_FLAG_HT5 ((uint32_t)0x00400000) 584 #define BDMA_FLAG_TE5 ((uint32_t)0x00800000) 585 #define BDMA_FLAG_GL6 ((uint32_t)0x01000000) 586 #define BDMA_FLAG_TC6 ((uint32_t)0x02000000) 587 #define BDMA_FLAG_HT6 ((uint32_t)0x04000000) 588 #define BDMA_FLAG_TE6 ((uint32_t)0x08000000) 589 #define BDMA_FLAG_GL7 ((uint32_t)0x10000000) 590 #define BDMA_FLAG_TC7 ((uint32_t)0x20000000) 591 #define BDMA_FLAG_HT7 ((uint32_t)0x40000000) 592 #define BDMA_FLAG_TE7 ((uint32_t)0x80000000) 593 594 /** 595 * @} 596 */ 597 598 /** 599 * @} 600 */ 601 602 /* Exported macro ------------------------------------------------------------*/ 603 /** @defgroup DMA_Exported_Macros DMA Exported Macros 604 * @{ 605 */ 606 607 /** @brief Reset DMA handle state 608 * @param __HANDLE__: specifies the DMA handle. 609 * @retval None 610 */ 611 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 612 613 /** 614 * @brief Return the current DMA Stream FIFO filled level. 615 * @param __HANDLE__: DMA handle 616 * @retval The FIFO filling state. 617 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 618 * and not empty. 619 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 620 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 621 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 622 * - DMA_FIFOStatus_Empty: when FIFO is empty 623 * - DMA_FIFOStatus_Full: when FIFO is full 624 */ 625 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) 626 627 /** 628 * @brief Enable the specified DMA Stream. 629 * @param __HANDLE__: DMA handle 630 * @retval None 631 */ 632 #define __HAL_DMA_ENABLE(__HANDLE__) \ 633 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \ 634 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) 635 636 /** 637 * @brief Disable the specified DMA Stream. 638 * @param __HANDLE__: DMA handle 639 * @retval None 640 */ 641 #define __HAL_DMA_DISABLE(__HANDLE__) \ 642 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \ 643 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) 644 645 /* Interrupt & Flag management */ 646 647 /** 648 * @brief Return the current DMA Stream transfer complete flag. 649 * @param __HANDLE__: DMA handle 650 * @retval The specified transfer complete flag index. 651 */ 652 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 653 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 661 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 662 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 663 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 664 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 665 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ 666 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ 667 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ 668 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ 669 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\ 670 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\ 671 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\ 672 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\ 673 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\ 674 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\ 675 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ 676 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ 677 (uint32_t)0x00000000) 678 679 /** 680 * @brief Return the current DMA Stream half transfer complete flag. 681 * @param __HANDLE__: DMA handle 682 * @retval The specified half transfer complete flag index. 683 */ 684 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 685 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 686 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 687 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 688 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 689 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 692 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 693 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 694 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 695 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 696 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 697 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ 698 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ 699 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ 700 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ 701 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\ 702 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\ 703 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\ 704 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\ 705 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\ 706 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\ 707 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ 708 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ 709 (uint32_t)0x00000000) 710 711 /** 712 * @brief Return the current DMA Stream transfer error flag. 713 * @param __HANDLE__: DMA handle 714 * @retval The specified transfer error flag index. 715 */ 716 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 717 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 718 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 719 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 720 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 723 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 724 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 725 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 726 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 727 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 728 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 729 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ 730 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ 731 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ 732 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ 733 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\ 734 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\ 735 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\ 736 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\ 737 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\ 738 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\ 739 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ 740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ 741 (uint32_t)0x00000000) 742 743 /** 744 * @brief Return the current DMA Stream FIFO error flag. 745 * @param __HANDLE__: DMA handle 746 * @retval The specified FIFO error flag index. 747 */ 748 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 749 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 750 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 751 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 752 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 753 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 754 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 755 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 756 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 761 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ 762 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ 763 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ 764 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ 765 (uint32_t)0x00000000) 766 767 /** 768 * @brief Return the current DMA Stream direct mode error flag. 769 * @param __HANDLE__: DMA handle 770 * @retval The specified direct mode error flag index. 771 */ 772 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 773 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 774 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 775 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 776 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 777 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 778 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 779 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 780 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 781 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 782 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 783 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 784 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 785 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ 786 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ 787 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ 788 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ 789 (uint32_t)0x00000000) 790 791 /** 792 * @brief Returns the current BDMA Channel Global interrupt flag. 793 * @param __HANDLE__: DMA handle 794 * @retval The specified transfer error flag index. 795 */ 796 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 797 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ 798 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ 799 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\ 800 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\ 801 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\ 802 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\ 803 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ 804 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ 805 (uint32_t)0x00000000) 806 807 /** 808 * @brief Get the DMA Stream pending flags. 809 * @param __HANDLE__: DMA handle 810 * @param __FLAG__: Get the specified flag. 811 * This parameter can be any combination of the following values: 812 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 813 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 814 * @arg DMA_FLAG_TEIFx: Transfer error flag. 815 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 816 * @arg DMA_FLAG_FEIFx: FIFO error flag. 817 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 818 * @retval The state of FLAG (SET or RESET). 819 */ 820 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 821 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ 822 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 823 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 824 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 825 826 /** 827 * @brief Clear the DMA Stream pending flags. 828 * @param __HANDLE__: DMA handle 829 * @param __FLAG__: specifies the flag to clear. 830 * This parameter can be any combination of the following values: 831 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 832 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 833 * @arg DMA_FLAG_TEIFx: Transfer error flag. 834 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 835 * @arg DMA_FLAG_FEIFx: FIFO error flag. 836 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 837 * @retval None 838 */ 839 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 840 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ 841 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 842 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 843 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 844 845 #define DMA_TO_BDMA_IT(__DMA_IT__) \ 846 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ 847 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\ 848 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ 849 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\ 850 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\ 851 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\ 852 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\ 853 (uint32_t)0x00000000) 854 855 856 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 857 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) 858 859 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 860 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) 861 862 /** 863 * @brief Enable the specified DMA Stream interrupts. 864 * @param __HANDLE__: DMA handle 865 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 866 * This parameter can be one of the following values: 867 * @arg DMA_IT_TC: Transfer complete interrupt mask. 868 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 869 * @arg DMA_IT_TE: Transfer error interrupt mask. 870 * @arg DMA_IT_FE: FIFO error interrupt mask. 871 * @arg DMA_IT_DME: Direct mode error interrupt. 872 * @retval None 873 */ 874 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ 875 (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ 876 (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) 877 878 879 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) 880 881 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 882 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) 883 884 /** 885 * @brief Disable the specified DMA Stream interrupts. 886 * @param __HANDLE__: DMA handle 887 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 888 * This parameter can be one of the following values: 889 * @arg DMA_IT_TC: Transfer complete interrupt mask. 890 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 891 * @arg DMA_IT_TE: Transfer error interrupt mask. 892 * @arg DMA_IT_FE: FIFO error interrupt mask. 893 * @arg DMA_IT_DME: Direct mode error interrupt. 894 * @retval None 895 */ 896 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ 897 (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ 898 (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) 899 900 901 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) 902 903 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 904 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ 905 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) 906 907 /** 908 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 909 * @param __HANDLE__: DMA handle 910 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 911 * This parameter can be one of the following values: 912 * @arg DMA_IT_TC: Transfer complete interrupt mask. 913 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 914 * @arg DMA_IT_TE: Transfer error interrupt mask. 915 * @arg DMA_IT_FE: FIFO error interrupt mask. 916 * @arg DMA_IT_DME: Direct mode error interrupt. 917 * @retval The state of DMA_IT. 918 */ 919 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 920 (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ 921 (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) 922 923 /** 924 * @brief Writes the number of data units to be transferred on the DMA Stream. 925 * @param __HANDLE__: DMA handle 926 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) 927 * Number of data items depends only on the Peripheral data format. 928 * 929 * @note If Peripheral data format is Bytes: number of data units is equal 930 * to total number of bytes to be transferred. 931 * 932 * @note If Peripheral data format is Half-Word: number of data units is 933 * equal to total number of bytes to be transferred / 2. 934 * 935 * @note If Peripheral data format is Word: number of data units is equal 936 * to total number of bytes to be transferred / 4. 937 * 938 * @retval The number of remaining data units in the current DMAy Streamx transfer. 939 */ 940 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 941 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\ 942 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) 943 944 /** 945 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 946 * @param __HANDLE__: DMA handle 947 * 948 * @retval The number of remaining data units in the current DMA Stream transfer. 949 */ 950 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 951 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\ 952 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) 953 954 /** 955 * @} 956 */ 957 958 /* Include DMA HAL Extension module */ 959 #include "stm32h7xx_hal_dma_ex.h" 960 961 /* Exported functions --------------------------------------------------------*/ 962 963 /** @defgroup DMA_Exported_Functions DMA Exported Functions 964 * @brief DMA Exported functions 965 * @{ 966 */ 967 968 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 969 * @brief Initialization and de-initialization functions 970 * @{ 971 */ 972 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 973 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 974 /** 975 * @} 976 */ 977 978 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 979 * @brief I/O operation functions 980 * @{ 981 */ 982 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 983 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 984 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 985 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 986 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 987 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 988 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 989 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 990 991 /** 992 * @} 993 */ 994 995 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 996 * @brief Peripheral State functions 997 * @{ 998 */ 999 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 1000 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 1001 /** 1002 * @} 1003 */ 1004 /** 1005 * @} 1006 */ 1007 /* Private Constants -------------------------------------------------------------*/ 1008 /** @defgroup DMA_Private_Constants DMA Private Constants 1009 * @brief DMA private defines and constants 1010 * @{ 1011 */ 1012 /** 1013 * @} 1014 */ 1015 1016 /* Private macros ------------------------------------------------------------*/ 1017 /** @defgroup DMA_Private_Macros DMA Private Macros 1018 * @brief DMA private macros 1019 * @{ 1020 */ 1021 1022 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) 1023 1024 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) 1025 1026 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 1027 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 1028 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 1029 1030 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 1031 1032 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 1033 ((STATE) == DMA_PINC_DISABLE)) 1034 1035 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 1036 ((STATE) == DMA_MINC_DISABLE)) 1037 1038 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 1039 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 1040 ((SIZE) == DMA_PDATAALIGN_WORD)) 1041 1042 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 1043 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 1044 ((SIZE) == DMA_MDATAALIGN_WORD )) 1045 1046 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 1047 ((MODE) == DMA_CIRCULAR) || \ 1048 ((MODE) == DMA_PFCTRL) || \ 1049 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ 1050 ((MODE) == DMA_DOUBLE_BUFFER_M1)) 1051 1052 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 1053 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 1054 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 1055 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 1056 1057 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 1058 ((STATE) == DMA_FIFOMODE_ENABLE)) 1059 1060 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 1061 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 1062 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 1063 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 1064 1065 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 1066 ((BURST) == DMA_MBURST_INC4) || \ 1067 ((BURST) == DMA_MBURST_INC8) || \ 1068 ((BURST) == DMA_MBURST_INC16)) 1069 1070 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 1071 ((BURST) == DMA_PBURST_INC4) || \ 1072 ((BURST) == DMA_PBURST_INC8) || \ 1073 ((BURST) == DMA_PBURST_INC16)) 1074 /** 1075 * @} 1076 */ 1077 1078 /* Private functions ---------------------------------------------------------*/ 1079 /** @defgroup DMA_Private_Functions DMA Private Functions 1080 * @brief DMA private functions 1081 * @{ 1082 */ 1083 /** 1084 * @} 1085 */ 1086 1087 /** 1088 * @} 1089 */ 1090 1091 /** 1092 * @} 1093 */ 1094 1095 #ifdef __cplusplus 1096 } 1097 #endif 1098 1099 #endif /* STM32H7xx_HAL_DMA_H */ 1100 1101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1102