1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145 (+) Break2Callback : TIM Break2 Callback.
146
147 [..]
148 By default, after the Init and when the state is HAL_TIM_STATE_RESET
149 all interrupt callbacks are set to the corresponding weak functions:
150 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
151
152 [..]
153 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
154 functionalities in the Init / DeInit only when these callbacks are null
155 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
156 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
157
158 [..]
159 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
160 Exception done MspInit / MspDeInit that can be registered / unregistered
161 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
162 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
163 In that case first register the MspInit/MspDeInit user callbacks
164 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
165
166 [..]
167 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
168 not defined, the callback registration feature is not available and all callbacks
169 are set to the corresponding weak functions.
170
171 @endverbatim
172 ******************************************************************************
173 * @attention
174 *
175 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
176 * All rights reserved.</center></h2>
177 *
178 * This software component is licensed by ST under BSD 3-Clause license,
179 * the "License"; You may not use this file except in compliance with the
180 * License. You may obtain a copy of the License at:
181 * opensource.org/licenses/BSD-3-Clause
182 *
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32h7xx_hal.h"
188
189 /** @addtogroup STM32H7xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macro -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
217 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
218 uint32_t TIM_ICFilter);
219 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
220 uint32_t TIM_ICFilter);
221 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
222 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
226 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
227 TIM_SlaveConfigTypeDef *sSlaveConfig);
228 /**
229 * @}
230 */
231 /* Exported functions --------------------------------------------------------*/
232
233 /** @defgroup TIM_Exported_Functions TIM Exported Functions
234 * @{
235 */
236
237 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
238 * @brief Time Base functions
239 *
240 @verbatim
241 ==============================================================================
242 ##### Time Base functions #####
243 ==============================================================================
244 [..]
245 This section provides functions allowing to:
246 (+) Initialize and configure the TIM base.
247 (+) De-initialize the TIM base.
248 (+) Start the Time Base.
249 (+) Stop the Time Base.
250 (+) Start the Time Base and enable interrupt.
251 (+) Stop the Time Base and disable interrupt.
252 (+) Start the Time Base and enable DMA transfer.
253 (+) Stop the Time Base and disable DMA transfer.
254
255 @endverbatim
256 * @{
257 */
258 /**
259 * @brief Initializes the TIM Time base Unit according to the specified
260 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
261 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
262 * requires a timer reset to avoid unexpected direction
263 * due to DIR bit readonly in center aligned mode.
264 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
265 * @param htim TIM Base handle
266 * @retval HAL status
267 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)268 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
269 {
270 /* Check the TIM handle allocation */
271 if (htim == NULL)
272 {
273 return HAL_ERROR;
274 }
275
276 /* Check the parameters */
277 assert_param(IS_TIM_INSTANCE(htim->Instance));
278 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
279 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
280 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
281
282 if (htim->State == HAL_TIM_STATE_RESET)
283 {
284 /* Allocate lock resource and initialize it */
285 htim->Lock = HAL_UNLOCKED;
286
287 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
288 /* Reset interrupt callbacks to legacy weak callbacks */
289 TIM_ResetCallback(htim);
290
291 if (htim->Base_MspInitCallback == NULL)
292 {
293 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
294 }
295 /* Init the low level hardware : GPIO, CLOCK, NVIC */
296 htim->Base_MspInitCallback(htim);
297 #else
298 /* Init the low level hardware : GPIO, CLOCK, NVIC */
299 HAL_TIM_Base_MspInit(htim);
300 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
301 }
302
303 /* Set the TIM state */
304 htim->State = HAL_TIM_STATE_BUSY;
305
306 /* Set the Time Base configuration */
307 TIM_Base_SetConfig(htim->Instance, &htim->Init);
308
309 /* Initialize the TIM state*/
310 htim->State = HAL_TIM_STATE_READY;
311
312 return HAL_OK;
313 }
314
315 /**
316 * @brief DeInitializes the TIM Base peripheral
317 * @param htim TIM Base handle
318 * @retval HAL status
319 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)320 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
321 {
322 /* Check the parameters */
323 assert_param(IS_TIM_INSTANCE(htim->Instance));
324
325 htim->State = HAL_TIM_STATE_BUSY;
326
327 /* Disable the TIM Peripheral Clock */
328 __HAL_TIM_DISABLE(htim);
329
330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
331 if (htim->Base_MspDeInitCallback == NULL)
332 {
333 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
334 }
335 /* DeInit the low level hardware */
336 htim->Base_MspDeInitCallback(htim);
337 #else
338 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
339 HAL_TIM_Base_MspDeInit(htim);
340 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
341
342 /* Change TIM state */
343 htim->State = HAL_TIM_STATE_RESET;
344
345 /* Release Lock */
346 __HAL_UNLOCK(htim);
347
348 return HAL_OK;
349 }
350
351 /**
352 * @brief Initializes the TIM Base MSP.
353 * @param htim TIM Base handle
354 * @retval None
355 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)356 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
357 {
358 /* Prevent unused argument(s) compilation warning */
359 UNUSED(htim);
360
361 /* NOTE : This function should not be modified, when the callback is needed,
362 the HAL_TIM_Base_MspInit could be implemented in the user file
363 */
364 }
365
366 /**
367 * @brief DeInitializes TIM Base MSP.
368 * @param htim TIM Base handle
369 * @retval None
370 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)371 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
372 {
373 /* Prevent unused argument(s) compilation warning */
374 UNUSED(htim);
375
376 /* NOTE : This function should not be modified, when the callback is needed,
377 the HAL_TIM_Base_MspDeInit could be implemented in the user file
378 */
379 }
380
381
382 /**
383 * @brief Starts the TIM Base generation.
384 * @param htim TIM Base handle
385 * @retval HAL status
386 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)387 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
388 {
389 uint32_t tmpsmcr;
390
391 /* Check the parameters */
392 assert_param(IS_TIM_INSTANCE(htim->Instance));
393
394 /* Set the TIM state */
395 htim->State = HAL_TIM_STATE_BUSY;
396
397 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
398 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
399 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
400 {
401 __HAL_TIM_ENABLE(htim);
402 }
403
404 /* Change the TIM state*/
405 htim->State = HAL_TIM_STATE_READY;
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Stops the TIM Base generation.
413 * @param htim TIM Base handle
414 * @retval HAL status
415 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
417 {
418 /* Check the parameters */
419 assert_param(IS_TIM_INSTANCE(htim->Instance));
420
421 /* Set the TIM state */
422 htim->State = HAL_TIM_STATE_BUSY;
423
424 /* Disable the Peripheral */
425 __HAL_TIM_DISABLE(htim);
426
427 /* Change the TIM state*/
428 htim->State = HAL_TIM_STATE_READY;
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Starts the TIM Base generation in interrupt mode.
436 * @param htim TIM Base handle
437 * @retval HAL status
438 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)439 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
440 {
441 uint32_t tmpsmcr;
442
443 /* Check the parameters */
444 assert_param(IS_TIM_INSTANCE(htim->Instance));
445
446 /* Enable the TIM Update interrupt */
447 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
448
449 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
450 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
451 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
452 {
453 __HAL_TIM_ENABLE(htim);
454 }
455
456 /* Return function status */
457 return HAL_OK;
458 }
459
460 /**
461 * @brief Stops the TIM Base generation in interrupt mode.
462 * @param htim TIM Base handle
463 * @retval HAL status
464 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)465 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
466 {
467 /* Check the parameters */
468 assert_param(IS_TIM_INSTANCE(htim->Instance));
469 /* Disable the TIM Update interrupt */
470 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
471
472 /* Disable the Peripheral */
473 __HAL_TIM_DISABLE(htim);
474
475 /* Return function status */
476 return HAL_OK;
477 }
478
479 /**
480 * @brief Starts the TIM Base generation in DMA mode.
481 * @param htim TIM Base handle
482 * @param pData The source Buffer address.
483 * @param Length The length of data to be transferred from memory to peripheral.
484 * @retval HAL status
485 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)486 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
487 {
488 uint32_t tmpsmcr;
489
490 /* Check the parameters */
491 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
492
493 if (htim->State == HAL_TIM_STATE_BUSY)
494 {
495 return HAL_BUSY;
496 }
497 else if (htim->State == HAL_TIM_STATE_READY)
498 {
499 if ((pData == NULL) && (Length > 0U))
500 {
501 return HAL_ERROR;
502 }
503 else
504 {
505 htim->State = HAL_TIM_STATE_BUSY;
506 }
507 }
508 else
509 {
510 /* nothing to do */
511 }
512
513 /* Set the DMA Period elapsed callbacks */
514 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
515 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
516
517 /* Set the DMA error callback */
518 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
519
520 /* Enable the DMA stream */
521 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
522 {
523 return HAL_ERROR;
524 }
525
526 /* Enable the TIM Update DMA request */
527 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
528
529 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
530 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
531 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
532 {
533 __HAL_TIM_ENABLE(htim);
534 }
535
536 /* Return function status */
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Stops the TIM Base generation in DMA mode.
542 * @param htim TIM Base handle
543 * @retval HAL status
544 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)545 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
546 {
547 /* Check the parameters */
548 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
549
550 /* Disable the TIM Update DMA request */
551 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
552
553 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
554
555 /* Disable the Peripheral */
556 __HAL_TIM_DISABLE(htim);
557
558 /* Change the htim state */
559 htim->State = HAL_TIM_STATE_READY;
560
561 /* Return function status */
562 return HAL_OK;
563 }
564
565 /**
566 * @}
567 */
568
569 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
570 * @brief TIM Output Compare functions
571 *
572 @verbatim
573 ==============================================================================
574 ##### TIM Output Compare functions #####
575 ==============================================================================
576 [..]
577 This section provides functions allowing to:
578 (+) Initialize and configure the TIM Output Compare.
579 (+) De-initialize the TIM Output Compare.
580 (+) Start the TIM Output Compare.
581 (+) Stop the TIM Output Compare.
582 (+) Start the TIM Output Compare and enable interrupt.
583 (+) Stop the TIM Output Compare and disable interrupt.
584 (+) Start the TIM Output Compare and enable DMA transfer.
585 (+) Stop the TIM Output Compare and disable DMA transfer.
586
587 @endverbatim
588 * @{
589 */
590 /**
591 * @brief Initializes the TIM Output Compare according to the specified
592 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
593 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
594 * requires a timer reset to avoid unexpected direction
595 * due to DIR bit readonly in center aligned mode.
596 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
597 * @param htim TIM Output Compare handle
598 * @retval HAL status
599 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)600 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
601 {
602 /* Check the TIM handle allocation */
603 if (htim == NULL)
604 {
605 return HAL_ERROR;
606 }
607
608 /* Check the parameters */
609 assert_param(IS_TIM_INSTANCE(htim->Instance));
610 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
611 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
612 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
613
614 if (htim->State == HAL_TIM_STATE_RESET)
615 {
616 /* Allocate lock resource and initialize it */
617 htim->Lock = HAL_UNLOCKED;
618
619 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
620 /* Reset interrupt callbacks to legacy weak callbacks */
621 TIM_ResetCallback(htim);
622
623 if (htim->OC_MspInitCallback == NULL)
624 {
625 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
626 }
627 /* Init the low level hardware : GPIO, CLOCK, NVIC */
628 htim->OC_MspInitCallback(htim);
629 #else
630 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
631 HAL_TIM_OC_MspInit(htim);
632 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
633 }
634
635 /* Set the TIM state */
636 htim->State = HAL_TIM_STATE_BUSY;
637
638 /* Init the base time for the Output Compare */
639 TIM_Base_SetConfig(htim->Instance, &htim->Init);
640
641 /* Initialize the TIM state*/
642 htim->State = HAL_TIM_STATE_READY;
643
644 return HAL_OK;
645 }
646
647 /**
648 * @brief DeInitializes the TIM peripheral
649 * @param htim TIM Output Compare handle
650 * @retval HAL status
651 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)652 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
653 {
654 /* Check the parameters */
655 assert_param(IS_TIM_INSTANCE(htim->Instance));
656
657 htim->State = HAL_TIM_STATE_BUSY;
658
659 /* Disable the TIM Peripheral Clock */
660 __HAL_TIM_DISABLE(htim);
661
662 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
663 if (htim->OC_MspDeInitCallback == NULL)
664 {
665 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
666 }
667 /* DeInit the low level hardware */
668 htim->OC_MspDeInitCallback(htim);
669 #else
670 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
671 HAL_TIM_OC_MspDeInit(htim);
672 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
673
674 /* Change TIM state */
675 htim->State = HAL_TIM_STATE_RESET;
676
677 /* Release Lock */
678 __HAL_UNLOCK(htim);
679
680 return HAL_OK;
681 }
682
683 /**
684 * @brief Initializes the TIM Output Compare MSP.
685 * @param htim TIM Output Compare handle
686 * @retval None
687 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)688 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
689 {
690 /* Prevent unused argument(s) compilation warning */
691 UNUSED(htim);
692
693 /* NOTE : This function should not be modified, when the callback is needed,
694 the HAL_TIM_OC_MspInit could be implemented in the user file
695 */
696 }
697
698 /**
699 * @brief DeInitializes TIM Output Compare MSP.
700 * @param htim TIM Output Compare handle
701 * @retval None
702 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)703 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
704 {
705 /* Prevent unused argument(s) compilation warning */
706 UNUSED(htim);
707
708 /* NOTE : This function should not be modified, when the callback is needed,
709 the HAL_TIM_OC_MspDeInit could be implemented in the user file
710 */
711 }
712
713 /**
714 * @brief Starts the TIM Output Compare signal generation.
715 * @param htim TIM Output Compare handle
716 * @param Channel TIM Channel to be enabled
717 * This parameter can be one of the following values:
718 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
719 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
720 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
721 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
722 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
723 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
724 * @retval HAL status
725 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)726 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
727 {
728 uint32_t tmpsmcr;
729
730 /* Check the parameters */
731 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
732
733 /* Enable the Output compare channel */
734 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
735
736 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
737 {
738 /* Enable the main output */
739 __HAL_TIM_MOE_ENABLE(htim);
740 }
741
742 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
743 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
744 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
745 {
746 __HAL_TIM_ENABLE(htim);
747 }
748
749 /* Return function status */
750 return HAL_OK;
751 }
752
753 /**
754 * @brief Stops the TIM Output Compare signal generation.
755 * @param htim TIM Output Compare handle
756 * @param Channel TIM Channel to be disabled
757 * This parameter can be one of the following values:
758 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
759 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
760 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
761 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
762 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
763 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
764 * @retval HAL status
765 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)766 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
767 {
768 /* Check the parameters */
769 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
770
771 /* Disable the Output compare channel */
772 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
773
774 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
775 {
776 /* Disable the Main Output */
777 __HAL_TIM_MOE_DISABLE(htim);
778 }
779
780 /* Disable the Peripheral */
781 __HAL_TIM_DISABLE(htim);
782
783 /* Return function status */
784 return HAL_OK;
785 }
786
787 /**
788 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
789 * @param htim TIM Output Compare handle
790 * @param Channel TIM Channel to be enabled
791 * This parameter can be one of the following values:
792 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
793 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
794 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
795 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
796 * @retval HAL status
797 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)798 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
799 {
800 uint32_t tmpsmcr;
801
802 /* Check the parameters */
803 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
804
805 switch (Channel)
806 {
807 case TIM_CHANNEL_1:
808 {
809 /* Enable the TIM Capture/Compare 1 interrupt */
810 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
811 break;
812 }
813
814 case TIM_CHANNEL_2:
815 {
816 /* Enable the TIM Capture/Compare 2 interrupt */
817 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
818 break;
819 }
820
821 case TIM_CHANNEL_3:
822 {
823 /* Enable the TIM Capture/Compare 3 interrupt */
824 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
825 break;
826 }
827
828 case TIM_CHANNEL_4:
829 {
830 /* Enable the TIM Capture/Compare 4 interrupt */
831 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
832 break;
833 }
834
835 default:
836 break;
837 }
838
839 /* Enable the Output compare channel */
840 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
841
842 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
843 {
844 /* Enable the main output */
845 __HAL_TIM_MOE_ENABLE(htim);
846 }
847
848 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
849 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
850 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
851 {
852 __HAL_TIM_ENABLE(htim);
853 }
854
855 /* Return function status */
856 return HAL_OK;
857 }
858
859 /**
860 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
861 * @param htim TIM Output Compare handle
862 * @param Channel TIM Channel to be disabled
863 * This parameter can be one of the following values:
864 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
865 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
866 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
867 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
868 * @retval HAL status
869 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)870 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
871 {
872 /* Check the parameters */
873 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
874
875 switch (Channel)
876 {
877 case TIM_CHANNEL_1:
878 {
879 /* Disable the TIM Capture/Compare 1 interrupt */
880 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
881 break;
882 }
883
884 case TIM_CHANNEL_2:
885 {
886 /* Disable the TIM Capture/Compare 2 interrupt */
887 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
888 break;
889 }
890
891 case TIM_CHANNEL_3:
892 {
893 /* Disable the TIM Capture/Compare 3 interrupt */
894 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
895 break;
896 }
897
898 case TIM_CHANNEL_4:
899 {
900 /* Disable the TIM Capture/Compare 4 interrupt */
901 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
902 break;
903 }
904
905 default:
906 break;
907 }
908
909 /* Disable the Output compare channel */
910 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
911
912 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
913 {
914 /* Disable the Main Output */
915 __HAL_TIM_MOE_DISABLE(htim);
916 }
917
918 /* Disable the Peripheral */
919 __HAL_TIM_DISABLE(htim);
920
921 /* Return function status */
922 return HAL_OK;
923 }
924
925 /**
926 * @brief Starts the TIM Output Compare signal generation in DMA mode.
927 * @param htim TIM Output Compare handle
928 * @param Channel TIM Channel to be enabled
929 * This parameter can be one of the following values:
930 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
931 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
932 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
933 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
934 * @param pData The source Buffer address.
935 * @param Length The length of data to be transferred from memory to TIM peripheral
936 * @retval HAL status
937 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)938 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
939 {
940 uint32_t tmpsmcr;
941
942 /* Check the parameters */
943 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
944
945 if (htim->State == HAL_TIM_STATE_BUSY)
946 {
947 return HAL_BUSY;
948 }
949 else if (htim->State == HAL_TIM_STATE_READY)
950 {
951 if ((pData == NULL) && (Length > 0U))
952 {
953 return HAL_ERROR;
954 }
955 else
956 {
957 htim->State = HAL_TIM_STATE_BUSY;
958 }
959 }
960 else
961 {
962 /* nothing to do */
963 }
964
965 switch (Channel)
966 {
967 case TIM_CHANNEL_1:
968 {
969 /* Set the DMA compare callbacks */
970 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
971 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
972
973 /* Set the DMA error callback */
974 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
975
976 /* Enable the DMA stream */
977 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
978 {
979 return HAL_ERROR;
980 }
981
982 /* Enable the TIM Capture/Compare 1 DMA request */
983 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
984 break;
985 }
986
987 case TIM_CHANNEL_2:
988 {
989 /* Set the DMA compare callbacks */
990 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
991 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
992
993 /* Set the DMA error callback */
994 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
995
996 /* Enable the DMA stream */
997 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
998 {
999 return HAL_ERROR;
1000 }
1001
1002 /* Enable the TIM Capture/Compare 2 DMA request */
1003 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1004 break;
1005 }
1006
1007 case TIM_CHANNEL_3:
1008 {
1009 /* Set the DMA compare callbacks */
1010 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1011 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1012
1013 /* Set the DMA error callback */
1014 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1015
1016 /* Enable the DMA stream */
1017 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1018 {
1019 return HAL_ERROR;
1020 }
1021 /* Enable the TIM Capture/Compare 3 DMA request */
1022 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1023 break;
1024 }
1025
1026 case TIM_CHANNEL_4:
1027 {
1028 /* Set the DMA compare callbacks */
1029 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1030 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1031
1032 /* Set the DMA error callback */
1033 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1034
1035 /* Enable the DMA stream */
1036 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1037 {
1038 return HAL_ERROR;
1039 }
1040 /* Enable the TIM Capture/Compare 4 DMA request */
1041 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1042 break;
1043 }
1044
1045 default:
1046 break;
1047 }
1048
1049 /* Enable the Output compare channel */
1050 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1051
1052 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1053 {
1054 /* Enable the main output */
1055 __HAL_TIM_MOE_ENABLE(htim);
1056 }
1057
1058 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1059 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1060 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1061 {
1062 __HAL_TIM_ENABLE(htim);
1063 }
1064
1065 /* Return function status */
1066 return HAL_OK;
1067 }
1068
1069 /**
1070 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1071 * @param htim TIM Output Compare handle
1072 * @param Channel TIM Channel to be disabled
1073 * This parameter can be one of the following values:
1074 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1075 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1076 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1077 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1078 * @retval HAL status
1079 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1080 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1081 {
1082 /* Check the parameters */
1083 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1084
1085 switch (Channel)
1086 {
1087 case TIM_CHANNEL_1:
1088 {
1089 /* Disable the TIM Capture/Compare 1 DMA request */
1090 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1091 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1092 break;
1093 }
1094
1095 case TIM_CHANNEL_2:
1096 {
1097 /* Disable the TIM Capture/Compare 2 DMA request */
1098 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1099 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1100 break;
1101 }
1102
1103 case TIM_CHANNEL_3:
1104 {
1105 /* Disable the TIM Capture/Compare 3 DMA request */
1106 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1107 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1108 break;
1109 }
1110
1111 case TIM_CHANNEL_4:
1112 {
1113 /* Disable the TIM Capture/Compare 4 interrupt */
1114 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1115 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1116 break;
1117 }
1118
1119 default:
1120 break;
1121 }
1122
1123 /* Disable the Output compare channel */
1124 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1125
1126 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1127 {
1128 /* Disable the Main Output */
1129 __HAL_TIM_MOE_DISABLE(htim);
1130 }
1131
1132 /* Disable the Peripheral */
1133 __HAL_TIM_DISABLE(htim);
1134
1135 /* Change the htim state */
1136 htim->State = HAL_TIM_STATE_READY;
1137
1138 /* Return function status */
1139 return HAL_OK;
1140 }
1141
1142 /**
1143 * @}
1144 */
1145
1146 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1147 * @brief TIM PWM functions
1148 *
1149 @verbatim
1150 ==============================================================================
1151 ##### TIM PWM functions #####
1152 ==============================================================================
1153 [..]
1154 This section provides functions allowing to:
1155 (+) Initialize and configure the TIM PWM.
1156 (+) De-initialize the TIM PWM.
1157 (+) Start the TIM PWM.
1158 (+) Stop the TIM PWM.
1159 (+) Start the TIM PWM and enable interrupt.
1160 (+) Stop the TIM PWM and disable interrupt.
1161 (+) Start the TIM PWM and enable DMA transfer.
1162 (+) Stop the TIM PWM and disable DMA transfer.
1163
1164 @endverbatim
1165 * @{
1166 */
1167 /**
1168 * @brief Initializes the TIM PWM Time Base according to the specified
1169 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1170 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1171 * requires a timer reset to avoid unexpected direction
1172 * due to DIR bit readonly in center aligned mode.
1173 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1174 * @param htim TIM PWM handle
1175 * @retval HAL status
1176 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1177 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1178 {
1179 /* Check the TIM handle allocation */
1180 if (htim == NULL)
1181 {
1182 return HAL_ERROR;
1183 }
1184
1185 /* Check the parameters */
1186 assert_param(IS_TIM_INSTANCE(htim->Instance));
1187 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1188 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1189 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1190
1191 if (htim->State == HAL_TIM_STATE_RESET)
1192 {
1193 /* Allocate lock resource and initialize it */
1194 htim->Lock = HAL_UNLOCKED;
1195
1196 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1197 /* Reset interrupt callbacks to legacy weak callbacks */
1198 TIM_ResetCallback(htim);
1199
1200 if (htim->PWM_MspInitCallback == NULL)
1201 {
1202 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1203 }
1204 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1205 htim->PWM_MspInitCallback(htim);
1206 #else
1207 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1208 HAL_TIM_PWM_MspInit(htim);
1209 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1210 }
1211
1212 /* Set the TIM state */
1213 htim->State = HAL_TIM_STATE_BUSY;
1214
1215 /* Init the base time for the PWM */
1216 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1217
1218 /* Initialize the TIM state*/
1219 htim->State = HAL_TIM_STATE_READY;
1220
1221 return HAL_OK;
1222 }
1223
1224 /**
1225 * @brief DeInitializes the TIM peripheral
1226 * @param htim TIM PWM handle
1227 * @retval HAL status
1228 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1229 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1230 {
1231 /* Check the parameters */
1232 assert_param(IS_TIM_INSTANCE(htim->Instance));
1233
1234 htim->State = HAL_TIM_STATE_BUSY;
1235
1236 /* Disable the TIM Peripheral Clock */
1237 __HAL_TIM_DISABLE(htim);
1238
1239 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1240 if (htim->PWM_MspDeInitCallback == NULL)
1241 {
1242 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1243 }
1244 /* DeInit the low level hardware */
1245 htim->PWM_MspDeInitCallback(htim);
1246 #else
1247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1248 HAL_TIM_PWM_MspDeInit(htim);
1249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1250
1251 /* Change TIM state */
1252 htim->State = HAL_TIM_STATE_RESET;
1253
1254 /* Release Lock */
1255 __HAL_UNLOCK(htim);
1256
1257 return HAL_OK;
1258 }
1259
1260 /**
1261 * @brief Initializes the TIM PWM MSP.
1262 * @param htim TIM PWM handle
1263 * @retval None
1264 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1265 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1266 {
1267 /* Prevent unused argument(s) compilation warning */
1268 UNUSED(htim);
1269
1270 /* NOTE : This function should not be modified, when the callback is needed,
1271 the HAL_TIM_PWM_MspInit could be implemented in the user file
1272 */
1273 }
1274
1275 /**
1276 * @brief DeInitializes TIM PWM MSP.
1277 * @param htim TIM PWM handle
1278 * @retval None
1279 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1280 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1281 {
1282 /* Prevent unused argument(s) compilation warning */
1283 UNUSED(htim);
1284
1285 /* NOTE : This function should not be modified, when the callback is needed,
1286 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1287 */
1288 }
1289
1290 /**
1291 * @brief Starts the PWM signal generation.
1292 * @param htim TIM handle
1293 * @param Channel TIM Channels to be enabled
1294 * This parameter can be one of the following values:
1295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1297 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1298 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1299 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1300 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1301 * @retval HAL status
1302 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1303 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1304 {
1305 uint32_t tmpsmcr;
1306
1307 /* Check the parameters */
1308 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1309
1310 /* Enable the Capture compare channel */
1311 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1312
1313 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1314 {
1315 /* Enable the main output */
1316 __HAL_TIM_MOE_ENABLE(htim);
1317 }
1318
1319 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1320 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1321 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1322 {
1323 __HAL_TIM_ENABLE(htim);
1324 }
1325
1326 /* Return function status */
1327 return HAL_OK;
1328 }
1329
1330 /**
1331 * @brief Stops the PWM signal generation.
1332 * @param htim TIM PWM handle
1333 * @param Channel TIM Channels to be disabled
1334 * This parameter can be one of the following values:
1335 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1336 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1337 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1338 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1339 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1340 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1341 * @retval HAL status
1342 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1343 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1344 {
1345 /* Check the parameters */
1346 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1347
1348 /* Disable the Capture compare channel */
1349 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1350
1351 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1352 {
1353 /* Disable the Main Output */
1354 __HAL_TIM_MOE_DISABLE(htim);
1355 }
1356
1357 /* Disable the Peripheral */
1358 __HAL_TIM_DISABLE(htim);
1359
1360 /* Change the htim state */
1361 htim->State = HAL_TIM_STATE_READY;
1362
1363 /* Return function status */
1364 return HAL_OK;
1365 }
1366
1367 /**
1368 * @brief Starts the PWM signal generation in interrupt mode.
1369 * @param htim TIM PWM handle
1370 * @param Channel TIM Channel to be enabled
1371 * This parameter can be one of the following values:
1372 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1373 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1374 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1375 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1376 * @retval HAL status
1377 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1378 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1379 {
1380 uint32_t tmpsmcr;
1381 /* Check the parameters */
1382 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1383
1384 switch (Channel)
1385 {
1386 case TIM_CHANNEL_1:
1387 {
1388 /* Enable the TIM Capture/Compare 1 interrupt */
1389 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1390 break;
1391 }
1392
1393 case TIM_CHANNEL_2:
1394 {
1395 /* Enable the TIM Capture/Compare 2 interrupt */
1396 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1397 break;
1398 }
1399
1400 case TIM_CHANNEL_3:
1401 {
1402 /* Enable the TIM Capture/Compare 3 interrupt */
1403 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1404 break;
1405 }
1406
1407 case TIM_CHANNEL_4:
1408 {
1409 /* Enable the TIM Capture/Compare 4 interrupt */
1410 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1411 break;
1412 }
1413
1414 default:
1415 break;
1416 }
1417
1418 /* Enable the Capture compare channel */
1419 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1420
1421 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1422 {
1423 /* Enable the main output */
1424 __HAL_TIM_MOE_ENABLE(htim);
1425 }
1426
1427 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1428 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1429 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1430 {
1431 __HAL_TIM_ENABLE(htim);
1432 }
1433
1434 /* Return function status */
1435 return HAL_OK;
1436 }
1437
1438 /**
1439 * @brief Stops the PWM signal generation in interrupt mode.
1440 * @param htim TIM PWM handle
1441 * @param Channel TIM Channels to be disabled
1442 * This parameter can be one of the following values:
1443 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1444 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1445 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1446 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1447 * @retval HAL status
1448 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1450 {
1451 /* Check the parameters */
1452 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1453
1454 switch (Channel)
1455 {
1456 case TIM_CHANNEL_1:
1457 {
1458 /* Disable the TIM Capture/Compare 1 interrupt */
1459 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1460 break;
1461 }
1462
1463 case TIM_CHANNEL_2:
1464 {
1465 /* Disable the TIM Capture/Compare 2 interrupt */
1466 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1467 break;
1468 }
1469
1470 case TIM_CHANNEL_3:
1471 {
1472 /* Disable the TIM Capture/Compare 3 interrupt */
1473 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1474 break;
1475 }
1476
1477 case TIM_CHANNEL_4:
1478 {
1479 /* Disable the TIM Capture/Compare 4 interrupt */
1480 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1481 break;
1482 }
1483
1484 default:
1485 break;
1486 }
1487
1488 /* Disable the Capture compare channel */
1489 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1490
1491 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1492 {
1493 /* Disable the Main Output */
1494 __HAL_TIM_MOE_DISABLE(htim);
1495 }
1496
1497 /* Disable the Peripheral */
1498 __HAL_TIM_DISABLE(htim);
1499
1500 /* Return function status */
1501 return HAL_OK;
1502 }
1503
1504 /**
1505 * @brief Starts the TIM PWM signal generation in DMA mode.
1506 * @param htim TIM PWM handle
1507 * @param Channel TIM Channels to be enabled
1508 * This parameter can be one of the following values:
1509 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1510 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1511 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1512 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1513 * @param pData The source Buffer address.
1514 * @param Length The length of data to be transferred from memory to TIM peripheral
1515 * @retval HAL status
1516 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1517 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1518 {
1519 uint32_t tmpsmcr;
1520
1521 /* Check the parameters */
1522 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1523
1524 if (htim->State == HAL_TIM_STATE_BUSY)
1525 {
1526 return HAL_BUSY;
1527 }
1528 else if (htim->State == HAL_TIM_STATE_READY)
1529 {
1530 if ((pData == NULL) && (Length > 0U))
1531 {
1532 return HAL_ERROR;
1533 }
1534 else
1535 {
1536 htim->State = HAL_TIM_STATE_BUSY;
1537 }
1538 }
1539 else
1540 {
1541 /* nothing to do */
1542 }
1543
1544 switch (Channel)
1545 {
1546 case TIM_CHANNEL_1:
1547 {
1548 /* Set the DMA compare callbacks */
1549 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1550 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1551
1552 /* Set the DMA error callback */
1553 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1554
1555 /* Enable the DMA stream */
1556 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1557 {
1558 return HAL_ERROR;
1559 }
1560
1561 /* Enable the TIM Capture/Compare 1 DMA request */
1562 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1563 break;
1564 }
1565
1566 case TIM_CHANNEL_2:
1567 {
1568 /* Set the DMA compare callbacks */
1569 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1570 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1571
1572 /* Set the DMA error callback */
1573 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1574
1575 /* Enable the DMA stream */
1576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1577 {
1578 return HAL_ERROR;
1579 }
1580 /* Enable the TIM Capture/Compare 2 DMA request */
1581 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1582 break;
1583 }
1584
1585 case TIM_CHANNEL_3:
1586 {
1587 /* Set the DMA compare callbacks */
1588 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1589 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1590
1591 /* Set the DMA error callback */
1592 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1593
1594 /* Enable the DMA stream */
1595 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1596 {
1597 return HAL_ERROR;
1598 }
1599 /* Enable the TIM Output Capture/Compare 3 request */
1600 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1601 break;
1602 }
1603
1604 case TIM_CHANNEL_4:
1605 {
1606 /* Set the DMA compare callbacks */
1607 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1608 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1609
1610 /* Set the DMA error callback */
1611 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1612
1613 /* Enable the DMA stream */
1614 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1615 {
1616 return HAL_ERROR;
1617 }
1618 /* Enable the TIM Capture/Compare 4 DMA request */
1619 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1620 break;
1621 }
1622
1623 default:
1624 break;
1625 }
1626
1627 /* Enable the Capture compare channel */
1628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1629
1630 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1631 {
1632 /* Enable the main output */
1633 __HAL_TIM_MOE_ENABLE(htim);
1634 }
1635
1636 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1637 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1638 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1639 {
1640 __HAL_TIM_ENABLE(htim);
1641 }
1642
1643 /* Return function status */
1644 return HAL_OK;
1645 }
1646
1647 /**
1648 * @brief Stops the TIM PWM signal generation in DMA mode.
1649 * @param htim TIM PWM handle
1650 * @param Channel TIM Channels to be disabled
1651 * This parameter can be one of the following values:
1652 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1653 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1654 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1655 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1656 * @retval HAL status
1657 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1658 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1659 {
1660 /* Check the parameters */
1661 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1662
1663 switch (Channel)
1664 {
1665 case TIM_CHANNEL_1:
1666 {
1667 /* Disable the TIM Capture/Compare 1 DMA request */
1668 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1669 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1670 break;
1671 }
1672
1673 case TIM_CHANNEL_2:
1674 {
1675 /* Disable the TIM Capture/Compare 2 DMA request */
1676 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1677 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1678 break;
1679 }
1680
1681 case TIM_CHANNEL_3:
1682 {
1683 /* Disable the TIM Capture/Compare 3 DMA request */
1684 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1685 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1686 break;
1687 }
1688
1689 case TIM_CHANNEL_4:
1690 {
1691 /* Disable the TIM Capture/Compare 4 interrupt */
1692 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1693 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1694 break;
1695 }
1696
1697 default:
1698 break;
1699 }
1700
1701 /* Disable the Capture compare channel */
1702 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1703
1704 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1705 {
1706 /* Disable the Main Output */
1707 __HAL_TIM_MOE_DISABLE(htim);
1708 }
1709
1710 /* Disable the Peripheral */
1711 __HAL_TIM_DISABLE(htim);
1712
1713 /* Change the htim state */
1714 htim->State = HAL_TIM_STATE_READY;
1715
1716 /* Return function status */
1717 return HAL_OK;
1718 }
1719
1720 /**
1721 * @}
1722 */
1723
1724 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1725 * @brief TIM Input Capture functions
1726 *
1727 @verbatim
1728 ==============================================================================
1729 ##### TIM Input Capture functions #####
1730 ==============================================================================
1731 [..]
1732 This section provides functions allowing to:
1733 (+) Initialize and configure the TIM Input Capture.
1734 (+) De-initialize the TIM Input Capture.
1735 (+) Start the TIM Input Capture.
1736 (+) Stop the TIM Input Capture.
1737 (+) Start the TIM Input Capture and enable interrupt.
1738 (+) Stop the TIM Input Capture and disable interrupt.
1739 (+) Start the TIM Input Capture and enable DMA transfer.
1740 (+) Stop the TIM Input Capture and disable DMA transfer.
1741
1742 @endverbatim
1743 * @{
1744 */
1745 /**
1746 * @brief Initializes the TIM Input Capture Time base according to the specified
1747 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1748 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1749 * requires a timer reset to avoid unexpected direction
1750 * due to DIR bit readonly in center aligned mode.
1751 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1752 * @param htim TIM Input Capture handle
1753 * @retval HAL status
1754 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1755 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1756 {
1757 /* Check the TIM handle allocation */
1758 if (htim == NULL)
1759 {
1760 return HAL_ERROR;
1761 }
1762
1763 /* Check the parameters */
1764 assert_param(IS_TIM_INSTANCE(htim->Instance));
1765 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1766 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1767 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1768
1769 if (htim->State == HAL_TIM_STATE_RESET)
1770 {
1771 /* Allocate lock resource and initialize it */
1772 htim->Lock = HAL_UNLOCKED;
1773
1774 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1775 /* Reset interrupt callbacks to legacy weak callbacks */
1776 TIM_ResetCallback(htim);
1777
1778 if (htim->IC_MspInitCallback == NULL)
1779 {
1780 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1781 }
1782 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1783 htim->IC_MspInitCallback(htim);
1784 #else
1785 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1786 HAL_TIM_IC_MspInit(htim);
1787 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1788 }
1789
1790 /* Set the TIM state */
1791 htim->State = HAL_TIM_STATE_BUSY;
1792
1793 /* Init the base time for the input capture */
1794 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1795
1796 /* Initialize the TIM state*/
1797 htim->State = HAL_TIM_STATE_READY;
1798
1799 return HAL_OK;
1800 }
1801
1802 /**
1803 * @brief DeInitializes the TIM peripheral
1804 * @param htim TIM Input Capture handle
1805 * @retval HAL status
1806 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1807 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1808 {
1809 /* Check the parameters */
1810 assert_param(IS_TIM_INSTANCE(htim->Instance));
1811
1812 htim->State = HAL_TIM_STATE_BUSY;
1813
1814 /* Disable the TIM Peripheral Clock */
1815 __HAL_TIM_DISABLE(htim);
1816
1817 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1818 if (htim->IC_MspDeInitCallback == NULL)
1819 {
1820 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1821 }
1822 /* DeInit the low level hardware */
1823 htim->IC_MspDeInitCallback(htim);
1824 #else
1825 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1826 HAL_TIM_IC_MspDeInit(htim);
1827 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1828
1829 /* Change TIM state */
1830 htim->State = HAL_TIM_STATE_RESET;
1831
1832 /* Release Lock */
1833 __HAL_UNLOCK(htim);
1834
1835 return HAL_OK;
1836 }
1837
1838 /**
1839 * @brief Initializes the TIM Input Capture MSP.
1840 * @param htim TIM Input Capture handle
1841 * @retval None
1842 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1843 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1844 {
1845 /* Prevent unused argument(s) compilation warning */
1846 UNUSED(htim);
1847
1848 /* NOTE : This function should not be modified, when the callback is needed,
1849 the HAL_TIM_IC_MspInit could be implemented in the user file
1850 */
1851 }
1852
1853 /**
1854 * @brief DeInitializes TIM Input Capture MSP.
1855 * @param htim TIM handle
1856 * @retval None
1857 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1858 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1859 {
1860 /* Prevent unused argument(s) compilation warning */
1861 UNUSED(htim);
1862
1863 /* NOTE : This function should not be modified, when the callback is needed,
1864 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1865 */
1866 }
1867
1868 /**
1869 * @brief Starts the TIM Input Capture measurement.
1870 * @param htim TIM Input Capture handle
1871 * @param Channel TIM Channels to be enabled
1872 * This parameter can be one of the following values:
1873 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1874 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1875 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1876 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1877 * @retval HAL status
1878 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1879 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1880 {
1881 uint32_t tmpsmcr;
1882
1883 /* Check the parameters */
1884 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1885
1886 /* Enable the Input Capture channel */
1887 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1888
1889 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1890 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1891 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1892 {
1893 __HAL_TIM_ENABLE(htim);
1894 }
1895
1896 /* Return function status */
1897 return HAL_OK;
1898 }
1899
1900 /**
1901 * @brief Stops the TIM Input Capture measurement.
1902 * @param htim TIM Input Capture handle
1903 * @param Channel TIM Channels to be disabled
1904 * This parameter can be one of the following values:
1905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1909 * @retval HAL status
1910 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1911 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1912 {
1913 /* Check the parameters */
1914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1915
1916 /* Disable the Input Capture channel */
1917 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1918
1919 /* Disable the Peripheral */
1920 __HAL_TIM_DISABLE(htim);
1921
1922 /* Return function status */
1923 return HAL_OK;
1924 }
1925
1926 /**
1927 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1928 * @param htim TIM Input Capture handle
1929 * @param Channel TIM Channels to be enabled
1930 * This parameter can be one of the following values:
1931 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1932 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1933 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1934 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1935 * @retval HAL status
1936 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1937 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1938 {
1939 uint32_t tmpsmcr;
1940
1941 /* Check the parameters */
1942 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1943
1944 switch (Channel)
1945 {
1946 case TIM_CHANNEL_1:
1947 {
1948 /* Enable the TIM Capture/Compare 1 interrupt */
1949 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1950 break;
1951 }
1952
1953 case TIM_CHANNEL_2:
1954 {
1955 /* Enable the TIM Capture/Compare 2 interrupt */
1956 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1957 break;
1958 }
1959
1960 case TIM_CHANNEL_3:
1961 {
1962 /* Enable the TIM Capture/Compare 3 interrupt */
1963 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1964 break;
1965 }
1966
1967 case TIM_CHANNEL_4:
1968 {
1969 /* Enable the TIM Capture/Compare 4 interrupt */
1970 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1971 break;
1972 }
1973
1974 default:
1975 break;
1976 }
1977 /* Enable the Input Capture channel */
1978 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1979
1980 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1981 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1982 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1983 {
1984 __HAL_TIM_ENABLE(htim);
1985 }
1986
1987 /* Return function status */
1988 return HAL_OK;
1989 }
1990
1991 /**
1992 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1993 * @param htim TIM Input Capture handle
1994 * @param Channel TIM Channels to be disabled
1995 * This parameter can be one of the following values:
1996 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1997 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1998 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1999 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2000 * @retval HAL status
2001 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2002 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2003 {
2004 /* Check the parameters */
2005 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2006
2007 switch (Channel)
2008 {
2009 case TIM_CHANNEL_1:
2010 {
2011 /* Disable the TIM Capture/Compare 1 interrupt */
2012 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2013 break;
2014 }
2015
2016 case TIM_CHANNEL_2:
2017 {
2018 /* Disable the TIM Capture/Compare 2 interrupt */
2019 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2020 break;
2021 }
2022
2023 case TIM_CHANNEL_3:
2024 {
2025 /* Disable the TIM Capture/Compare 3 interrupt */
2026 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2027 break;
2028 }
2029
2030 case TIM_CHANNEL_4:
2031 {
2032 /* Disable the TIM Capture/Compare 4 interrupt */
2033 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2034 break;
2035 }
2036
2037 default:
2038 break;
2039 }
2040
2041 /* Disable the Input Capture channel */
2042 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2043
2044 /* Disable the Peripheral */
2045 __HAL_TIM_DISABLE(htim);
2046
2047 /* Return function status */
2048 return HAL_OK;
2049 }
2050
2051 /**
2052 * @brief Starts the TIM Input Capture measurement in DMA mode.
2053 * @param htim TIM Input Capture handle
2054 * @param Channel TIM Channels to be enabled
2055 * This parameter can be one of the following values:
2056 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2057 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2058 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2059 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2060 * @param pData The destination Buffer address.
2061 * @param Length The length of data to be transferred from TIM peripheral to memory.
2062 * @retval HAL status
2063 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2064 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2065 {
2066 uint32_t tmpsmcr;
2067
2068 /* Check the parameters */
2069 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2070 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2071
2072 if (htim->State == HAL_TIM_STATE_BUSY)
2073 {
2074 return HAL_BUSY;
2075 }
2076 else if (htim->State == HAL_TIM_STATE_READY)
2077 {
2078 if ((pData == NULL) && (Length > 0U))
2079 {
2080 return HAL_ERROR;
2081 }
2082 else
2083 {
2084 htim->State = HAL_TIM_STATE_BUSY;
2085 }
2086 }
2087 else
2088 {
2089 /* nothing to do */
2090 }
2091
2092 switch (Channel)
2093 {
2094 case TIM_CHANNEL_1:
2095 {
2096 /* Set the DMA capture callbacks */
2097 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2098 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2099
2100 /* Set the DMA error callback */
2101 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2102
2103 /* Enable the DMA stream */
2104 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2105 {
2106 return HAL_ERROR;
2107 }
2108 /* Enable the TIM Capture/Compare 1 DMA request */
2109 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2110 break;
2111 }
2112
2113 case TIM_CHANNEL_2:
2114 {
2115 /* Set the DMA capture callbacks */
2116 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2117 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2118
2119 /* Set the DMA error callback */
2120 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2121
2122 /* Enable the DMA stream */
2123 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2124 {
2125 return HAL_ERROR;
2126 }
2127 /* Enable the TIM Capture/Compare 2 DMA request */
2128 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2129 break;
2130 }
2131
2132 case TIM_CHANNEL_3:
2133 {
2134 /* Set the DMA capture callbacks */
2135 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2136 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2137
2138 /* Set the DMA error callback */
2139 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2140
2141 /* Enable the DMA stream */
2142 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2143 {
2144 return HAL_ERROR;
2145 }
2146 /* Enable the TIM Capture/Compare 3 DMA request */
2147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2148 break;
2149 }
2150
2151 case TIM_CHANNEL_4:
2152 {
2153 /* Set the DMA capture callbacks */
2154 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2155 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2156
2157 /* Set the DMA error callback */
2158 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2159
2160 /* Enable the DMA stream */
2161 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2162 {
2163 return HAL_ERROR;
2164 }
2165 /* Enable the TIM Capture/Compare 4 DMA request */
2166 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2167 break;
2168 }
2169
2170 default:
2171 break;
2172 }
2173
2174 /* Enable the Input Capture channel */
2175 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2176
2177 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2178 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2179 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2180 {
2181 __HAL_TIM_ENABLE(htim);
2182 }
2183
2184 /* Return function status */
2185 return HAL_OK;
2186 }
2187
2188 /**
2189 * @brief Stops the TIM Input Capture measurement in DMA mode.
2190 * @param htim TIM Input Capture handle
2191 * @param Channel TIM Channels to be disabled
2192 * This parameter can be one of the following values:
2193 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2194 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2195 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2196 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2197 * @retval HAL status
2198 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2199 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2200 {
2201 /* Check the parameters */
2202 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2203 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2204
2205 switch (Channel)
2206 {
2207 case TIM_CHANNEL_1:
2208 {
2209 /* Disable the TIM Capture/Compare 1 DMA request */
2210 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2211 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2212 break;
2213 }
2214
2215 case TIM_CHANNEL_2:
2216 {
2217 /* Disable the TIM Capture/Compare 2 DMA request */
2218 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2219 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2220 break;
2221 }
2222
2223 case TIM_CHANNEL_3:
2224 {
2225 /* Disable the TIM Capture/Compare 3 DMA request */
2226 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2227 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_4:
2232 {
2233 /* Disable the TIM Capture/Compare 4 DMA request */
2234 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2235 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2236 break;
2237 }
2238
2239 default:
2240 break;
2241 }
2242
2243 /* Disable the Input Capture channel */
2244 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2245
2246 /* Disable the Peripheral */
2247 __HAL_TIM_DISABLE(htim);
2248
2249 /* Change the htim state */
2250 htim->State = HAL_TIM_STATE_READY;
2251
2252 /* Return function status */
2253 return HAL_OK;
2254 }
2255 /**
2256 * @}
2257 */
2258
2259 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2260 * @brief TIM One Pulse functions
2261 *
2262 @verbatim
2263 ==============================================================================
2264 ##### TIM One Pulse functions #####
2265 ==============================================================================
2266 [..]
2267 This section provides functions allowing to:
2268 (+) Initialize and configure the TIM One Pulse.
2269 (+) De-initialize the TIM One Pulse.
2270 (+) Start the TIM One Pulse.
2271 (+) Stop the TIM One Pulse.
2272 (+) Start the TIM One Pulse and enable interrupt.
2273 (+) Stop the TIM One Pulse and disable interrupt.
2274 (+) Start the TIM One Pulse and enable DMA transfer.
2275 (+) Stop the TIM One Pulse and disable DMA transfer.
2276
2277 @endverbatim
2278 * @{
2279 */
2280 /**
2281 * @brief Initializes the TIM One Pulse Time Base according to the specified
2282 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2283 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2284 * requires a timer reset to avoid unexpected direction
2285 * due to DIR bit readonly in center aligned mode.
2286 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2287 * @param htim TIM One Pulse handle
2288 * @param OnePulseMode Select the One pulse mode.
2289 * This parameter can be one of the following values:
2290 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2291 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2292 * @retval HAL status
2293 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2294 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2295 {
2296 /* Check the TIM handle allocation */
2297 if (htim == NULL)
2298 {
2299 return HAL_ERROR;
2300 }
2301
2302 /* Check the parameters */
2303 assert_param(IS_TIM_INSTANCE(htim->Instance));
2304 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2305 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2306 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2307 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2308
2309 if (htim->State == HAL_TIM_STATE_RESET)
2310 {
2311 /* Allocate lock resource and initialize it */
2312 htim->Lock = HAL_UNLOCKED;
2313
2314 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2315 /* Reset interrupt callbacks to legacy weak callbacks */
2316 TIM_ResetCallback(htim);
2317
2318 if (htim->OnePulse_MspInitCallback == NULL)
2319 {
2320 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2321 }
2322 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2323 htim->OnePulse_MspInitCallback(htim);
2324 #else
2325 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2326 HAL_TIM_OnePulse_MspInit(htim);
2327 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2328 }
2329
2330 /* Set the TIM state */
2331 htim->State = HAL_TIM_STATE_BUSY;
2332
2333 /* Configure the Time base in the One Pulse Mode */
2334 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2335
2336 /* Reset the OPM Bit */
2337 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2338
2339 /* Configure the OPM Mode */
2340 htim->Instance->CR1 |= OnePulseMode;
2341
2342 /* Initialize the TIM state*/
2343 htim->State = HAL_TIM_STATE_READY;
2344
2345 return HAL_OK;
2346 }
2347
2348 /**
2349 * @brief DeInitializes the TIM One Pulse
2350 * @param htim TIM One Pulse handle
2351 * @retval HAL status
2352 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2353 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2354 {
2355 /* Check the parameters */
2356 assert_param(IS_TIM_INSTANCE(htim->Instance));
2357
2358 htim->State = HAL_TIM_STATE_BUSY;
2359
2360 /* Disable the TIM Peripheral Clock */
2361 __HAL_TIM_DISABLE(htim);
2362
2363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2364 if (htim->OnePulse_MspDeInitCallback == NULL)
2365 {
2366 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2367 }
2368 /* DeInit the low level hardware */
2369 htim->OnePulse_MspDeInitCallback(htim);
2370 #else
2371 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2372 HAL_TIM_OnePulse_MspDeInit(htim);
2373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2374
2375 /* Change TIM state */
2376 htim->State = HAL_TIM_STATE_RESET;
2377
2378 /* Release Lock */
2379 __HAL_UNLOCK(htim);
2380
2381 return HAL_OK;
2382 }
2383
2384 /**
2385 * @brief Initializes the TIM One Pulse MSP.
2386 * @param htim TIM One Pulse handle
2387 * @retval None
2388 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2389 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2390 {
2391 /* Prevent unused argument(s) compilation warning */
2392 UNUSED(htim);
2393
2394 /* NOTE : This function should not be modified, when the callback is needed,
2395 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2396 */
2397 }
2398
2399 /**
2400 * @brief DeInitializes TIM One Pulse MSP.
2401 * @param htim TIM One Pulse handle
2402 * @retval None
2403 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2404 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2405 {
2406 /* Prevent unused argument(s) compilation warning */
2407 UNUSED(htim);
2408
2409 /* NOTE : This function should not be modified, when the callback is needed,
2410 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2411 */
2412 }
2413
2414 /**
2415 * @brief Starts the TIM One Pulse signal generation.
2416 * @param htim TIM One Pulse handle
2417 * @param OutputChannel TIM Channels to be enabled
2418 * This parameter can be one of the following values:
2419 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2420 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2421 * @retval HAL status
2422 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2423 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2424 {
2425 /* Prevent unused argument(s) compilation warning */
2426 UNUSED(OutputChannel);
2427
2428 /* Enable the Capture compare and the Input Capture channels
2429 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2430 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2431 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2432 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2433
2434 No need to enable the counter, it's enabled automatically by hardware
2435 (the counter starts in response to a stimulus and generate a pulse */
2436
2437 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2438 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2439
2440 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2441 {
2442 /* Enable the main output */
2443 __HAL_TIM_MOE_ENABLE(htim);
2444 }
2445
2446 /* Return function status */
2447 return HAL_OK;
2448 }
2449
2450 /**
2451 * @brief Stops the TIM One Pulse signal generation.
2452 * @param htim TIM One Pulse handle
2453 * @param OutputChannel TIM Channels to be disable
2454 * This parameter can be one of the following values:
2455 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2456 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2457 * @retval HAL status
2458 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2459 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2460 {
2461 /* Prevent unused argument(s) compilation warning */
2462 UNUSED(OutputChannel);
2463
2464 /* Disable the Capture compare and the Input Capture channels
2465 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2466 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2467 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2468 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2469
2470 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2472
2473 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2474 {
2475 /* Disable the Main Output */
2476 __HAL_TIM_MOE_DISABLE(htim);
2477 }
2478
2479 /* Disable the Peripheral */
2480 __HAL_TIM_DISABLE(htim);
2481
2482 /* Return function status */
2483 return HAL_OK;
2484 }
2485
2486 /**
2487 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2488 * @param htim TIM One Pulse handle
2489 * @param OutputChannel TIM Channels to be enabled
2490 * This parameter can be one of the following values:
2491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2493 * @retval HAL status
2494 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2495 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2496 {
2497 /* Prevent unused argument(s) compilation warning */
2498 UNUSED(OutputChannel);
2499
2500 /* Enable the Capture compare and the Input Capture channels
2501 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2502 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2503 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2504 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2505
2506 No need to enable the counter, it's enabled automatically by hardware
2507 (the counter starts in response to a stimulus and generate a pulse */
2508
2509 /* Enable the TIM Capture/Compare 1 interrupt */
2510 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2511
2512 /* Enable the TIM Capture/Compare 2 interrupt */
2513 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2514
2515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2516 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2517
2518 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2519 {
2520 /* Enable the main output */
2521 __HAL_TIM_MOE_ENABLE(htim);
2522 }
2523
2524 /* Return function status */
2525 return HAL_OK;
2526 }
2527
2528 /**
2529 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2530 * @param htim TIM One Pulse handle
2531 * @param OutputChannel TIM Channels to be enabled
2532 * This parameter can be one of the following values:
2533 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2534 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2535 * @retval HAL status
2536 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2537 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2538 {
2539 /* Prevent unused argument(s) compilation warning */
2540 UNUSED(OutputChannel);
2541
2542 /* Disable the TIM Capture/Compare 1 interrupt */
2543 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2544
2545 /* Disable the TIM Capture/Compare 2 interrupt */
2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2547
2548 /* Disable the Capture compare and the Input Capture channels
2549 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2550 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2551 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2552 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2553 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2554 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2555
2556 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2557 {
2558 /* Disable the Main Output */
2559 __HAL_TIM_MOE_DISABLE(htim);
2560 }
2561
2562 /* Disable the Peripheral */
2563 __HAL_TIM_DISABLE(htim);
2564
2565 /* Return function status */
2566 return HAL_OK;
2567 }
2568
2569 /**
2570 * @}
2571 */
2572
2573 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2574 * @brief TIM Encoder functions
2575 *
2576 @verbatim
2577 ==============================================================================
2578 ##### TIM Encoder functions #####
2579 ==============================================================================
2580 [..]
2581 This section provides functions allowing to:
2582 (+) Initialize and configure the TIM Encoder.
2583 (+) De-initialize the TIM Encoder.
2584 (+) Start the TIM Encoder.
2585 (+) Stop the TIM Encoder.
2586 (+) Start the TIM Encoder and enable interrupt.
2587 (+) Stop the TIM Encoder and disable interrupt.
2588 (+) Start the TIM Encoder and enable DMA transfer.
2589 (+) Stop the TIM Encoder and disable DMA transfer.
2590
2591 @endverbatim
2592 * @{
2593 */
2594 /**
2595 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2596 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2597 * requires a timer reset to avoid unexpected direction
2598 * due to DIR bit readonly in center aligned mode.
2599 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2600 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2601 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2602 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2603 * @param htim TIM Encoder Interface handle
2604 * @param sConfig TIM Encoder Interface configuration structure
2605 * @retval HAL status
2606 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2607 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2608 {
2609 uint32_t tmpsmcr;
2610 uint32_t tmpccmr1;
2611 uint32_t tmpccer;
2612
2613 /* Check the TIM handle allocation */
2614 if (htim == NULL)
2615 {
2616 return HAL_ERROR;
2617 }
2618
2619 /* Check the parameters */
2620 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2621 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2622 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2623 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2624 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2625 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2626 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2627 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2628 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2629 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2630 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2631 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2632 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2633
2634 if (htim->State == HAL_TIM_STATE_RESET)
2635 {
2636 /* Allocate lock resource and initialize it */
2637 htim->Lock = HAL_UNLOCKED;
2638
2639 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2640 /* Reset interrupt callbacks to legacy weak callbacks */
2641 TIM_ResetCallback(htim);
2642
2643 if (htim->Encoder_MspInitCallback == NULL)
2644 {
2645 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2646 }
2647 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2648 htim->Encoder_MspInitCallback(htim);
2649 #else
2650 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2651 HAL_TIM_Encoder_MspInit(htim);
2652 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2653 }
2654
2655 /* Set the TIM state */
2656 htim->State = HAL_TIM_STATE_BUSY;
2657
2658 /* Reset the SMS and ECE bits */
2659 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2660
2661 /* Configure the Time base in the Encoder Mode */
2662 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2663
2664 /* Get the TIMx SMCR register value */
2665 tmpsmcr = htim->Instance->SMCR;
2666
2667 /* Get the TIMx CCMR1 register value */
2668 tmpccmr1 = htim->Instance->CCMR1;
2669
2670 /* Get the TIMx CCER register value */
2671 tmpccer = htim->Instance->CCER;
2672
2673 /* Set the encoder Mode */
2674 tmpsmcr |= sConfig->EncoderMode;
2675
2676 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2677 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2678 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2679
2680 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2681 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2682 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2683 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2684 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2685
2686 /* Set the TI1 and the TI2 Polarities */
2687 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2688 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2689 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2690
2691 /* Write to TIMx SMCR */
2692 htim->Instance->SMCR = tmpsmcr;
2693
2694 /* Write to TIMx CCMR1 */
2695 htim->Instance->CCMR1 = tmpccmr1;
2696
2697 /* Write to TIMx CCER */
2698 htim->Instance->CCER = tmpccer;
2699
2700 /* Initialize the TIM state*/
2701 htim->State = HAL_TIM_STATE_READY;
2702
2703 return HAL_OK;
2704 }
2705
2706
2707 /**
2708 * @brief DeInitializes the TIM Encoder interface
2709 * @param htim TIM Encoder Interface handle
2710 * @retval HAL status
2711 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2712 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2713 {
2714 /* Check the parameters */
2715 assert_param(IS_TIM_INSTANCE(htim->Instance));
2716
2717 htim->State = HAL_TIM_STATE_BUSY;
2718
2719 /* Disable the TIM Peripheral Clock */
2720 __HAL_TIM_DISABLE(htim);
2721
2722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2723 if (htim->Encoder_MspDeInitCallback == NULL)
2724 {
2725 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2726 }
2727 /* DeInit the low level hardware */
2728 htim->Encoder_MspDeInitCallback(htim);
2729 #else
2730 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2731 HAL_TIM_Encoder_MspDeInit(htim);
2732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2733
2734 /* Change TIM state */
2735 htim->State = HAL_TIM_STATE_RESET;
2736
2737 /* Release Lock */
2738 __HAL_UNLOCK(htim);
2739
2740 return HAL_OK;
2741 }
2742
2743 /**
2744 * @brief Initializes the TIM Encoder Interface MSP.
2745 * @param htim TIM Encoder Interface handle
2746 * @retval None
2747 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)2748 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2749 {
2750 /* Prevent unused argument(s) compilation warning */
2751 UNUSED(htim);
2752
2753 /* NOTE : This function should not be modified, when the callback is needed,
2754 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2755 */
2756 }
2757
2758 /**
2759 * @brief DeInitializes TIM Encoder Interface MSP.
2760 * @param htim TIM Encoder Interface handle
2761 * @retval None
2762 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)2763 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2764 {
2765 /* Prevent unused argument(s) compilation warning */
2766 UNUSED(htim);
2767
2768 /* NOTE : This function should not be modified, when the callback is needed,
2769 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2770 */
2771 }
2772
2773 /**
2774 * @brief Starts the TIM Encoder Interface.
2775 * @param htim TIM Encoder Interface handle
2776 * @param Channel TIM Channels to be enabled
2777 * This parameter can be one of the following values:
2778 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2779 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2780 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2781 * @retval HAL status
2782 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2783 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2784 {
2785 /* Check the parameters */
2786 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2787
2788 /* Enable the encoder interface channels */
2789 switch (Channel)
2790 {
2791 case TIM_CHANNEL_1:
2792 {
2793 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2794 break;
2795 }
2796
2797 case TIM_CHANNEL_2:
2798 {
2799 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2800 break;
2801 }
2802
2803 default :
2804 {
2805 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2806 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2807 break;
2808 }
2809 }
2810 /* Enable the Peripheral */
2811 __HAL_TIM_ENABLE(htim);
2812
2813 /* Return function status */
2814 return HAL_OK;
2815 }
2816
2817 /**
2818 * @brief Stops the TIM Encoder Interface.
2819 * @param htim TIM Encoder Interface handle
2820 * @param Channel TIM Channels to be disabled
2821 * This parameter can be one of the following values:
2822 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2823 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2824 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2825 * @retval HAL status
2826 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2827 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2828 {
2829 /* Check the parameters */
2830 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2831
2832 /* Disable the Input Capture channels 1 and 2
2833 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2834 switch (Channel)
2835 {
2836 case TIM_CHANNEL_1:
2837 {
2838 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2839 break;
2840 }
2841
2842 case TIM_CHANNEL_2:
2843 {
2844 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2845 break;
2846 }
2847
2848 default :
2849 {
2850 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2851 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2852 break;
2853 }
2854 }
2855
2856 /* Disable the Peripheral */
2857 __HAL_TIM_DISABLE(htim);
2858
2859 /* Return function status */
2860 return HAL_OK;
2861 }
2862
2863 /**
2864 * @brief Starts the TIM Encoder Interface in interrupt mode.
2865 * @param htim TIM Encoder Interface handle
2866 * @param Channel TIM Channels to be enabled
2867 * This parameter can be one of the following values:
2868 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2869 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2870 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2871 * @retval HAL status
2872 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2873 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2874 {
2875 /* Check the parameters */
2876 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2877
2878 /* Enable the encoder interface channels */
2879 /* Enable the capture compare Interrupts 1 and/or 2 */
2880 switch (Channel)
2881 {
2882 case TIM_CHANNEL_1:
2883 {
2884 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2885 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2886 break;
2887 }
2888
2889 case TIM_CHANNEL_2:
2890 {
2891 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2892 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2893 break;
2894 }
2895
2896 default :
2897 {
2898 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2899 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2901 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2902 break;
2903 }
2904 }
2905
2906 /* Enable the Peripheral */
2907 __HAL_TIM_ENABLE(htim);
2908
2909 /* Return function status */
2910 return HAL_OK;
2911 }
2912
2913 /**
2914 * @brief Stops the TIM Encoder Interface in interrupt mode.
2915 * @param htim TIM Encoder Interface handle
2916 * @param Channel TIM Channels to be disabled
2917 * This parameter can be one of the following values:
2918 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2919 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2920 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2921 * @retval HAL status
2922 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2923 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2924 {
2925 /* Check the parameters */
2926 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2927
2928 /* Disable the Input Capture channels 1 and 2
2929 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2930 if (Channel == TIM_CHANNEL_1)
2931 {
2932 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2933
2934 /* Disable the capture compare Interrupts 1 */
2935 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2936 }
2937 else if (Channel == TIM_CHANNEL_2)
2938 {
2939 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2940
2941 /* Disable the capture compare Interrupts 2 */
2942 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2943 }
2944 else
2945 {
2946 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2947 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2948
2949 /* Disable the capture compare Interrupts 1 and 2 */
2950 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2951 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2952 }
2953
2954 /* Disable the Peripheral */
2955 __HAL_TIM_DISABLE(htim);
2956
2957 /* Change the htim state */
2958 htim->State = HAL_TIM_STATE_READY;
2959
2960 /* Return function status */
2961 return HAL_OK;
2962 }
2963
2964 /**
2965 * @brief Starts the TIM Encoder Interface in DMA mode.
2966 * @param htim TIM Encoder Interface handle
2967 * @param Channel TIM Channels to be enabled
2968 * This parameter can be one of the following values:
2969 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2970 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2971 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2972 * @param pData1 The destination Buffer address for IC1.
2973 * @param pData2 The destination Buffer address for IC2.
2974 * @param Length The length of data to be transferred from TIM peripheral to memory.
2975 * @retval HAL status
2976 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2977 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2978 uint32_t *pData2, uint16_t Length)
2979 {
2980 /* Check the parameters */
2981 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2982
2983 if (htim->State == HAL_TIM_STATE_BUSY)
2984 {
2985 return HAL_BUSY;
2986 }
2987 else if (htim->State == HAL_TIM_STATE_READY)
2988 {
2989 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
2990 {
2991 return HAL_ERROR;
2992 }
2993 else
2994 {
2995 htim->State = HAL_TIM_STATE_BUSY;
2996 }
2997 }
2998 else
2999 {
3000 /* nothing to do */
3001 }
3002
3003 switch (Channel)
3004 {
3005 case TIM_CHANNEL_1:
3006 {
3007 /* Set the DMA capture callbacks */
3008 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3009 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3010
3011 /* Set the DMA error callback */
3012 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3013
3014 /* Enable the DMA stream */
3015 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3016 {
3017 return HAL_ERROR;
3018 }
3019 /* Enable the TIM Input Capture DMA request */
3020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3021
3022 /* Enable the Peripheral */
3023 __HAL_TIM_ENABLE(htim);
3024
3025 /* Enable the Capture compare channel */
3026 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3027 break;
3028 }
3029
3030 case TIM_CHANNEL_2:
3031 {
3032 /* Set the DMA capture callbacks */
3033 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3034 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3035
3036 /* Set the DMA error callback */
3037 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3038 /* Enable the DMA stream */
3039 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3040 {
3041 return HAL_ERROR;
3042 }
3043 /* Enable the TIM Input Capture DMA request */
3044 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3045
3046 /* Enable the Peripheral */
3047 __HAL_TIM_ENABLE(htim);
3048
3049 /* Enable the Capture compare channel */
3050 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3051 break;
3052 }
3053
3054 case TIM_CHANNEL_ALL:
3055 {
3056 /* Set the DMA capture callbacks */
3057 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3058 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3059
3060 /* Set the DMA error callback */
3061 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3062
3063 /* Enable the DMA stream */
3064 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3065 {
3066 return HAL_ERROR;
3067 }
3068
3069 /* Set the DMA capture callbacks */
3070 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3071 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3072
3073 /* Set the DMA error callback */
3074 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3075
3076 /* Enable the DMA stream */
3077 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3078 {
3079 return HAL_ERROR;
3080 }
3081 /* Enable the Peripheral */
3082 __HAL_TIM_ENABLE(htim);
3083
3084 /* Enable the Capture compare channel */
3085 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3086 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3087
3088 /* Enable the TIM Input Capture DMA request */
3089 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3090 /* Enable the TIM Input Capture DMA request */
3091 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3092 break;
3093 }
3094
3095 default:
3096 break;
3097 }
3098 /* Return function status */
3099 return HAL_OK;
3100 }
3101
3102 /**
3103 * @brief Stops the TIM Encoder Interface in DMA mode.
3104 * @param htim TIM Encoder Interface handle
3105 * @param Channel TIM Channels to be enabled
3106 * This parameter can be one of the following values:
3107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3109 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3110 * @retval HAL status
3111 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3112 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3113 {
3114 /* Check the parameters */
3115 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
3116
3117 /* Disable the Input Capture channels 1 and 2
3118 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3119 if (Channel == TIM_CHANNEL_1)
3120 {
3121 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3122
3123 /* Disable the capture compare DMA Request 1 */
3124 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3125 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3126 }
3127 else if (Channel == TIM_CHANNEL_2)
3128 {
3129 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3130
3131 /* Disable the capture compare DMA Request 2 */
3132 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3133 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3134 }
3135 else
3136 {
3137 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3139
3140 /* Disable the capture compare DMA Request 1 and 2 */
3141 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3142 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3143 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3144 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3145 }
3146
3147 /* Disable the Peripheral */
3148 __HAL_TIM_DISABLE(htim);
3149
3150 /* Change the htim state */
3151 htim->State = HAL_TIM_STATE_READY;
3152
3153 /* Return function status */
3154 return HAL_OK;
3155 }
3156
3157 /**
3158 * @}
3159 */
3160 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3161 * @brief TIM IRQ handler management
3162 *
3163 @verbatim
3164 ==============================================================================
3165 ##### IRQ handler management #####
3166 ==============================================================================
3167 [..]
3168 This section provides Timer IRQ handler function.
3169
3170 @endverbatim
3171 * @{
3172 */
3173 /**
3174 * @brief This function handles TIM interrupts requests.
3175 * @param htim TIM handle
3176 * @retval None
3177 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3178 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3179 {
3180 /* Capture compare 1 event */
3181 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3182 {
3183 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3184 {
3185 {
3186 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3187 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3188
3189 /* Input capture event */
3190 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3191 {
3192 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3193 htim->IC_CaptureCallback(htim);
3194 #else
3195 HAL_TIM_IC_CaptureCallback(htim);
3196 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3197 }
3198 /* Output compare event */
3199 else
3200 {
3201 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3202 htim->OC_DelayElapsedCallback(htim);
3203 htim->PWM_PulseFinishedCallback(htim);
3204 #else
3205 HAL_TIM_OC_DelayElapsedCallback(htim);
3206 HAL_TIM_PWM_PulseFinishedCallback(htim);
3207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3208 }
3209 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3210 }
3211 }
3212 }
3213 /* Capture compare 2 event */
3214 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3215 {
3216 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3217 {
3218 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3219 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3220 /* Input capture event */
3221 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3222 {
3223 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3224 htim->IC_CaptureCallback(htim);
3225 #else
3226 HAL_TIM_IC_CaptureCallback(htim);
3227 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3228 }
3229 /* Output compare event */
3230 else
3231 {
3232 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3233 htim->OC_DelayElapsedCallback(htim);
3234 htim->PWM_PulseFinishedCallback(htim);
3235 #else
3236 HAL_TIM_OC_DelayElapsedCallback(htim);
3237 HAL_TIM_PWM_PulseFinishedCallback(htim);
3238 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3239 }
3240 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3241 }
3242 }
3243 /* Capture compare 3 event */
3244 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3245 {
3246 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3247 {
3248 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3249 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3250 /* Input capture event */
3251 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3252 {
3253 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3254 htim->IC_CaptureCallback(htim);
3255 #else
3256 HAL_TIM_IC_CaptureCallback(htim);
3257 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3258 }
3259 /* Output compare event */
3260 else
3261 {
3262 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3263 htim->OC_DelayElapsedCallback(htim);
3264 htim->PWM_PulseFinishedCallback(htim);
3265 #else
3266 HAL_TIM_OC_DelayElapsedCallback(htim);
3267 HAL_TIM_PWM_PulseFinishedCallback(htim);
3268 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3269 }
3270 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3271 }
3272 }
3273 /* Capture compare 4 event */
3274 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3275 {
3276 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3277 {
3278 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3279 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3280 /* Input capture event */
3281 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3282 {
3283 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3284 htim->IC_CaptureCallback(htim);
3285 #else
3286 HAL_TIM_IC_CaptureCallback(htim);
3287 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3288 }
3289 /* Output compare event */
3290 else
3291 {
3292 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3293 htim->OC_DelayElapsedCallback(htim);
3294 htim->PWM_PulseFinishedCallback(htim);
3295 #else
3296 HAL_TIM_OC_DelayElapsedCallback(htim);
3297 HAL_TIM_PWM_PulseFinishedCallback(htim);
3298 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3299 }
3300 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3301 }
3302 }
3303 /* TIM Update event */
3304 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3305 {
3306 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3307 {
3308 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3309 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3310 htim->PeriodElapsedCallback(htim);
3311 #else
3312 HAL_TIM_PeriodElapsedCallback(htim);
3313 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3314 }
3315 }
3316 /* TIM Break input event */
3317 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3318 {
3319 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3320 {
3321 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3322 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3323 htim->BreakCallback(htim);
3324 #else
3325 HAL_TIMEx_BreakCallback(htim);
3326 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3327 }
3328 }
3329 /* TIM Break2 input event */
3330 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3331 {
3332 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3333 {
3334 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3336 htim->Break2Callback(htim);
3337 #else
3338 HAL_TIMEx_Break2Callback(htim);
3339 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3340 }
3341 }
3342 /* TIM Trigger detection event */
3343 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3344 {
3345 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3346 {
3347 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3349 htim->TriggerCallback(htim);
3350 #else
3351 HAL_TIM_TriggerCallback(htim);
3352 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3353 }
3354 }
3355 /* TIM commutation event */
3356 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3357 {
3358 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3359 {
3360 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3362 htim->CommutationCallback(htim);
3363 #else
3364 HAL_TIMEx_CommutCallback(htim);
3365 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3366 }
3367 }
3368 }
3369
3370 /**
3371 * @}
3372 */
3373
3374 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3375 * @brief TIM Peripheral Control functions
3376 *
3377 @verbatim
3378 ==============================================================================
3379 ##### Peripheral Control functions #####
3380 ==============================================================================
3381 [..]
3382 This section provides functions allowing to:
3383 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3384 (+) Configure External Clock source.
3385 (+) Configure Complementary channels, break features and dead time.
3386 (+) Configure Master and the Slave synchronization.
3387 (+) Configure the DMA Burst Mode.
3388
3389 @endverbatim
3390 * @{
3391 */
3392
3393 /**
3394 * @brief Initializes the TIM Output Compare Channels according to the specified
3395 * parameters in the TIM_OC_InitTypeDef.
3396 * @param htim TIM Output Compare handle
3397 * @param sConfig TIM Output Compare configuration structure
3398 * @param Channel TIM Channels to configure
3399 * This parameter can be one of the following values:
3400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3402 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3403 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3404 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3405 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3406 * @retval HAL status
3407 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3408 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3409 TIM_OC_InitTypeDef *sConfig,
3410 uint32_t Channel)
3411 {
3412 /* Check the parameters */
3413 assert_param(IS_TIM_CHANNELS(Channel));
3414 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3415 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3416
3417 /* Process Locked */
3418 __HAL_LOCK(htim);
3419
3420 htim->State = HAL_TIM_STATE_BUSY;
3421
3422 switch (Channel)
3423 {
3424 case TIM_CHANNEL_1:
3425 {
3426 /* Check the parameters */
3427 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3428
3429 /* Configure the TIM Channel 1 in Output Compare */
3430 TIM_OC1_SetConfig(htim->Instance, sConfig);
3431 break;
3432 }
3433
3434 case TIM_CHANNEL_2:
3435 {
3436 /* Check the parameters */
3437 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3438
3439 /* Configure the TIM Channel 2 in Output Compare */
3440 TIM_OC2_SetConfig(htim->Instance, sConfig);
3441 break;
3442 }
3443
3444 case TIM_CHANNEL_3:
3445 {
3446 /* Check the parameters */
3447 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3448
3449 /* Configure the TIM Channel 3 in Output Compare */
3450 TIM_OC3_SetConfig(htim->Instance, sConfig);
3451 break;
3452 }
3453
3454 case TIM_CHANNEL_4:
3455 {
3456 /* Check the parameters */
3457 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3458
3459 /* Configure the TIM Channel 4 in Output Compare */
3460 TIM_OC4_SetConfig(htim->Instance, sConfig);
3461 break;
3462 }
3463
3464 case TIM_CHANNEL_5:
3465 {
3466 /* Check the parameters */
3467 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3468
3469 /* Configure the TIM Channel 5 in Output Compare */
3470 TIM_OC5_SetConfig(htim->Instance, sConfig);
3471 break;
3472 }
3473
3474 case TIM_CHANNEL_6:
3475 {
3476 /* Check the parameters */
3477 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3478
3479 /* Configure the TIM Channel 6 in Output Compare */
3480 TIM_OC6_SetConfig(htim->Instance, sConfig);
3481 break;
3482 }
3483
3484 default:
3485 break;
3486 }
3487
3488 htim->State = HAL_TIM_STATE_READY;
3489
3490 __HAL_UNLOCK(htim);
3491
3492 return HAL_OK;
3493 }
3494
3495 /**
3496 * @brief Initializes the TIM Input Capture Channels according to the specified
3497 * parameters in the TIM_IC_InitTypeDef.
3498 * @param htim TIM IC handle
3499 * @param sConfig TIM Input Capture configuration structure
3500 * @param Channel TIM Channel to configure
3501 * This parameter can be one of the following values:
3502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3504 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3505 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3506 * @retval HAL status
3507 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3508 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3509 {
3510 /* Check the parameters */
3511 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3512 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3513 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3514 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3515 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3516
3517 /* Process Locked */
3518 __HAL_LOCK(htim);
3519
3520 htim->State = HAL_TIM_STATE_BUSY;
3521
3522 if (Channel == TIM_CHANNEL_1)
3523 {
3524 /* TI1 Configuration */
3525 TIM_TI1_SetConfig(htim->Instance,
3526 sConfig->ICPolarity,
3527 sConfig->ICSelection,
3528 sConfig->ICFilter);
3529
3530 /* Reset the IC1PSC Bits */
3531 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3532
3533 /* Set the IC1PSC value */
3534 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3535 }
3536 else if (Channel == TIM_CHANNEL_2)
3537 {
3538 /* TI2 Configuration */
3539 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3540
3541 TIM_TI2_SetConfig(htim->Instance,
3542 sConfig->ICPolarity,
3543 sConfig->ICSelection,
3544 sConfig->ICFilter);
3545
3546 /* Reset the IC2PSC Bits */
3547 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3548
3549 /* Set the IC2PSC value */
3550 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3551 }
3552 else if (Channel == TIM_CHANNEL_3)
3553 {
3554 /* TI3 Configuration */
3555 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3556
3557 TIM_TI3_SetConfig(htim->Instance,
3558 sConfig->ICPolarity,
3559 sConfig->ICSelection,
3560 sConfig->ICFilter);
3561
3562 /* Reset the IC3PSC Bits */
3563 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3564
3565 /* Set the IC3PSC value */
3566 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3567 }
3568 else
3569 {
3570 /* TI4 Configuration */
3571 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3572
3573 TIM_TI4_SetConfig(htim->Instance,
3574 sConfig->ICPolarity,
3575 sConfig->ICSelection,
3576 sConfig->ICFilter);
3577
3578 /* Reset the IC4PSC Bits */
3579 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3580
3581 /* Set the IC4PSC value */
3582 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3583 }
3584
3585 htim->State = HAL_TIM_STATE_READY;
3586
3587 __HAL_UNLOCK(htim);
3588
3589 return HAL_OK;
3590 }
3591
3592 /**
3593 * @brief Initializes the TIM PWM channels according to the specified
3594 * parameters in the TIM_OC_InitTypeDef.
3595 * @param htim TIM PWM handle
3596 * @param sConfig TIM PWM configuration structure
3597 * @param Channel TIM Channels to be configured
3598 * This parameter can be one of the following values:
3599 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3600 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3601 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3602 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3603 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3604 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3605 * @retval HAL status
3606 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3607 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
3608 TIM_OC_InitTypeDef *sConfig,
3609 uint32_t Channel)
3610 {
3611 /* Check the parameters */
3612 assert_param(IS_TIM_CHANNELS(Channel));
3613 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3614 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3615 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3616
3617 /* Process Locked */
3618 __HAL_LOCK(htim);
3619
3620 htim->State = HAL_TIM_STATE_BUSY;
3621
3622 switch (Channel)
3623 {
3624 case TIM_CHANNEL_1:
3625 {
3626 /* Check the parameters */
3627 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3628
3629 /* Configure the Channel 1 in PWM mode */
3630 TIM_OC1_SetConfig(htim->Instance, sConfig);
3631
3632 /* Set the Preload enable bit for channel1 */
3633 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3634
3635 /* Configure the Output Fast mode */
3636 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3637 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3638 break;
3639 }
3640
3641 case TIM_CHANNEL_2:
3642 {
3643 /* Check the parameters */
3644 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3645
3646 /* Configure the Channel 2 in PWM mode */
3647 TIM_OC2_SetConfig(htim->Instance, sConfig);
3648
3649 /* Set the Preload enable bit for channel2 */
3650 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3651
3652 /* Configure the Output Fast mode */
3653 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3654 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3655 break;
3656 }
3657
3658 case TIM_CHANNEL_3:
3659 {
3660 /* Check the parameters */
3661 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3662
3663 /* Configure the Channel 3 in PWM mode */
3664 TIM_OC3_SetConfig(htim->Instance, sConfig);
3665
3666 /* Set the Preload enable bit for channel3 */
3667 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3668
3669 /* Configure the Output Fast mode */
3670 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3671 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3672 break;
3673 }
3674
3675 case TIM_CHANNEL_4:
3676 {
3677 /* Check the parameters */
3678 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3679
3680 /* Configure the Channel 4 in PWM mode */
3681 TIM_OC4_SetConfig(htim->Instance, sConfig);
3682
3683 /* Set the Preload enable bit for channel4 */
3684 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3685
3686 /* Configure the Output Fast mode */
3687 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3688 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3689 break;
3690 }
3691
3692 case TIM_CHANNEL_5:
3693 {
3694 /* Check the parameters */
3695 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3696
3697 /* Configure the Channel 5 in PWM mode */
3698 TIM_OC5_SetConfig(htim->Instance, sConfig);
3699
3700 /* Set the Preload enable bit for channel5*/
3701 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
3702
3703 /* Configure the Output Fast mode */
3704 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
3705 htim->Instance->CCMR3 |= sConfig->OCFastMode;
3706 break;
3707 }
3708
3709 case TIM_CHANNEL_6:
3710 {
3711 /* Check the parameters */
3712 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3713
3714 /* Configure the Channel 6 in PWM mode */
3715 TIM_OC6_SetConfig(htim->Instance, sConfig);
3716
3717 /* Set the Preload enable bit for channel6 */
3718 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
3719
3720 /* Configure the Output Fast mode */
3721 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
3722 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
3723 break;
3724 }
3725
3726 default:
3727 break;
3728 }
3729
3730 htim->State = HAL_TIM_STATE_READY;
3731
3732 __HAL_UNLOCK(htim);
3733
3734 return HAL_OK;
3735 }
3736
3737 /**
3738 * @brief Initializes the TIM One Pulse Channels according to the specified
3739 * parameters in the TIM_OnePulse_InitTypeDef.
3740 * @param htim TIM One Pulse handle
3741 * @param sConfig TIM One Pulse configuration structure
3742 * @param OutputChannel TIM output channel to configure
3743 * This parameter can be one of the following values:
3744 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3745 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3746 * @param InputChannel TIM input Channel to configure
3747 * This parameter can be one of the following values:
3748 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3749 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3750 * @note To output a waveform with a minimum delay user can enable the fast
3751 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
3752 * output is forced in response to the edge detection on TIx input,
3753 * without taking in account the comparison.
3754 * @retval HAL status
3755 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3756 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
3757 uint32_t OutputChannel, uint32_t InputChannel)
3758 {
3759 TIM_OC_InitTypeDef temp1;
3760
3761 /* Check the parameters */
3762 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3763 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3764
3765 if (OutputChannel != InputChannel)
3766 {
3767 /* Process Locked */
3768 __HAL_LOCK(htim);
3769
3770 htim->State = HAL_TIM_STATE_BUSY;
3771
3772 /* Extract the Output compare configuration from sConfig structure */
3773 temp1.OCMode = sConfig->OCMode;
3774 temp1.Pulse = sConfig->Pulse;
3775 temp1.OCPolarity = sConfig->OCPolarity;
3776 temp1.OCNPolarity = sConfig->OCNPolarity;
3777 temp1.OCIdleState = sConfig->OCIdleState;
3778 temp1.OCNIdleState = sConfig->OCNIdleState;
3779
3780 switch (OutputChannel)
3781 {
3782 case TIM_CHANNEL_1:
3783 {
3784 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3785
3786 TIM_OC1_SetConfig(htim->Instance, &temp1);
3787 break;
3788 }
3789 case TIM_CHANNEL_2:
3790 {
3791 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3792
3793 TIM_OC2_SetConfig(htim->Instance, &temp1);
3794 break;
3795 }
3796 default:
3797 break;
3798 }
3799
3800 switch (InputChannel)
3801 {
3802 case TIM_CHANNEL_1:
3803 {
3804 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3805
3806 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3807 sConfig->ICSelection, sConfig->ICFilter);
3808
3809 /* Reset the IC1PSC Bits */
3810 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3811
3812 /* Select the Trigger source */
3813 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3814 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3815
3816 /* Select the Slave Mode */
3817 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3818 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3819 break;
3820 }
3821 case TIM_CHANNEL_2:
3822 {
3823 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3824
3825 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3826 sConfig->ICSelection, sConfig->ICFilter);
3827
3828 /* Reset the IC2PSC Bits */
3829 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3830
3831 /* Select the Trigger source */
3832 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3833 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3834
3835 /* Select the Slave Mode */
3836 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3837 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3838 break;
3839 }
3840
3841 default:
3842 break;
3843 }
3844
3845 htim->State = HAL_TIM_STATE_READY;
3846
3847 __HAL_UNLOCK(htim);
3848
3849 return HAL_OK;
3850 }
3851 else
3852 {
3853 return HAL_ERROR;
3854 }
3855 }
3856
3857 /**
3858 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3859 * @param htim TIM handle
3860 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3861 * This parameter can be one of the following values:
3862 * @arg TIM_DMABASE_CR1
3863 * @arg TIM_DMABASE_CR2
3864 * @arg TIM_DMABASE_SMCR
3865 * @arg TIM_DMABASE_DIER
3866 * @arg TIM_DMABASE_SR
3867 * @arg TIM_DMABASE_EGR
3868 * @arg TIM_DMABASE_CCMR1
3869 * @arg TIM_DMABASE_CCMR2
3870 * @arg TIM_DMABASE_CCER
3871 * @arg TIM_DMABASE_CNT
3872 * @arg TIM_DMABASE_PSC
3873 * @arg TIM_DMABASE_ARR
3874 * @arg TIM_DMABASE_RCR
3875 * @arg TIM_DMABASE_CCR1
3876 * @arg TIM_DMABASE_CCR2
3877 * @arg TIM_DMABASE_CCR3
3878 * @arg TIM_DMABASE_CCR4
3879 * @arg TIM_DMABASE_BDTR
3880 * @arg TIM_DMABASE_CCMR3
3881 * @arg TIM_DMABASE_CCR5
3882 * @arg TIM_DMABASE_CCR6
3883 * @arg TIM_DMABASE_AF1
3884 * @arg TIM_DMABASE_AF2
3885 * @arg TIM_DMABASE_TISEL
3886 *
3887 * @param BurstRequestSrc TIM DMA Request sources
3888 * This parameter can be one of the following values:
3889 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3890 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3891 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3892 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3893 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3894 * @arg TIM_DMA_COM: TIM Commutation DMA source
3895 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3896 * @param BurstBuffer The Buffer address.
3897 * @param BurstLength DMA Burst length. This parameter can be one value
3898 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3899 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
3900 * @retval HAL status
3901 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3902 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
3903 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
3904 {
3905 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
3906 ((BurstLength) >> 8U) + 1U);
3907 }
3908
3909 /**
3910 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
3911 * @param htim TIM handle
3912 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3913 * This parameter can be one of the following values:
3914 * @arg TIM_DMABASE_CR1
3915 * @arg TIM_DMABASE_CR2
3916 * @arg TIM_DMABASE_SMCR
3917 * @arg TIM_DMABASE_DIER
3918 * @arg TIM_DMABASE_SR
3919 * @arg TIM_DMABASE_EGR
3920 * @arg TIM_DMABASE_CCMR1
3921 * @arg TIM_DMABASE_CCMR2
3922 * @arg TIM_DMABASE_CCER
3923 * @arg TIM_DMABASE_CNT
3924 * @arg TIM_DMABASE_PSC
3925 * @arg TIM_DMABASE_ARR
3926 * @arg TIM_DMABASE_RCR
3927 * @arg TIM_DMABASE_CCR1
3928 * @arg TIM_DMABASE_CCR2
3929 * @arg TIM_DMABASE_CCR3
3930 * @arg TIM_DMABASE_CCR4
3931 * @arg TIM_DMABASE_BDTR
3932 * @arg TIM_DMABASE_CCMR3
3933 * @arg TIM_DMABASE_CCR5
3934 * @arg TIM_DMABASE_CCR6
3935 * @arg TIM_DMABASE_AF1
3936 * @arg TIM_DMABASE_AF2
3937 * @arg TIM_DMABASE_TISEL
3938 *
3939 * @param BurstRequestSrc TIM DMA Request sources
3940 * This parameter can be one of the following values:
3941 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3942 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3943 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3944 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3945 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3946 * @arg TIM_DMA_COM: TIM Commutation DMA source
3947 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3948 * @param BurstBuffer The Buffer address.
3949 * @param BurstLength DMA Burst length. This parameter can be one value
3950 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3951 * @param DataLength Data length. This parameter can be one value
3952 * between 1 and 0xFFFF.
3953 * @retval HAL status
3954 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)3955 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
3956 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
3957 uint32_t BurstLength, uint32_t DataLength)
3958 {
3959 /* Check the parameters */
3960 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3961 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3962 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3963 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3964 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
3965
3966 if (htim->State == HAL_TIM_STATE_BUSY)
3967 {
3968 return HAL_BUSY;
3969 }
3970 else if (htim->State == HAL_TIM_STATE_READY)
3971 {
3972 if ((BurstBuffer == NULL) && (BurstLength > 0U))
3973 {
3974 return HAL_ERROR;
3975 }
3976 else
3977 {
3978 htim->State = HAL_TIM_STATE_BUSY;
3979 }
3980 }
3981 else
3982 {
3983 /* nothing to do */
3984 }
3985 switch (BurstRequestSrc)
3986 {
3987 case TIM_DMA_UPDATE:
3988 {
3989 /* Set the DMA Period elapsed callbacks */
3990 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3991 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
3992
3993 /* Set the DMA error callback */
3994 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3995
3996 /* Enable the DMA stream */
3997 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
3998 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
3999 {
4000 return HAL_ERROR;
4001 }
4002 break;
4003 }
4004 case TIM_DMA_CC1:
4005 {
4006 /* Set the DMA compare callbacks */
4007 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4008 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4009
4010 /* Set the DMA error callback */
4011 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4012
4013 /* Enable the DMA stream */
4014 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4015 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4016 {
4017 return HAL_ERROR;
4018 }
4019 break;
4020 }
4021 case TIM_DMA_CC2:
4022 {
4023 /* Set the DMA compare callbacks */
4024 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4025 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4026
4027 /* Set the DMA error callback */
4028 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4029
4030 /* Enable the DMA stream */
4031 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4032 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4033 {
4034 return HAL_ERROR;
4035 }
4036 break;
4037 }
4038 case TIM_DMA_CC3:
4039 {
4040 /* Set the DMA compare callbacks */
4041 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4042 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4043
4044 /* Set the DMA error callback */
4045 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4046
4047 /* Enable the DMA stream */
4048 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4049 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4050 {
4051 return HAL_ERROR;
4052 }
4053 break;
4054 }
4055 case TIM_DMA_CC4:
4056 {
4057 /* Set the DMA compare callbacks */
4058 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4059 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4060
4061 /* Set the DMA error callback */
4062 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4063
4064 /* Enable the DMA stream */
4065 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4066 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4067 {
4068 return HAL_ERROR;
4069 }
4070 break;
4071 }
4072 case TIM_DMA_COM:
4073 {
4074 /* Set the DMA commutation callbacks */
4075 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4076 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4077
4078 /* Set the DMA error callback */
4079 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4080
4081 /* Enable the DMA stream */
4082 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4083 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4084 {
4085 return HAL_ERROR;
4086 }
4087 break;
4088 }
4089 case TIM_DMA_TRIGGER:
4090 {
4091 /* Set the DMA trigger callbacks */
4092 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4093 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4094
4095 /* Set the DMA error callback */
4096 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4097
4098 /* Enable the DMA stream */
4099 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4100 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4101 {
4102 return HAL_ERROR;
4103 }
4104 break;
4105 }
4106 default:
4107 break;
4108 }
4109
4110 /* Configure the DMA Burst Mode */
4111 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4112 /* Enable the TIM DMA Request */
4113 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4114
4115 htim->State = HAL_TIM_STATE_READY;
4116
4117 /* Return function status */
4118 return HAL_OK;
4119 }
4120
4121 /**
4122 * @brief Stops the TIM DMA Burst mode
4123 * @param htim TIM handle
4124 * @param BurstRequestSrc TIM DMA Request sources to disable
4125 * @retval HAL status
4126 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4127 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4128 {
4129 HAL_StatusTypeDef status = HAL_OK;
4130 /* Check the parameters */
4131 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4132
4133 /* Abort the DMA transfer (at least disable the DMA stream) */
4134 switch (BurstRequestSrc)
4135 {
4136 case TIM_DMA_UPDATE:
4137 {
4138 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4139 break;
4140 }
4141 case TIM_DMA_CC1:
4142 {
4143 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4144 break;
4145 }
4146 case TIM_DMA_CC2:
4147 {
4148 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4149 break;
4150 }
4151 case TIM_DMA_CC3:
4152 {
4153 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4154 break;
4155 }
4156 case TIM_DMA_CC4:
4157 {
4158 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4159 break;
4160 }
4161 case TIM_DMA_COM:
4162 {
4163 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4164 break;
4165 }
4166 case TIM_DMA_TRIGGER:
4167 {
4168 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4169 break;
4170 }
4171 default:
4172 break;
4173 }
4174
4175 if (HAL_OK == status)
4176 {
4177 /* Disable the TIM Update DMA request */
4178 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4179 }
4180
4181 /* Return function status */
4182 return status;
4183 }
4184
4185 /**
4186 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4187 * @param htim TIM handle
4188 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4189 * This parameter can be one of the following values:
4190 * @arg TIM_DMABASE_CR1
4191 * @arg TIM_DMABASE_CR2
4192 * @arg TIM_DMABASE_SMCR
4193 * @arg TIM_DMABASE_DIER
4194 * @arg TIM_DMABASE_SR
4195 * @arg TIM_DMABASE_EGR
4196 * @arg TIM_DMABASE_CCMR1
4197 * @arg TIM_DMABASE_CCMR2
4198 * @arg TIM_DMABASE_CCER
4199 * @arg TIM_DMABASE_CNT
4200 * @arg TIM_DMABASE_PSC
4201 * @arg TIM_DMABASE_ARR
4202 * @arg TIM_DMABASE_RCR
4203 * @arg TIM_DMABASE_CCR1
4204 * @arg TIM_DMABASE_CCR2
4205 * @arg TIM_DMABASE_CCR3
4206 * @arg TIM_DMABASE_CCR4
4207 * @arg TIM_DMABASE_BDTR
4208 * @arg TIM_DMABASE_CCMR3
4209 * @arg TIM_DMABASE_CCR5
4210 * @arg TIM_DMABASE_CCR6
4211 * @arg TIM_DMABASE_AF1
4212 * @arg TIM_DMABASE_AF2
4213 * @arg TIM_DMABASE_TISEL
4214 *
4215 * @param BurstRequestSrc TIM DMA Request sources
4216 * This parameter can be one of the following values:
4217 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4218 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4219 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4220 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4221 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4222 * @arg TIM_DMA_COM: TIM Commutation DMA source
4223 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4224 * @param BurstBuffer The Buffer address.
4225 * @param BurstLength DMA Burst length. This parameter can be one value
4226 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4227 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4228 * @retval HAL status
4229 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4230 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4231 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4232 {
4233 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4234 ((BurstLength) >> 8U) + 1U);
4235 }
4236
4237 /**
4238 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4239 * @param htim TIM handle
4240 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4241 * This parameter can be one of the following values:
4242 * @arg TIM_DMABASE_CR1
4243 * @arg TIM_DMABASE_CR2
4244 * @arg TIM_DMABASE_SMCR
4245 * @arg TIM_DMABASE_DIER
4246 * @arg TIM_DMABASE_SR
4247 * @arg TIM_DMABASE_EGR
4248 * @arg TIM_DMABASE_CCMR1
4249 * @arg TIM_DMABASE_CCMR2
4250 * @arg TIM_DMABASE_CCER
4251 * @arg TIM_DMABASE_CNT
4252 * @arg TIM_DMABASE_PSC
4253 * @arg TIM_DMABASE_ARR
4254 * @arg TIM_DMABASE_RCR
4255 * @arg TIM_DMABASE_CCR1
4256 * @arg TIM_DMABASE_CCR2
4257 * @arg TIM_DMABASE_CCR3
4258 * @arg TIM_DMABASE_CCR4
4259 * @arg TIM_DMABASE_BDTR
4260 * @arg TIM_DMABASE_CCMR3
4261 * @arg TIM_DMABASE_CCR5
4262 * @arg TIM_DMABASE_CCR6
4263 * @arg TIM_DMABASE_AF1
4264 * @arg TIM_DMABASE_AF2
4265 * @arg TIM_DMABASE_TISEL
4266 *
4267 * @param BurstRequestSrc TIM DMA Request sources
4268 * This parameter can be one of the following values:
4269 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4270 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4271 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4272 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4273 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4274 * @arg TIM_DMA_COM: TIM Commutation DMA source
4275 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4276 * @param BurstBuffer The Buffer address.
4277 * @param BurstLength DMA Burst length. This parameter can be one value
4278 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4279 * @param DataLength Data length. This parameter can be one value
4280 * between 1 and 0xFFFF.
4281 * @retval HAL status
4282 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4283 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4284 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4285 uint32_t BurstLength, uint32_t DataLength)
4286 {
4287 /* Check the parameters */
4288 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4289 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4290 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4291 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4292 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4293
4294 if (htim->State == HAL_TIM_STATE_BUSY)
4295 {
4296 return HAL_BUSY;
4297 }
4298 else if (htim->State == HAL_TIM_STATE_READY)
4299 {
4300 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4301 {
4302 return HAL_ERROR;
4303 }
4304 else
4305 {
4306 htim->State = HAL_TIM_STATE_BUSY;
4307 }
4308 }
4309 else
4310 {
4311 /* nothing to do */
4312 }
4313 switch (BurstRequestSrc)
4314 {
4315 case TIM_DMA_UPDATE:
4316 {
4317 /* Set the DMA Period elapsed callbacks */
4318 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4319 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4320
4321 /* Set the DMA error callback */
4322 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4323
4324 /* Enable the DMA stream */
4325 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4326 DataLength) != HAL_OK)
4327 {
4328 return HAL_ERROR;
4329 }
4330 break;
4331 }
4332 case TIM_DMA_CC1:
4333 {
4334 /* Set the DMA capture callbacks */
4335 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4336 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4337
4338 /* Set the DMA error callback */
4339 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4340
4341 /* Enable the DMA stream */
4342 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4343 DataLength) != HAL_OK)
4344 {
4345 return HAL_ERROR;
4346 }
4347 break;
4348 }
4349 case TIM_DMA_CC2:
4350 {
4351 /* Set the DMA capture callbacks */
4352 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4353 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4354
4355 /* Set the DMA error callback */
4356 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4357
4358 /* Enable the DMA stream */
4359 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4360 DataLength) != HAL_OK)
4361 {
4362 return HAL_ERROR;
4363 }
4364 break;
4365 }
4366 case TIM_DMA_CC3:
4367 {
4368 /* Set the DMA capture callbacks */
4369 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4370 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4371
4372 /* Set the DMA error callback */
4373 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4374
4375 /* Enable the DMA stream */
4376 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4377 DataLength) != HAL_OK)
4378 {
4379 return HAL_ERROR;
4380 }
4381 break;
4382 }
4383 case TIM_DMA_CC4:
4384 {
4385 /* Set the DMA capture callbacks */
4386 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4387 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4388
4389 /* Set the DMA error callback */
4390 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4391
4392 /* Enable the DMA stream */
4393 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4394 DataLength) != HAL_OK)
4395 {
4396 return HAL_ERROR;
4397 }
4398 break;
4399 }
4400 case TIM_DMA_COM:
4401 {
4402 /* Set the DMA commutation callbacks */
4403 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4404 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4405
4406 /* Set the DMA error callback */
4407 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4408
4409 /* Enable the DMA stream */
4410 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4411 DataLength) != HAL_OK)
4412 {
4413 return HAL_ERROR;
4414 }
4415 break;
4416 }
4417 case TIM_DMA_TRIGGER:
4418 {
4419 /* Set the DMA trigger callbacks */
4420 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4421 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4422
4423 /* Set the DMA error callback */
4424 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4425
4426 /* Enable the DMA stream */
4427 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4428 DataLength) != HAL_OK)
4429 {
4430 return HAL_ERROR;
4431 }
4432 break;
4433 }
4434 default:
4435 break;
4436 }
4437
4438 /* Configure the DMA Burst Mode */
4439 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4440
4441 /* Enable the TIM DMA Request */
4442 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4443
4444 htim->State = HAL_TIM_STATE_READY;
4445
4446 /* Return function status */
4447 return HAL_OK;
4448 }
4449
4450 /**
4451 * @brief Stop the DMA burst reading
4452 * @param htim TIM handle
4453 * @param BurstRequestSrc TIM DMA Request sources to disable.
4454 * @retval HAL status
4455 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4456 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4457 {
4458 HAL_StatusTypeDef status = HAL_OK;
4459 /* Check the parameters */
4460 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4461
4462 /* Abort the DMA transfer (at least disable the DMA stream) */
4463 switch (BurstRequestSrc)
4464 {
4465 case TIM_DMA_UPDATE:
4466 {
4467 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4468 break;
4469 }
4470 case TIM_DMA_CC1:
4471 {
4472 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4473 break;
4474 }
4475 case TIM_DMA_CC2:
4476 {
4477 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4478 break;
4479 }
4480 case TIM_DMA_CC3:
4481 {
4482 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4483 break;
4484 }
4485 case TIM_DMA_CC4:
4486 {
4487 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4488 break;
4489 }
4490 case TIM_DMA_COM:
4491 {
4492 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4493 break;
4494 }
4495 case TIM_DMA_TRIGGER:
4496 {
4497 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4498 break;
4499 }
4500 default:
4501 break;
4502 }
4503
4504 if (HAL_OK == status)
4505 {
4506 /* Disable the TIM Update DMA request */
4507 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4508 }
4509
4510 /* Return function status */
4511 return status;
4512 }
4513
4514 /**
4515 * @brief Generate a software event
4516 * @param htim TIM handle
4517 * @param EventSource specifies the event source.
4518 * This parameter can be one of the following values:
4519 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4520 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4521 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4522 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4523 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4524 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4525 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4526 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4527 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
4528 * @note Basic timers can only generate an update event.
4529 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4530 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
4531 * only for timer instances supporting break input(s).
4532 * @retval HAL status
4533 */
4534
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4535 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4536 {
4537 /* Check the parameters */
4538 assert_param(IS_TIM_INSTANCE(htim->Instance));
4539 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4540
4541 /* Process Locked */
4542 __HAL_LOCK(htim);
4543
4544 /* Change the TIM state */
4545 htim->State = HAL_TIM_STATE_BUSY;
4546
4547 /* Set the event sources */
4548 htim->Instance->EGR = EventSource;
4549
4550 /* Change the TIM state */
4551 htim->State = HAL_TIM_STATE_READY;
4552
4553 __HAL_UNLOCK(htim);
4554
4555 /* Return function status */
4556 return HAL_OK;
4557 }
4558
4559 /**
4560 * @brief Configures the OCRef clear feature
4561 * @param htim TIM handle
4562 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4563 * contains the OCREF clear feature and parameters for the TIM peripheral.
4564 * @param Channel specifies the TIM Channel
4565 * This parameter can be one of the following values:
4566 * @arg TIM_CHANNEL_1: TIM Channel 1
4567 * @arg TIM_CHANNEL_2: TIM Channel 2
4568 * @arg TIM_CHANNEL_3: TIM Channel 3
4569 * @arg TIM_CHANNEL_4: TIM Channel 4
4570 * @arg TIM_CHANNEL_5: TIM Channel 5
4571 * @arg TIM_CHANNEL_6: TIM Channel 6
4572 * @retval HAL status
4573 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4574 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4575 TIM_ClearInputConfigTypeDef *sClearInputConfig,
4576 uint32_t Channel)
4577 {
4578 /* Check the parameters */
4579 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4580 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4581
4582 /* Process Locked */
4583 __HAL_LOCK(htim);
4584
4585 htim->State = HAL_TIM_STATE_BUSY;
4586
4587 switch (sClearInputConfig->ClearInputSource)
4588 {
4589 case TIM_CLEARINPUTSOURCE_NONE:
4590 {
4591 /* Clear the OCREF clear selection bit and the the ETR Bits */
4592 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4593 break;
4594 }
4595
4596 case TIM_CLEARINPUTSOURCE_ETR:
4597 {
4598 /* Check the parameters */
4599 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4600 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4601 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4602
4603 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4604 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4605 {
4606 htim->State = HAL_TIM_STATE_READY;
4607 __HAL_UNLOCK(htim);
4608 return HAL_ERROR;
4609 }
4610
4611 TIM_ETR_SetConfig(htim->Instance,
4612 sClearInputConfig->ClearInputPrescaler,
4613 sClearInputConfig->ClearInputPolarity,
4614 sClearInputConfig->ClearInputFilter);
4615 break;
4616 }
4617
4618 default:
4619 break;
4620 }
4621
4622 switch (Channel)
4623 {
4624 case TIM_CHANNEL_1:
4625 {
4626 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4627 {
4628 /* Enable the OCREF clear feature for Channel 1 */
4629 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4630 }
4631 else
4632 {
4633 /* Disable the OCREF clear feature for Channel 1 */
4634 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4635 }
4636 break;
4637 }
4638 case TIM_CHANNEL_2:
4639 {
4640 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4641 {
4642 /* Enable the OCREF clear feature for Channel 2 */
4643 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4644 }
4645 else
4646 {
4647 /* Disable the OCREF clear feature for Channel 2 */
4648 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4649 }
4650 break;
4651 }
4652 case TIM_CHANNEL_3:
4653 {
4654 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4655 {
4656 /* Enable the OCREF clear feature for Channel 3 */
4657 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4658 }
4659 else
4660 {
4661 /* Disable the OCREF clear feature for Channel 3 */
4662 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4663 }
4664 break;
4665 }
4666 case TIM_CHANNEL_4:
4667 {
4668 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4669 {
4670 /* Enable the OCREF clear feature for Channel 4 */
4671 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4672 }
4673 else
4674 {
4675 /* Disable the OCREF clear feature for Channel 4 */
4676 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4677 }
4678 break;
4679 }
4680 case TIM_CHANNEL_5:
4681 {
4682 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4683 {
4684 /* Enable the OCREF clear feature for Channel 5 */
4685 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4686 }
4687 else
4688 {
4689 /* Disable the OCREF clear feature for Channel 5 */
4690 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4691 }
4692 break;
4693 }
4694 case TIM_CHANNEL_6:
4695 {
4696 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4697 {
4698 /* Enable the OCREF clear feature for Channel 6 */
4699 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4700 }
4701 else
4702 {
4703 /* Disable the OCREF clear feature for Channel 6 */
4704 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4705 }
4706 break;
4707 }
4708 default:
4709 break;
4710 }
4711
4712 htim->State = HAL_TIM_STATE_READY;
4713
4714 __HAL_UNLOCK(htim);
4715
4716 return HAL_OK;
4717 }
4718
4719 /**
4720 * @brief Configures the clock source to be used
4721 * @param htim TIM handle
4722 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4723 * contains the clock source information for the TIM peripheral.
4724 * @retval HAL status
4725 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)4726 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
4727 {
4728 uint32_t tmpsmcr;
4729
4730 /* Process Locked */
4731 __HAL_LOCK(htim);
4732
4733 htim->State = HAL_TIM_STATE_BUSY;
4734
4735 /* Check the parameters */
4736 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4737
4738 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4739 tmpsmcr = htim->Instance->SMCR;
4740 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4741 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4742 htim->Instance->SMCR = tmpsmcr;
4743
4744 switch (sClockSourceConfig->ClockSource)
4745 {
4746 case TIM_CLOCKSOURCE_INTERNAL:
4747 {
4748 assert_param(IS_TIM_INSTANCE(htim->Instance));
4749 break;
4750 }
4751
4752 case TIM_CLOCKSOURCE_ETRMODE1:
4753 {
4754 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4755 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4756
4757 /* Check ETR input conditioning related parameters */
4758 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4759 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4760 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4761
4762 /* Configure the ETR Clock source */
4763 TIM_ETR_SetConfig(htim->Instance,
4764 sClockSourceConfig->ClockPrescaler,
4765 sClockSourceConfig->ClockPolarity,
4766 sClockSourceConfig->ClockFilter);
4767
4768 /* Select the External clock mode1 and the ETRF trigger */
4769 tmpsmcr = htim->Instance->SMCR;
4770 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4771 /* Write to TIMx SMCR */
4772 htim->Instance->SMCR = tmpsmcr;
4773 break;
4774 }
4775
4776 case TIM_CLOCKSOURCE_ETRMODE2:
4777 {
4778 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4779 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4780
4781 /* Check ETR input conditioning related parameters */
4782 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4783 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4784 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4785
4786 /* Configure the ETR Clock source */
4787 TIM_ETR_SetConfig(htim->Instance,
4788 sClockSourceConfig->ClockPrescaler,
4789 sClockSourceConfig->ClockPolarity,
4790 sClockSourceConfig->ClockFilter);
4791 /* Enable the External clock mode2 */
4792 htim->Instance->SMCR |= TIM_SMCR_ECE;
4793 break;
4794 }
4795
4796 case TIM_CLOCKSOURCE_TI1:
4797 {
4798 /* Check whether or not the timer instance supports external clock mode 1 */
4799 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4800
4801 /* Check TI1 input conditioning related parameters */
4802 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4803 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4804
4805 TIM_TI1_ConfigInputStage(htim->Instance,
4806 sClockSourceConfig->ClockPolarity,
4807 sClockSourceConfig->ClockFilter);
4808 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4809 break;
4810 }
4811
4812 case TIM_CLOCKSOURCE_TI2:
4813 {
4814 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4815 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4816
4817 /* Check TI2 input conditioning related parameters */
4818 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4819 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4820
4821 TIM_TI2_ConfigInputStage(htim->Instance,
4822 sClockSourceConfig->ClockPolarity,
4823 sClockSourceConfig->ClockFilter);
4824 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4825 break;
4826 }
4827
4828 case TIM_CLOCKSOURCE_TI1ED:
4829 {
4830 /* Check whether or not the timer instance supports external clock mode 1 */
4831 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4832
4833 /* Check TI1 input conditioning related parameters */
4834 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4835 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4836
4837 TIM_TI1_ConfigInputStage(htim->Instance,
4838 sClockSourceConfig->ClockPolarity,
4839 sClockSourceConfig->ClockFilter);
4840 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4841 break;
4842 }
4843
4844 case TIM_CLOCKSOURCE_ITR0:
4845 case TIM_CLOCKSOURCE_ITR1:
4846 case TIM_CLOCKSOURCE_ITR2:
4847 case TIM_CLOCKSOURCE_ITR3:
4848 case TIM_CLOCKSOURCE_ITR4:
4849 case TIM_CLOCKSOURCE_ITR5:
4850 case TIM_CLOCKSOURCE_ITR6:
4851 case TIM_CLOCKSOURCE_ITR7:
4852 case TIM_CLOCKSOURCE_ITR8:
4853 {
4854 /* Check whether or not the timer instance supports internal trigger input */
4855 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4856
4857 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
4858 break;
4859 }
4860
4861 default:
4862 break;
4863 }
4864 htim->State = HAL_TIM_STATE_READY;
4865
4866 __HAL_UNLOCK(htim);
4867
4868 return HAL_OK;
4869 }
4870
4871 /**
4872 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4873 * or a XOR combination between CH1_input, CH2_input & CH3_input
4874 * @param htim TIM handle.
4875 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4876 * output of a XOR gate.
4877 * This parameter can be one of the following values:
4878 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4879 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4880 * pins are connected to the TI1 input (XOR combination)
4881 * @retval HAL status
4882 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)4883 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4884 {
4885 uint32_t tmpcr2;
4886
4887 /* Check the parameters */
4888 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4889 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4890
4891 /* Get the TIMx CR2 register value */
4892 tmpcr2 = htim->Instance->CR2;
4893
4894 /* Reset the TI1 selection */
4895 tmpcr2 &= ~TIM_CR2_TI1S;
4896
4897 /* Set the TI1 selection */
4898 tmpcr2 |= TI1_Selection;
4899
4900 /* Write to TIMxCR2 */
4901 htim->Instance->CR2 = tmpcr2;
4902
4903 return HAL_OK;
4904 }
4905
4906 /**
4907 * @brief Configures the TIM in Slave mode
4908 * @param htim TIM handle.
4909 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4910 * contains the selected trigger (internal trigger input, filtered
4911 * timer input or external trigger input) and the Slave mode
4912 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4913 * @retval HAL status
4914 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4915 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
4916 {
4917 /* Check the parameters */
4918 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4919 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4920 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4921
4922 __HAL_LOCK(htim);
4923
4924 htim->State = HAL_TIM_STATE_BUSY;
4925
4926 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4927 {
4928 htim->State = HAL_TIM_STATE_READY;
4929 __HAL_UNLOCK(htim);
4930 return HAL_ERROR;
4931 }
4932
4933 /* Disable Trigger Interrupt */
4934 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4935
4936 /* Disable Trigger DMA request */
4937 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4938
4939 htim->State = HAL_TIM_STATE_READY;
4940
4941 __HAL_UNLOCK(htim);
4942
4943 return HAL_OK;
4944 }
4945
4946 /**
4947 * @brief Configures the TIM in Slave mode in interrupt mode
4948 * @param htim TIM handle.
4949 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4950 * contains the selected trigger (internal trigger input, filtered
4951 * timer input or external trigger input) and the Slave mode
4952 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4953 * @retval HAL status
4954 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4955 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
4956 TIM_SlaveConfigTypeDef *sSlaveConfig)
4957 {
4958 /* Check the parameters */
4959 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4960 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4961 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4962
4963 __HAL_LOCK(htim);
4964
4965 htim->State = HAL_TIM_STATE_BUSY;
4966
4967 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4968 {
4969 htim->State = HAL_TIM_STATE_READY;
4970 __HAL_UNLOCK(htim);
4971 return HAL_ERROR;
4972 }
4973
4974 /* Enable Trigger Interrupt */
4975 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4976
4977 /* Disable Trigger DMA request */
4978 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4979
4980 htim->State = HAL_TIM_STATE_READY;
4981
4982 __HAL_UNLOCK(htim);
4983
4984 return HAL_OK;
4985 }
4986
4987 /**
4988 * @brief Read the captured value from Capture Compare unit
4989 * @param htim TIM handle.
4990 * @param Channel TIM Channels to be enabled
4991 * This parameter can be one of the following values:
4992 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4993 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4994 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4995 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4996 * @retval Captured value
4997 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)4998 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4999 {
5000 uint32_t tmpreg = 0U;
5001
5002 switch (Channel)
5003 {
5004 case TIM_CHANNEL_1:
5005 {
5006 /* Check the parameters */
5007 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5008
5009 /* Return the capture 1 value */
5010 tmpreg = htim->Instance->CCR1;
5011
5012 break;
5013 }
5014 case TIM_CHANNEL_2:
5015 {
5016 /* Check the parameters */
5017 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5018
5019 /* Return the capture 2 value */
5020 tmpreg = htim->Instance->CCR2;
5021
5022 break;
5023 }
5024
5025 case TIM_CHANNEL_3:
5026 {
5027 /* Check the parameters */
5028 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5029
5030 /* Return the capture 3 value */
5031 tmpreg = htim->Instance->CCR3;
5032
5033 break;
5034 }
5035
5036 case TIM_CHANNEL_4:
5037 {
5038 /* Check the parameters */
5039 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5040
5041 /* Return the capture 4 value */
5042 tmpreg = htim->Instance->CCR4;
5043
5044 break;
5045 }
5046
5047 default:
5048 break;
5049 }
5050
5051 return tmpreg;
5052 }
5053
5054 /**
5055 * @}
5056 */
5057
5058 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5059 * @brief TIM Callbacks functions
5060 *
5061 @verbatim
5062 ==============================================================================
5063 ##### TIM Callbacks functions #####
5064 ==============================================================================
5065 [..]
5066 This section provides TIM callback functions:
5067 (+) TIM Period elapsed callback
5068 (+) TIM Output Compare callback
5069 (+) TIM Input capture callback
5070 (+) TIM Trigger callback
5071 (+) TIM Error callback
5072
5073 @endverbatim
5074 * @{
5075 */
5076
5077 /**
5078 * @brief Period elapsed callback in non-blocking mode
5079 * @param htim TIM handle
5080 * @retval None
5081 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5082 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5083 {
5084 /* Prevent unused argument(s) compilation warning */
5085 UNUSED(htim);
5086
5087 /* NOTE : This function should not be modified, when the callback is needed,
5088 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5089 */
5090 }
5091
5092 /**
5093 * @brief Period elapsed half complete callback in non-blocking mode
5094 * @param htim TIM handle
5095 * @retval None
5096 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5097 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5098 {
5099 /* Prevent unused argument(s) compilation warning */
5100 UNUSED(htim);
5101
5102 /* NOTE : This function should not be modified, when the callback is needed,
5103 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5104 */
5105 }
5106
5107 /**
5108 * @brief Output Compare callback in non-blocking mode
5109 * @param htim TIM OC handle
5110 * @retval None
5111 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5112 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5113 {
5114 /* Prevent unused argument(s) compilation warning */
5115 UNUSED(htim);
5116
5117 /* NOTE : This function should not be modified, when the callback is needed,
5118 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5119 */
5120 }
5121
5122 /**
5123 * @brief Input Capture callback in non-blocking mode
5124 * @param htim TIM IC handle
5125 * @retval None
5126 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5127 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5128 {
5129 /* Prevent unused argument(s) compilation warning */
5130 UNUSED(htim);
5131
5132 /* NOTE : This function should not be modified, when the callback is needed,
5133 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5134 */
5135 }
5136
5137 /**
5138 * @brief Input Capture half complete callback in non-blocking mode
5139 * @param htim TIM IC handle
5140 * @retval None
5141 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5142 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5143 {
5144 /* Prevent unused argument(s) compilation warning */
5145 UNUSED(htim);
5146
5147 /* NOTE : This function should not be modified, when the callback is needed,
5148 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5149 */
5150 }
5151
5152 /**
5153 * @brief PWM Pulse finished callback in non-blocking mode
5154 * @param htim TIM handle
5155 * @retval None
5156 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5157 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5158 {
5159 /* Prevent unused argument(s) compilation warning */
5160 UNUSED(htim);
5161
5162 /* NOTE : This function should not be modified, when the callback is needed,
5163 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5164 */
5165 }
5166
5167 /**
5168 * @brief PWM Pulse finished half complete callback in non-blocking mode
5169 * @param htim TIM handle
5170 * @retval None
5171 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5172 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5173 {
5174 /* Prevent unused argument(s) compilation warning */
5175 UNUSED(htim);
5176
5177 /* NOTE : This function should not be modified, when the callback is needed,
5178 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5179 */
5180 }
5181
5182 /**
5183 * @brief Hall Trigger detection callback in non-blocking mode
5184 * @param htim TIM handle
5185 * @retval None
5186 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5187 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5188 {
5189 /* Prevent unused argument(s) compilation warning */
5190 UNUSED(htim);
5191
5192 /* NOTE : This function should not be modified, when the callback is needed,
5193 the HAL_TIM_TriggerCallback could be implemented in the user file
5194 */
5195 }
5196
5197 /**
5198 * @brief Hall Trigger detection half complete callback in non-blocking mode
5199 * @param htim TIM handle
5200 * @retval None
5201 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5202 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5203 {
5204 /* Prevent unused argument(s) compilation warning */
5205 UNUSED(htim);
5206
5207 /* NOTE : This function should not be modified, when the callback is needed,
5208 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5209 */
5210 }
5211
5212 /**
5213 * @brief Timer error callback in non-blocking mode
5214 * @param htim TIM handle
5215 * @retval None
5216 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5217 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5218 {
5219 /* Prevent unused argument(s) compilation warning */
5220 UNUSED(htim);
5221
5222 /* NOTE : This function should not be modified, when the callback is needed,
5223 the HAL_TIM_ErrorCallback could be implemented in the user file
5224 */
5225 }
5226
5227 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5228 /**
5229 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5230 * @param htim tim handle
5231 * @param CallbackID ID of the callback to be registered
5232 * This parameter can be one of the following values:
5233 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5234 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5235 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5236 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5237 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5238 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5239 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5240 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5241 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5242 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5243 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5244 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5245 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5246 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5247 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5248 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5249 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5250 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5251 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5252 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5253 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5254 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5255 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5256 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5257 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5258 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5259 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5260 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5261 * @param pCallback pointer to the callback function
5262 * @retval status
5263 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5264 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5265 pTIM_CallbackTypeDef pCallback)
5266 {
5267 HAL_StatusTypeDef status = HAL_OK;
5268
5269 if (pCallback == NULL)
5270 {
5271 return HAL_ERROR;
5272 }
5273 /* Process locked */
5274 __HAL_LOCK(htim);
5275
5276 if (htim->State == HAL_TIM_STATE_READY)
5277 {
5278 switch (CallbackID)
5279 {
5280 case HAL_TIM_BASE_MSPINIT_CB_ID :
5281 htim->Base_MspInitCallback = pCallback;
5282 break;
5283
5284 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5285 htim->Base_MspDeInitCallback = pCallback;
5286 break;
5287
5288 case HAL_TIM_IC_MSPINIT_CB_ID :
5289 htim->IC_MspInitCallback = pCallback;
5290 break;
5291
5292 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5293 htim->IC_MspDeInitCallback = pCallback;
5294 break;
5295
5296 case HAL_TIM_OC_MSPINIT_CB_ID :
5297 htim->OC_MspInitCallback = pCallback;
5298 break;
5299
5300 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5301 htim->OC_MspDeInitCallback = pCallback;
5302 break;
5303
5304 case HAL_TIM_PWM_MSPINIT_CB_ID :
5305 htim->PWM_MspInitCallback = pCallback;
5306 break;
5307
5308 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5309 htim->PWM_MspDeInitCallback = pCallback;
5310 break;
5311
5312 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5313 htim->OnePulse_MspInitCallback = pCallback;
5314 break;
5315
5316 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5317 htim->OnePulse_MspDeInitCallback = pCallback;
5318 break;
5319
5320 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5321 htim->Encoder_MspInitCallback = pCallback;
5322 break;
5323
5324 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5325 htim->Encoder_MspDeInitCallback = pCallback;
5326 break;
5327
5328 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5329 htim->HallSensor_MspInitCallback = pCallback;
5330 break;
5331
5332 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5333 htim->HallSensor_MspDeInitCallback = pCallback;
5334 break;
5335
5336 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5337 htim->PeriodElapsedCallback = pCallback;
5338 break;
5339
5340 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5341 htim->PeriodElapsedHalfCpltCallback = pCallback;
5342 break;
5343
5344 case HAL_TIM_TRIGGER_CB_ID :
5345 htim->TriggerCallback = pCallback;
5346 break;
5347
5348 case HAL_TIM_TRIGGER_HALF_CB_ID :
5349 htim->TriggerHalfCpltCallback = pCallback;
5350 break;
5351
5352 case HAL_TIM_IC_CAPTURE_CB_ID :
5353 htim->IC_CaptureCallback = pCallback;
5354 break;
5355
5356 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5357 htim->IC_CaptureHalfCpltCallback = pCallback;
5358 break;
5359
5360 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5361 htim->OC_DelayElapsedCallback = pCallback;
5362 break;
5363
5364 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5365 htim->PWM_PulseFinishedCallback = pCallback;
5366 break;
5367
5368 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5369 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5370 break;
5371
5372 case HAL_TIM_ERROR_CB_ID :
5373 htim->ErrorCallback = pCallback;
5374 break;
5375
5376 case HAL_TIM_COMMUTATION_CB_ID :
5377 htim->CommutationCallback = pCallback;
5378 break;
5379
5380 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5381 htim->CommutationHalfCpltCallback = pCallback;
5382 break;
5383
5384 case HAL_TIM_BREAK_CB_ID :
5385 htim->BreakCallback = pCallback;
5386 break;
5387
5388 case HAL_TIM_BREAK2_CB_ID :
5389 htim->Break2Callback = pCallback;
5390 break;
5391
5392 default :
5393 /* Return error status */
5394 status = HAL_ERROR;
5395 break;
5396 }
5397 }
5398 else if (htim->State == HAL_TIM_STATE_RESET)
5399 {
5400 switch (CallbackID)
5401 {
5402 case HAL_TIM_BASE_MSPINIT_CB_ID :
5403 htim->Base_MspInitCallback = pCallback;
5404 break;
5405
5406 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5407 htim->Base_MspDeInitCallback = pCallback;
5408 break;
5409
5410 case HAL_TIM_IC_MSPINIT_CB_ID :
5411 htim->IC_MspInitCallback = pCallback;
5412 break;
5413
5414 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5415 htim->IC_MspDeInitCallback = pCallback;
5416 break;
5417
5418 case HAL_TIM_OC_MSPINIT_CB_ID :
5419 htim->OC_MspInitCallback = pCallback;
5420 break;
5421
5422 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5423 htim->OC_MspDeInitCallback = pCallback;
5424 break;
5425
5426 case HAL_TIM_PWM_MSPINIT_CB_ID :
5427 htim->PWM_MspInitCallback = pCallback;
5428 break;
5429
5430 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5431 htim->PWM_MspDeInitCallback = pCallback;
5432 break;
5433
5434 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5435 htim->OnePulse_MspInitCallback = pCallback;
5436 break;
5437
5438 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5439 htim->OnePulse_MspDeInitCallback = pCallback;
5440 break;
5441
5442 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5443 htim->Encoder_MspInitCallback = pCallback;
5444 break;
5445
5446 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5447 htim->Encoder_MspDeInitCallback = pCallback;
5448 break;
5449
5450 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5451 htim->HallSensor_MspInitCallback = pCallback;
5452 break;
5453
5454 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5455 htim->HallSensor_MspDeInitCallback = pCallback;
5456 break;
5457
5458 default :
5459 /* Return error status */
5460 status = HAL_ERROR;
5461 break;
5462 }
5463 }
5464 else
5465 {
5466 /* Return error status */
5467 status = HAL_ERROR;
5468 }
5469
5470 /* Release Lock */
5471 __HAL_UNLOCK(htim);
5472
5473 return status;
5474 }
5475
5476 /**
5477 * @brief Unregister a TIM callback
5478 * TIM callback is redirected to the weak predefined callback
5479 * @param htim tim handle
5480 * @param CallbackID ID of the callback to be unregistered
5481 * This parameter can be one of the following values:
5482 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5483 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5484 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5485 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5486 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5487 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5488 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5489 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5490 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5491 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5492 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5493 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5494 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5495 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5496 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5497 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5498 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5499 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5500 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5501 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5502 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5503 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5504 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5505 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5506 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5507 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5508 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5509 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5510 * @retval status
5511 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5512 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5513 {
5514 HAL_StatusTypeDef status = HAL_OK;
5515
5516 /* Process locked */
5517 __HAL_LOCK(htim);
5518
5519 if (htim->State == HAL_TIM_STATE_READY)
5520 {
5521 switch (CallbackID)
5522 {
5523 case HAL_TIM_BASE_MSPINIT_CB_ID :
5524 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5525 break;
5526
5527 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5528 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5529 break;
5530
5531 case HAL_TIM_IC_MSPINIT_CB_ID :
5532 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5533 break;
5534
5535 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5536 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5537 break;
5538
5539 case HAL_TIM_OC_MSPINIT_CB_ID :
5540 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5541 break;
5542
5543 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5544 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5545 break;
5546
5547 case HAL_TIM_PWM_MSPINIT_CB_ID :
5548 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5549 break;
5550
5551 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5552 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5553 break;
5554
5555 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5556 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5557 break;
5558
5559 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5560 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5561 break;
5562
5563 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5564 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5565 break;
5566
5567 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5568 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5569 break;
5570
5571 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5572 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5573 break;
5574
5575 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5576 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5577 break;
5578
5579 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5580 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5581 break;
5582
5583 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5584 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
5585 break;
5586
5587 case HAL_TIM_TRIGGER_CB_ID :
5588 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5589 break;
5590
5591 case HAL_TIM_TRIGGER_HALF_CB_ID :
5592 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
5593 break;
5594
5595 case HAL_TIM_IC_CAPTURE_CB_ID :
5596 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
5597 break;
5598
5599 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5600 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
5601 break;
5602
5603 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5604 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
5605 break;
5606
5607 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5608 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
5609 break;
5610
5611 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5612 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
5613 break;
5614
5615 case HAL_TIM_ERROR_CB_ID :
5616 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
5617 break;
5618
5619 case HAL_TIM_COMMUTATION_CB_ID :
5620 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
5621 break;
5622
5623 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5624 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
5625 break;
5626
5627 case HAL_TIM_BREAK_CB_ID :
5628 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
5629 break;
5630
5631 case HAL_TIM_BREAK2_CB_ID :
5632 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
5633 break;
5634
5635 default :
5636 /* Return error status */
5637 status = HAL_ERROR;
5638 break;
5639 }
5640 }
5641 else if (htim->State == HAL_TIM_STATE_RESET)
5642 {
5643 switch (CallbackID)
5644 {
5645 case HAL_TIM_BASE_MSPINIT_CB_ID :
5646 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5647 break;
5648
5649 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5650 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5651 break;
5652
5653 case HAL_TIM_IC_MSPINIT_CB_ID :
5654 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5655 break;
5656
5657 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5658 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5659 break;
5660
5661 case HAL_TIM_OC_MSPINIT_CB_ID :
5662 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5663 break;
5664
5665 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5666 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5667 break;
5668
5669 case HAL_TIM_PWM_MSPINIT_CB_ID :
5670 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5671 break;
5672
5673 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5674 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5675 break;
5676
5677 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5678 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5679 break;
5680
5681 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5682 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5683 break;
5684
5685 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5686 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5687 break;
5688
5689 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5690 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5691 break;
5692
5693 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5694 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5695 break;
5696
5697 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5698 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5699 break;
5700
5701 default :
5702 /* Return error status */
5703 status = HAL_ERROR;
5704 break;
5705 }
5706 }
5707 else
5708 {
5709 /* Return error status */
5710 status = HAL_ERROR;
5711 }
5712
5713 /* Release Lock */
5714 __HAL_UNLOCK(htim);
5715
5716 return status;
5717 }
5718 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5719
5720 /**
5721 * @}
5722 */
5723
5724 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5725 * @brief TIM Peripheral State functions
5726 *
5727 @verbatim
5728 ==============================================================================
5729 ##### Peripheral State functions #####
5730 ==============================================================================
5731 [..]
5732 This subsection permits to get in run-time the status of the peripheral
5733 and the data flow.
5734
5735 @endverbatim
5736 * @{
5737 */
5738
5739 /**
5740 * @brief Return the TIM Base handle state.
5741 * @param htim TIM Base handle
5742 * @retval HAL state
5743 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)5744 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
5745 {
5746 return htim->State;
5747 }
5748
5749 /**
5750 * @brief Return the TIM OC handle state.
5751 * @param htim TIM Output Compare handle
5752 * @retval HAL state
5753 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)5754 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
5755 {
5756 return htim->State;
5757 }
5758
5759 /**
5760 * @brief Return the TIM PWM handle state.
5761 * @param htim TIM handle
5762 * @retval HAL state
5763 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)5764 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
5765 {
5766 return htim->State;
5767 }
5768
5769 /**
5770 * @brief Return the TIM Input Capture handle state.
5771 * @param htim TIM IC handle
5772 * @retval HAL state
5773 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)5774 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
5775 {
5776 return htim->State;
5777 }
5778
5779 /**
5780 * @brief Return the TIM One Pulse Mode handle state.
5781 * @param htim TIM OPM handle
5782 * @retval HAL state
5783 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)5784 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
5785 {
5786 return htim->State;
5787 }
5788
5789 /**
5790 * @brief Return the TIM Encoder Mode handle state.
5791 * @param htim TIM Encoder Interface handle
5792 * @retval HAL state
5793 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)5794 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
5795 {
5796 return htim->State;
5797 }
5798
5799 /**
5800 * @}
5801 */
5802
5803 /**
5804 * @}
5805 */
5806
5807 /** @defgroup TIM_Private_Functions TIM Private Functions
5808 * @{
5809 */
5810
5811 /**
5812 * @brief TIM DMA error callback
5813 * @param hdma pointer to DMA handle.
5814 * @retval None
5815 */
TIM_DMAError(DMA_HandleTypeDef * hdma)5816 void TIM_DMAError(DMA_HandleTypeDef *hdma)
5817 {
5818 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5819
5820 htim->State = HAL_TIM_STATE_READY;
5821
5822 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5823 htim->ErrorCallback(htim);
5824 #else
5825 HAL_TIM_ErrorCallback(htim);
5826 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5827 }
5828
5829 /**
5830 * @brief TIM DMA Delay Pulse complete callback.
5831 * @param hdma pointer to DMA handle.
5832 * @retval None
5833 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)5834 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
5835 {
5836 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5837
5838 htim->State = HAL_TIM_STATE_READY;
5839
5840 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5841 {
5842 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5843 }
5844 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5845 {
5846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5847 }
5848 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5849 {
5850 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5851 }
5852 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5853 {
5854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5855 }
5856 else
5857 {
5858 /* nothing to do */
5859 }
5860
5861 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5862 htim->PWM_PulseFinishedCallback(htim);
5863 #else
5864 HAL_TIM_PWM_PulseFinishedCallback(htim);
5865 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5866
5867 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5868 }
5869
5870 /**
5871 * @brief TIM DMA Delay Pulse half complete callback.
5872 * @param hdma pointer to DMA handle.
5873 * @retval None
5874 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)5875 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
5876 {
5877 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5878
5879 htim->State = HAL_TIM_STATE_READY;
5880
5881 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5882 {
5883 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5884 }
5885 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5886 {
5887 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5888 }
5889 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5890 {
5891 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5892 }
5893 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5894 {
5895 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5896 }
5897 else
5898 {
5899 /* nothing to do */
5900 }
5901
5902 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5903 htim->PWM_PulseFinishedHalfCpltCallback(htim);
5904 #else
5905 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
5906 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5907
5908 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5909 }
5910
5911 /**
5912 * @brief TIM DMA Capture complete callback.
5913 * @param hdma pointer to DMA handle.
5914 * @retval None
5915 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)5916 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
5917 {
5918 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5919
5920 htim->State = HAL_TIM_STATE_READY;
5921
5922 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5923 {
5924 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5925 }
5926 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5927 {
5928 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5929 }
5930 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5931 {
5932 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5933 }
5934 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5935 {
5936 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5937 }
5938 else
5939 {
5940 /* nothing to do */
5941 }
5942
5943 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5944 htim->IC_CaptureCallback(htim);
5945 #else
5946 HAL_TIM_IC_CaptureCallback(htim);
5947 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5948
5949 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5950 }
5951
5952 /**
5953 * @brief TIM DMA Capture half complete callback.
5954 * @param hdma pointer to DMA handle.
5955 * @retval None
5956 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)5957 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
5958 {
5959 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5960
5961 htim->State = HAL_TIM_STATE_READY;
5962
5963 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5964 {
5965 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5966 }
5967 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5968 {
5969 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5970 }
5971 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5972 {
5973 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5974 }
5975 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5976 {
5977 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5978 }
5979 else
5980 {
5981 /* nothing to do */
5982 }
5983
5984 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5985 htim->IC_CaptureHalfCpltCallback(htim);
5986 #else
5987 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
5988 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5989
5990 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5991 }
5992
5993 /**
5994 * @brief TIM DMA Period Elapse complete callback.
5995 * @param hdma pointer to DMA handle.
5996 * @retval None
5997 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)5998 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
5999 {
6000 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6001
6002 htim->State = HAL_TIM_STATE_READY;
6003
6004 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6005 htim->PeriodElapsedCallback(htim);
6006 #else
6007 HAL_TIM_PeriodElapsedCallback(htim);
6008 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6009 }
6010
6011 /**
6012 * @brief TIM DMA Period Elapse half complete callback.
6013 * @param hdma pointer to DMA handle.
6014 * @retval None
6015 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6016 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6017 {
6018 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6019
6020 htim->State = HAL_TIM_STATE_READY;
6021
6022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6023 htim->PeriodElapsedHalfCpltCallback(htim);
6024 #else
6025 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6026 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6027 }
6028
6029 /**
6030 * @brief TIM DMA Trigger callback.
6031 * @param hdma pointer to DMA handle.
6032 * @retval None
6033 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6034 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6035 {
6036 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6037
6038 htim->State = HAL_TIM_STATE_READY;
6039
6040 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6041 htim->TriggerCallback(htim);
6042 #else
6043 HAL_TIM_TriggerCallback(htim);
6044 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6045 }
6046
6047 /**
6048 * @brief TIM DMA Trigger half complete callback.
6049 * @param hdma pointer to DMA handle.
6050 * @retval None
6051 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6052 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6053 {
6054 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6055
6056 htim->State = HAL_TIM_STATE_READY;
6057
6058 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6059 htim->TriggerHalfCpltCallback(htim);
6060 #else
6061 HAL_TIM_TriggerHalfCpltCallback(htim);
6062 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6063 }
6064
6065 /**
6066 * @brief Time Base configuration
6067 * @param TIMx TIM peripheral
6068 * @param Structure TIM Base configuration structure
6069 * @retval None
6070 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)6071 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
6072 {
6073 uint32_t tmpcr1;
6074 tmpcr1 = TIMx->CR1;
6075
6076 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6077 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6078 {
6079 /* Select the Counter Mode */
6080 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6081 tmpcr1 |= Structure->CounterMode;
6082 }
6083
6084 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6085 {
6086 /* Set the clock division */
6087 tmpcr1 &= ~TIM_CR1_CKD;
6088 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6089 }
6090
6091 /* Set the auto-reload preload */
6092 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6093
6094 TIMx->CR1 = tmpcr1;
6095
6096 /* Set the Autoreload value */
6097 TIMx->ARR = (uint32_t)Structure->Period ;
6098
6099 /* Set the Prescaler value */
6100 TIMx->PSC = Structure->Prescaler;
6101
6102 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6103 {
6104 /* Set the Repetition Counter value */
6105 TIMx->RCR = Structure->RepetitionCounter;
6106 }
6107
6108 /* Generate an update event to reload the Prescaler
6109 and the repetition counter (only for advanced timer) value immediately */
6110 TIMx->EGR = TIM_EGR_UG;
6111 }
6112
6113 /**
6114 * @brief Timer Output Compare 1 configuration
6115 * @param TIMx to select the TIM peripheral
6116 * @param OC_Config The ouput configuration structure
6117 * @retval None
6118 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6119 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6120 {
6121 uint32_t tmpccmrx;
6122 uint32_t tmpccer;
6123 uint32_t tmpcr2;
6124
6125 /* Disable the Channel 1: Reset the CC1E Bit */
6126 TIMx->CCER &= ~TIM_CCER_CC1E;
6127
6128 /* Get the TIMx CCER register value */
6129 tmpccer = TIMx->CCER;
6130 /* Get the TIMx CR2 register value */
6131 tmpcr2 = TIMx->CR2;
6132
6133 /* Get the TIMx CCMR1 register value */
6134 tmpccmrx = TIMx->CCMR1;
6135
6136 /* Reset the Output Compare Mode Bits */
6137 tmpccmrx &= ~TIM_CCMR1_OC1M;
6138 tmpccmrx &= ~TIM_CCMR1_CC1S;
6139 /* Select the Output Compare Mode */
6140 tmpccmrx |= OC_Config->OCMode;
6141
6142 /* Reset the Output Polarity level */
6143 tmpccer &= ~TIM_CCER_CC1P;
6144 /* Set the Output Compare Polarity */
6145 tmpccer |= OC_Config->OCPolarity;
6146
6147 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6148 {
6149 /* Check parameters */
6150 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6151
6152 /* Reset the Output N Polarity level */
6153 tmpccer &= ~TIM_CCER_CC1NP;
6154 /* Set the Output N Polarity */
6155 tmpccer |= OC_Config->OCNPolarity;
6156 /* Reset the Output N State */
6157 tmpccer &= ~TIM_CCER_CC1NE;
6158 }
6159
6160 if (IS_TIM_BREAK_INSTANCE(TIMx))
6161 {
6162 /* Check parameters */
6163 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6164 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6165
6166 /* Reset the Output Compare and Output Compare N IDLE State */
6167 tmpcr2 &= ~TIM_CR2_OIS1;
6168 tmpcr2 &= ~TIM_CR2_OIS1N;
6169 /* Set the Output Idle state */
6170 tmpcr2 |= OC_Config->OCIdleState;
6171 /* Set the Output N Idle state */
6172 tmpcr2 |= OC_Config->OCNIdleState;
6173 }
6174
6175 /* Write to TIMx CR2 */
6176 TIMx->CR2 = tmpcr2;
6177
6178 /* Write to TIMx CCMR1 */
6179 TIMx->CCMR1 = tmpccmrx;
6180
6181 /* Set the Capture Compare Register value */
6182 TIMx->CCR1 = OC_Config->Pulse;
6183
6184 /* Write to TIMx CCER */
6185 TIMx->CCER = tmpccer;
6186 }
6187
6188 /**
6189 * @brief Timer Output Compare 2 configuration
6190 * @param TIMx to select the TIM peripheral
6191 * @param OC_Config The ouput configuration structure
6192 * @retval None
6193 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6194 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6195 {
6196 uint32_t tmpccmrx;
6197 uint32_t tmpccer;
6198 uint32_t tmpcr2;
6199
6200 /* Disable the Channel 2: Reset the CC2E Bit */
6201 TIMx->CCER &= ~TIM_CCER_CC2E;
6202
6203 /* Get the TIMx CCER register value */
6204 tmpccer = TIMx->CCER;
6205 /* Get the TIMx CR2 register value */
6206 tmpcr2 = TIMx->CR2;
6207
6208 /* Get the TIMx CCMR1 register value */
6209 tmpccmrx = TIMx->CCMR1;
6210
6211 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6212 tmpccmrx &= ~TIM_CCMR1_OC2M;
6213 tmpccmrx &= ~TIM_CCMR1_CC2S;
6214
6215 /* Select the Output Compare Mode */
6216 tmpccmrx |= (OC_Config->OCMode << 8U);
6217
6218 /* Reset the Output Polarity level */
6219 tmpccer &= ~TIM_CCER_CC2P;
6220 /* Set the Output Compare Polarity */
6221 tmpccer |= (OC_Config->OCPolarity << 4U);
6222
6223 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6224 {
6225 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6226
6227 /* Reset the Output N Polarity level */
6228 tmpccer &= ~TIM_CCER_CC2NP;
6229 /* Set the Output N Polarity */
6230 tmpccer |= (OC_Config->OCNPolarity << 4U);
6231 /* Reset the Output N State */
6232 tmpccer &= ~TIM_CCER_CC2NE;
6233
6234 }
6235
6236 if (IS_TIM_BREAK_INSTANCE(TIMx))
6237 {
6238 /* Check parameters */
6239 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6240 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6241
6242 /* Reset the Output Compare and Output Compare N IDLE State */
6243 tmpcr2 &= ~TIM_CR2_OIS2;
6244 tmpcr2 &= ~TIM_CR2_OIS2N;
6245 /* Set the Output Idle state */
6246 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6247 /* Set the Output N Idle state */
6248 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6249 }
6250
6251 /* Write to TIMx CR2 */
6252 TIMx->CR2 = tmpcr2;
6253
6254 /* Write to TIMx CCMR1 */
6255 TIMx->CCMR1 = tmpccmrx;
6256
6257 /* Set the Capture Compare Register value */
6258 TIMx->CCR2 = OC_Config->Pulse;
6259
6260 /* Write to TIMx CCER */
6261 TIMx->CCER = tmpccer;
6262 }
6263
6264 /**
6265 * @brief Timer Output Compare 3 configuration
6266 * @param TIMx to select the TIM peripheral
6267 * @param OC_Config The ouput configuration structure
6268 * @retval None
6269 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6270 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6271 {
6272 uint32_t tmpccmrx;
6273 uint32_t tmpccer;
6274 uint32_t tmpcr2;
6275
6276 /* Disable the Channel 3: Reset the CC2E Bit */
6277 TIMx->CCER &= ~TIM_CCER_CC3E;
6278
6279 /* Get the TIMx CCER register value */
6280 tmpccer = TIMx->CCER;
6281 /* Get the TIMx CR2 register value */
6282 tmpcr2 = TIMx->CR2;
6283
6284 /* Get the TIMx CCMR2 register value */
6285 tmpccmrx = TIMx->CCMR2;
6286
6287 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6288 tmpccmrx &= ~TIM_CCMR2_OC3M;
6289 tmpccmrx &= ~TIM_CCMR2_CC3S;
6290 /* Select the Output Compare Mode */
6291 tmpccmrx |= OC_Config->OCMode;
6292
6293 /* Reset the Output Polarity level */
6294 tmpccer &= ~TIM_CCER_CC3P;
6295 /* Set the Output Compare Polarity */
6296 tmpccer |= (OC_Config->OCPolarity << 8U);
6297
6298 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6299 {
6300 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6301
6302 /* Reset the Output N Polarity level */
6303 tmpccer &= ~TIM_CCER_CC3NP;
6304 /* Set the Output N Polarity */
6305 tmpccer |= (OC_Config->OCNPolarity << 8U);
6306 /* Reset the Output N State */
6307 tmpccer &= ~TIM_CCER_CC3NE;
6308 }
6309
6310 if (IS_TIM_BREAK_INSTANCE(TIMx))
6311 {
6312 /* Check parameters */
6313 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6314 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6315
6316 /* Reset the Output Compare and Output Compare N IDLE State */
6317 tmpcr2 &= ~TIM_CR2_OIS3;
6318 tmpcr2 &= ~TIM_CR2_OIS3N;
6319 /* Set the Output Idle state */
6320 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6321 /* Set the Output N Idle state */
6322 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6323 }
6324
6325 /* Write to TIMx CR2 */
6326 TIMx->CR2 = tmpcr2;
6327
6328 /* Write to TIMx CCMR2 */
6329 TIMx->CCMR2 = tmpccmrx;
6330
6331 /* Set the Capture Compare Register value */
6332 TIMx->CCR3 = OC_Config->Pulse;
6333
6334 /* Write to TIMx CCER */
6335 TIMx->CCER = tmpccer;
6336 }
6337
6338 /**
6339 * @brief Timer Output Compare 4 configuration
6340 * @param TIMx to select the TIM peripheral
6341 * @param OC_Config The ouput configuration structure
6342 * @retval None
6343 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6344 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6345 {
6346 uint32_t tmpccmrx;
6347 uint32_t tmpccer;
6348 uint32_t tmpcr2;
6349
6350 /* Disable the Channel 4: Reset the CC4E Bit */
6351 TIMx->CCER &= ~TIM_CCER_CC4E;
6352
6353 /* Get the TIMx CCER register value */
6354 tmpccer = TIMx->CCER;
6355 /* Get the TIMx CR2 register value */
6356 tmpcr2 = TIMx->CR2;
6357
6358 /* Get the TIMx CCMR2 register value */
6359 tmpccmrx = TIMx->CCMR2;
6360
6361 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6362 tmpccmrx &= ~TIM_CCMR2_OC4M;
6363 tmpccmrx &= ~TIM_CCMR2_CC4S;
6364
6365 /* Select the Output Compare Mode */
6366 tmpccmrx |= (OC_Config->OCMode << 8U);
6367
6368 /* Reset the Output Polarity level */
6369 tmpccer &= ~TIM_CCER_CC4P;
6370 /* Set the Output Compare Polarity */
6371 tmpccer |= (OC_Config->OCPolarity << 12U);
6372
6373 if (IS_TIM_BREAK_INSTANCE(TIMx))
6374 {
6375 /* Check parameters */
6376 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6377
6378 /* Reset the Output Compare IDLE State */
6379 tmpcr2 &= ~TIM_CR2_OIS4;
6380
6381 /* Set the Output Idle state */
6382 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6383 }
6384
6385 /* Write to TIMx CR2 */
6386 TIMx->CR2 = tmpcr2;
6387
6388 /* Write to TIMx CCMR2 */
6389 TIMx->CCMR2 = tmpccmrx;
6390
6391 /* Set the Capture Compare Register value */
6392 TIMx->CCR4 = OC_Config->Pulse;
6393
6394 /* Write to TIMx CCER */
6395 TIMx->CCER = tmpccer;
6396 }
6397
6398 /**
6399 * @brief Timer Output Compare 5 configuration
6400 * @param TIMx to select the TIM peripheral
6401 * @param OC_Config The ouput configuration structure
6402 * @retval None
6403 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6404 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
6405 TIM_OC_InitTypeDef *OC_Config)
6406 {
6407 uint32_t tmpccmrx;
6408 uint32_t tmpccer;
6409 uint32_t tmpcr2;
6410
6411 /* Disable the output: Reset the CCxE Bit */
6412 TIMx->CCER &= ~TIM_CCER_CC5E;
6413
6414 /* Get the TIMx CCER register value */
6415 tmpccer = TIMx->CCER;
6416 /* Get the TIMx CR2 register value */
6417 tmpcr2 = TIMx->CR2;
6418 /* Get the TIMx CCMR1 register value */
6419 tmpccmrx = TIMx->CCMR3;
6420
6421 /* Reset the Output Compare Mode Bits */
6422 tmpccmrx &= ~(TIM_CCMR3_OC5M);
6423 /* Select the Output Compare Mode */
6424 tmpccmrx |= OC_Config->OCMode;
6425
6426 /* Reset the Output Polarity level */
6427 tmpccer &= ~TIM_CCER_CC5P;
6428 /* Set the Output Compare Polarity */
6429 tmpccer |= (OC_Config->OCPolarity << 16U);
6430
6431 if (IS_TIM_BREAK_INSTANCE(TIMx))
6432 {
6433 /* Reset the Output Compare IDLE State */
6434 tmpcr2 &= ~TIM_CR2_OIS5;
6435 /* Set the Output Idle state */
6436 tmpcr2 |= (OC_Config->OCIdleState << 8U);
6437 }
6438 /* Write to TIMx CR2 */
6439 TIMx->CR2 = tmpcr2;
6440
6441 /* Write to TIMx CCMR3 */
6442 TIMx->CCMR3 = tmpccmrx;
6443
6444 /* Set the Capture Compare Register value */
6445 TIMx->CCR5 = OC_Config->Pulse;
6446
6447 /* Write to TIMx CCER */
6448 TIMx->CCER = tmpccer;
6449 }
6450
6451 /**
6452 * @brief Timer Output Compare 6 configuration
6453 * @param TIMx to select the TIM peripheral
6454 * @param OC_Config The ouput configuration structure
6455 * @retval None
6456 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6457 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
6458 TIM_OC_InitTypeDef *OC_Config)
6459 {
6460 uint32_t tmpccmrx;
6461 uint32_t tmpccer;
6462 uint32_t tmpcr2;
6463
6464 /* Disable the output: Reset the CCxE Bit */
6465 TIMx->CCER &= ~TIM_CCER_CC6E;
6466
6467 /* Get the TIMx CCER register value */
6468 tmpccer = TIMx->CCER;
6469 /* Get the TIMx CR2 register value */
6470 tmpcr2 = TIMx->CR2;
6471 /* Get the TIMx CCMR1 register value */
6472 tmpccmrx = TIMx->CCMR3;
6473
6474 /* Reset the Output Compare Mode Bits */
6475 tmpccmrx &= ~(TIM_CCMR3_OC6M);
6476 /* Select the Output Compare Mode */
6477 tmpccmrx |= (OC_Config->OCMode << 8U);
6478
6479 /* Reset the Output Polarity level */
6480 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
6481 /* Set the Output Compare Polarity */
6482 tmpccer |= (OC_Config->OCPolarity << 20U);
6483
6484 if (IS_TIM_BREAK_INSTANCE(TIMx))
6485 {
6486 /* Reset the Output Compare IDLE State */
6487 tmpcr2 &= ~TIM_CR2_OIS6;
6488 /* Set the Output Idle state */
6489 tmpcr2 |= (OC_Config->OCIdleState << 10U);
6490 }
6491
6492 /* Write to TIMx CR2 */
6493 TIMx->CR2 = tmpcr2;
6494
6495 /* Write to TIMx CCMR3 */
6496 TIMx->CCMR3 = tmpccmrx;
6497
6498 /* Set the Capture Compare Register value */
6499 TIMx->CCR6 = OC_Config->Pulse;
6500
6501 /* Write to TIMx CCER */
6502 TIMx->CCER = tmpccer;
6503 }
6504
6505 /**
6506 * @brief Slave Timer configuration function
6507 * @param htim TIM handle
6508 * @param sSlaveConfig Slave timer configuration
6509 * @retval None
6510 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6511 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6512 TIM_SlaveConfigTypeDef *sSlaveConfig)
6513 {
6514 uint32_t tmpsmcr;
6515 uint32_t tmpccmr1;
6516 uint32_t tmpccer;
6517
6518 /* Get the TIMx SMCR register value */
6519 tmpsmcr = htim->Instance->SMCR;
6520
6521 /* Reset the Trigger Selection Bits */
6522 tmpsmcr &= ~TIM_SMCR_TS;
6523 /* Set the Input Trigger source */
6524 tmpsmcr |= sSlaveConfig->InputTrigger;
6525
6526 /* Reset the slave mode Bits */
6527 tmpsmcr &= ~TIM_SMCR_SMS;
6528 /* Set the slave mode */
6529 tmpsmcr |= sSlaveConfig->SlaveMode;
6530
6531 /* Write to TIMx SMCR */
6532 htim->Instance->SMCR = tmpsmcr;
6533
6534 /* Configure the trigger prescaler, filter, and polarity */
6535 switch (sSlaveConfig->InputTrigger)
6536 {
6537 case TIM_TS_ETRF:
6538 {
6539 /* Check the parameters */
6540 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6541 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6542 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6543 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6544 /* Configure the ETR Trigger source */
6545 TIM_ETR_SetConfig(htim->Instance,
6546 sSlaveConfig->TriggerPrescaler,
6547 sSlaveConfig->TriggerPolarity,
6548 sSlaveConfig->TriggerFilter);
6549 break;
6550 }
6551
6552 case TIM_TS_TI1F_ED:
6553 {
6554 /* Check the parameters */
6555 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6556 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6557
6558 if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6559 {
6560 return HAL_ERROR;
6561 }
6562
6563 /* Disable the Channel 1: Reset the CC1E Bit */
6564 tmpccer = htim->Instance->CCER;
6565 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6566 tmpccmr1 = htim->Instance->CCMR1;
6567
6568 /* Set the filter */
6569 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6570 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6571
6572 /* Write to TIMx CCMR1 and CCER registers */
6573 htim->Instance->CCMR1 = tmpccmr1;
6574 htim->Instance->CCER = tmpccer;
6575 break;
6576 }
6577
6578 case TIM_TS_TI1FP1:
6579 {
6580 /* Check the parameters */
6581 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6582 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6583 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6584
6585 /* Configure TI1 Filter and Polarity */
6586 TIM_TI1_ConfigInputStage(htim->Instance,
6587 sSlaveConfig->TriggerPolarity,
6588 sSlaveConfig->TriggerFilter);
6589 break;
6590 }
6591
6592 case TIM_TS_TI2FP2:
6593 {
6594 /* Check the parameters */
6595 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6596 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6597 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6598
6599 /* Configure TI2 Filter and Polarity */
6600 TIM_TI2_ConfigInputStage(htim->Instance,
6601 sSlaveConfig->TriggerPolarity,
6602 sSlaveConfig->TriggerFilter);
6603 break;
6604 }
6605
6606 case TIM_TS_ITR0:
6607 case TIM_TS_ITR1:
6608 case TIM_TS_ITR2:
6609 case TIM_TS_ITR3:
6610 case TIM_TS_ITR4:
6611 case TIM_TS_ITR5:
6612 case TIM_TS_ITR6:
6613 case TIM_TS_ITR7:
6614 case TIM_TS_ITR8:
6615 {
6616 /* Check the parameter */
6617 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6618 break;
6619 }
6620
6621 default:
6622 break;
6623 }
6624 return HAL_OK;
6625 }
6626
6627 /**
6628 * @brief Configure the TI1 as Input.
6629 * @param TIMx to select the TIM peripheral.
6630 * @param TIM_ICPolarity The Input Polarity.
6631 * This parameter can be one of the following values:
6632 * @arg TIM_ICPOLARITY_RISING
6633 * @arg TIM_ICPOLARITY_FALLING
6634 * @arg TIM_ICPOLARITY_BOTHEDGE
6635 * @param TIM_ICSelection specifies the input to be used.
6636 * This parameter can be one of the following values:
6637 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6638 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6639 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6640 * @param TIM_ICFilter Specifies the Input Capture Filter.
6641 * This parameter must be a value between 0x00 and 0x0F.
6642 * @retval None
6643 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6644 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6645 * protected against un-initialized filter and polarity values.
6646 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6647 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6648 uint32_t TIM_ICFilter)
6649 {
6650 uint32_t tmpccmr1;
6651 uint32_t tmpccer;
6652
6653 /* Disable the Channel 1: Reset the CC1E Bit */
6654 TIMx->CCER &= ~TIM_CCER_CC1E;
6655 tmpccmr1 = TIMx->CCMR1;
6656 tmpccer = TIMx->CCER;
6657
6658 /* Select the Input */
6659 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6660 {
6661 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6662 tmpccmr1 |= TIM_ICSelection;
6663 }
6664 else
6665 {
6666 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6667 }
6668
6669 /* Set the filter */
6670 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6671 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6672
6673 /* Select the Polarity and set the CC1E Bit */
6674 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6675 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6676
6677 /* Write to TIMx CCMR1 and CCER registers */
6678 TIMx->CCMR1 = tmpccmr1;
6679 TIMx->CCER = tmpccer;
6680 }
6681
6682 /**
6683 * @brief Configure the Polarity and Filter for TI1.
6684 * @param TIMx to select the TIM peripheral.
6685 * @param TIM_ICPolarity The Input Polarity.
6686 * This parameter can be one of the following values:
6687 * @arg TIM_ICPOLARITY_RISING
6688 * @arg TIM_ICPOLARITY_FALLING
6689 * @arg TIM_ICPOLARITY_BOTHEDGE
6690 * @param TIM_ICFilter Specifies the Input Capture Filter.
6691 * This parameter must be a value between 0x00 and 0x0F.
6692 * @retval None
6693 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6694 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6695 {
6696 uint32_t tmpccmr1;
6697 uint32_t tmpccer;
6698
6699 /* Disable the Channel 1: Reset the CC1E Bit */
6700 tmpccer = TIMx->CCER;
6701 TIMx->CCER &= ~TIM_CCER_CC1E;
6702 tmpccmr1 = TIMx->CCMR1;
6703
6704 /* Set the filter */
6705 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6706 tmpccmr1 |= (TIM_ICFilter << 4U);
6707
6708 /* Select the Polarity and set the CC1E Bit */
6709 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6710 tmpccer |= TIM_ICPolarity;
6711
6712 /* Write to TIMx CCMR1 and CCER registers */
6713 TIMx->CCMR1 = tmpccmr1;
6714 TIMx->CCER = tmpccer;
6715 }
6716
6717 /**
6718 * @brief Configure the TI2 as Input.
6719 * @param TIMx to select the TIM peripheral
6720 * @param TIM_ICPolarity The Input Polarity.
6721 * This parameter can be one of the following values:
6722 * @arg TIM_ICPOLARITY_RISING
6723 * @arg TIM_ICPOLARITY_FALLING
6724 * @arg TIM_ICPOLARITY_BOTHEDGE
6725 * @param TIM_ICSelection specifies the input to be used.
6726 * This parameter can be one of the following values:
6727 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6728 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6729 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6730 * @param TIM_ICFilter Specifies the Input Capture Filter.
6731 * This parameter must be a value between 0x00 and 0x0F.
6732 * @retval None
6733 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6734 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6735 * protected against un-initialized filter and polarity values.
6736 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6737 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6738 uint32_t TIM_ICFilter)
6739 {
6740 uint32_t tmpccmr1;
6741 uint32_t tmpccer;
6742
6743 /* Disable the Channel 2: Reset the CC2E Bit */
6744 TIMx->CCER &= ~TIM_CCER_CC2E;
6745 tmpccmr1 = TIMx->CCMR1;
6746 tmpccer = TIMx->CCER;
6747
6748 /* Select the Input */
6749 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6750 tmpccmr1 |= (TIM_ICSelection << 8U);
6751
6752 /* Set the filter */
6753 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6754 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6755
6756 /* Select the Polarity and set the CC2E Bit */
6757 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6758 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6759
6760 /* Write to TIMx CCMR1 and CCER registers */
6761 TIMx->CCMR1 = tmpccmr1 ;
6762 TIMx->CCER = tmpccer;
6763 }
6764
6765 /**
6766 * @brief Configure the Polarity and Filter for TI2.
6767 * @param TIMx to select the TIM peripheral.
6768 * @param TIM_ICPolarity The Input Polarity.
6769 * This parameter can be one of the following values:
6770 * @arg TIM_ICPOLARITY_RISING
6771 * @arg TIM_ICPOLARITY_FALLING
6772 * @arg TIM_ICPOLARITY_BOTHEDGE
6773 * @param TIM_ICFilter Specifies the Input Capture Filter.
6774 * This parameter must be a value between 0x00 and 0x0F.
6775 * @retval None
6776 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6777 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6778 {
6779 uint32_t tmpccmr1;
6780 uint32_t tmpccer;
6781
6782 /* Disable the Channel 2: Reset the CC2E Bit */
6783 TIMx->CCER &= ~TIM_CCER_CC2E;
6784 tmpccmr1 = TIMx->CCMR1;
6785 tmpccer = TIMx->CCER;
6786
6787 /* Set the filter */
6788 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6789 tmpccmr1 |= (TIM_ICFilter << 12U);
6790
6791 /* Select the Polarity and set the CC2E Bit */
6792 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6793 tmpccer |= (TIM_ICPolarity << 4U);
6794
6795 /* Write to TIMx CCMR1 and CCER registers */
6796 TIMx->CCMR1 = tmpccmr1 ;
6797 TIMx->CCER = tmpccer;
6798 }
6799
6800 /**
6801 * @brief Configure the TI3 as Input.
6802 * @param TIMx to select the TIM peripheral
6803 * @param TIM_ICPolarity The Input Polarity.
6804 * This parameter can be one of the following values:
6805 * @arg TIM_ICPOLARITY_RISING
6806 * @arg TIM_ICPOLARITY_FALLING
6807 * @arg TIM_ICPOLARITY_BOTHEDGE
6808 * @param TIM_ICSelection specifies the input to be used.
6809 * This parameter can be one of the following values:
6810 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6811 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6812 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6813 * @param TIM_ICFilter Specifies the Input Capture Filter.
6814 * This parameter must be a value between 0x00 and 0x0F.
6815 * @retval None
6816 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6817 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6818 * protected against un-initialized filter and polarity values.
6819 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6820 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6821 uint32_t TIM_ICFilter)
6822 {
6823 uint32_t tmpccmr2;
6824 uint32_t tmpccer;
6825
6826 /* Disable the Channel 3: Reset the CC3E Bit */
6827 TIMx->CCER &= ~TIM_CCER_CC3E;
6828 tmpccmr2 = TIMx->CCMR2;
6829 tmpccer = TIMx->CCER;
6830
6831 /* Select the Input */
6832 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6833 tmpccmr2 |= TIM_ICSelection;
6834
6835 /* Set the filter */
6836 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6837 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6838
6839 /* Select the Polarity and set the CC3E Bit */
6840 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6841 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6842
6843 /* Write to TIMx CCMR2 and CCER registers */
6844 TIMx->CCMR2 = tmpccmr2;
6845 TIMx->CCER = tmpccer;
6846 }
6847
6848 /**
6849 * @brief Configure the TI4 as Input.
6850 * @param TIMx to select the TIM peripheral
6851 * @param TIM_ICPolarity The Input Polarity.
6852 * This parameter can be one of the following values:
6853 * @arg TIM_ICPOLARITY_RISING
6854 * @arg TIM_ICPOLARITY_FALLING
6855 * @arg TIM_ICPOLARITY_BOTHEDGE
6856 * @param TIM_ICSelection specifies the input to be used.
6857 * This parameter can be one of the following values:
6858 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
6859 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
6860 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
6861 * @param TIM_ICFilter Specifies the Input Capture Filter.
6862 * This parameter must be a value between 0x00 and 0x0F.
6863 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
6864 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6865 * protected against un-initialized filter and polarity values.
6866 * @retval None
6867 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6868 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6869 uint32_t TIM_ICFilter)
6870 {
6871 uint32_t tmpccmr2;
6872 uint32_t tmpccer;
6873
6874 /* Disable the Channel 4: Reset the CC4E Bit */
6875 TIMx->CCER &= ~TIM_CCER_CC4E;
6876 tmpccmr2 = TIMx->CCMR2;
6877 tmpccer = TIMx->CCER;
6878
6879 /* Select the Input */
6880 tmpccmr2 &= ~TIM_CCMR2_CC4S;
6881 tmpccmr2 |= (TIM_ICSelection << 8U);
6882
6883 /* Set the filter */
6884 tmpccmr2 &= ~TIM_CCMR2_IC4F;
6885 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
6886
6887 /* Select the Polarity and set the CC4E Bit */
6888 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
6889 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
6890
6891 /* Write to TIMx CCMR2 and CCER registers */
6892 TIMx->CCMR2 = tmpccmr2;
6893 TIMx->CCER = tmpccer ;
6894 }
6895
6896 /**
6897 * @brief Selects the Input Trigger source
6898 * @param TIMx to select the TIM peripheral
6899 * @param InputTriggerSource The Input Trigger source.
6900 * This parameter can be one of the following values:
6901 * @arg TIM_TS_ITR0: Internal Trigger 0
6902 * @arg TIM_TS_ITR1: Internal Trigger 1
6903 * @arg TIM_TS_ITR2: Internal Trigger 2
6904 * @arg TIM_TS_ITR3: Internal Trigger 3
6905 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
6906 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
6907 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
6908 * @arg TIM_TS_ETRF: External Trigger input
6909 * @arg TIM_TS_ITR4: Internal Trigger 4
6910 * @arg TIM_TS_ITR5: Internal Trigger 5
6911 * @arg TIM_TS_ITR6: Internal Trigger 6
6912 * @arg TIM_TS_ITR7: Internal Trigger 7
6913 * @arg TIM_TS_ITR8: Internal Trigger 8
6914 * @retval None
6915 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)6916 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
6917 {
6918 uint32_t tmpsmcr;
6919
6920 /* Get the TIMx SMCR register value */
6921 tmpsmcr = TIMx->SMCR;
6922 /* Reset the TS Bits */
6923 tmpsmcr &= ~TIM_SMCR_TS;
6924 /* Set the Input Trigger source and the slave mode*/
6925 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
6926 /* Write to TIMx SMCR */
6927 TIMx->SMCR = tmpsmcr;
6928 }
6929 /**
6930 * @brief Configures the TIMx External Trigger (ETR).
6931 * @param TIMx to select the TIM peripheral
6932 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
6933 * This parameter can be one of the following values:
6934 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
6935 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
6936 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
6937 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
6938 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
6939 * This parameter can be one of the following values:
6940 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
6941 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
6942 * @param ExtTRGFilter External Trigger Filter.
6943 * This parameter must be a value between 0x00 and 0x0F
6944 * @retval None
6945 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)6946 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
6947 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
6948 {
6949 uint32_t tmpsmcr;
6950
6951 tmpsmcr = TIMx->SMCR;
6952
6953 /* Reset the ETR Bits */
6954 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
6955
6956 /* Set the Prescaler, the Filter value and the Polarity */
6957 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
6958
6959 /* Write to TIMx SMCR */
6960 TIMx->SMCR = tmpsmcr;
6961 }
6962
6963 /**
6964 * @brief Enables or disables the TIM Capture Compare Channel x.
6965 * @param TIMx to select the TIM peripheral
6966 * @param Channel specifies the TIM Channel
6967 * This parameter can be one of the following values:
6968 * @arg TIM_CHANNEL_1: TIM Channel 1
6969 * @arg TIM_CHANNEL_2: TIM Channel 2
6970 * @arg TIM_CHANNEL_3: TIM Channel 3
6971 * @arg TIM_CHANNEL_4: TIM Channel 4
6972 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
6973 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
6974 * @param ChannelState specifies the TIM Channel CCxE bit new state.
6975 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
6976 * @retval None
6977 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)6978 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
6979 {
6980 uint32_t tmp;
6981
6982 /* Check the parameters */
6983 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
6984 assert_param(IS_TIM_CHANNELS(Channel));
6985
6986 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
6987
6988 /* Reset the CCxE Bit */
6989 TIMx->CCER &= ~tmp;
6990
6991 /* Set or reset the CCxE Bit */
6992 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
6993 }
6994
6995 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6996 /**
6997 * @brief Reset interrupt callbacks to the legacy weak callbacks.
6998 * @param htim pointer to a TIM_HandleTypeDef structure that contains
6999 * the configuration information for TIM module.
7000 * @retval None
7001 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7002 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7003 {
7004 /* Reset the TIM callback to the legacy weak callbacks */
7005 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
7006 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
7007 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
7008 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
7009 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
7010 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
7011 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
7012 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
7013 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
7014 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
7015 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
7016 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
7017 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
7018 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
7019 }
7020 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7021
7022 /**
7023 * @}
7024 */
7025
7026 #endif /* HAL_TIM_MODULE_ENABLED */
7027 /**
7028 * @}
7029 */
7030
7031 /**
7032 * @}
7033 */
7034 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7035