1 /** 2 ****************************************************************************** 3 * @file stm32f10x_rcc.h 4 * @author MCD Application Team 5 * @version V3.1.2 6 * @date 09/28/2009 7 * @brief This file contains all the functions prototypes for the RCC firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __STM32F10x_RCC_H 24 #define __STM32F10x_RCC_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f10x.h" 32 33 /** @addtogroup STM32F10x_StdPeriph_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCC 38 * @{ 39 */ 40 41 /** @defgroup RCC_Exported_Types 42 * @{ 43 */ 44 45 typedef struct 46 { 47 uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ 48 uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ 49 uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ 50 uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ 51 uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ 52 }RCC_ClocksTypeDef; 53 54 /** 55 * @} 56 */ 57 58 /** @defgroup RCC_Exported_Constants 59 * @{ 60 */ 61 62 /** @defgroup HSE_configuration 63 * @{ 64 */ 65 66 #define RCC_HSE_OFF ((uint32_t)0x00000000) 67 #define RCC_HSE_ON ((uint32_t)0x00010000) 68 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 69 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 70 ((HSE) == RCC_HSE_Bypass)) 71 72 /** 73 * @} 74 */ 75 76 /** @defgroup PLL_entry_clock_source 77 * @{ 78 */ 79 80 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) 81 82 #ifndef STM32F10X_CL 83 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 84 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 85 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 86 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 87 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 88 #else 89 #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) 90 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 91 ((SOURCE) == RCC_PLLSource_PREDIV1)) 92 #endif /* STM32F10X_CL */ 93 94 /** 95 * @} 96 */ 97 98 /** @defgroup PLL_multiplication_factor 99 * @{ 100 */ 101 #ifndef STM32F10X_CL 102 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 103 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 104 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 105 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 106 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 107 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 108 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 109 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 110 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 111 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 112 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 113 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 114 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 115 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 116 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 117 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 118 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 119 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 120 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 121 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 122 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 123 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 124 ((MUL) == RCC_PLLMul_16)) 125 126 #else 127 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 128 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 129 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 130 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 131 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 132 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 133 #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) 134 135 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 136 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 137 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 138 ((MUL) == RCC_PLLMul_6_5)) 139 #endif /* STM32F10X_CL */ 140 /** 141 * @} 142 */ 143 144 #ifdef STM32F10X_CL 145 /** @defgroup PREDIV1_division_factor 146 * @{ 147 */ 148 #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) 149 #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) 150 #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) 151 #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) 152 #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) 153 #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) 154 #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) 155 #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) 156 #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) 157 #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) 158 #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) 159 #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) 160 #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) 161 #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) 162 #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) 163 #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) 164 165 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ 166 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ 167 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ 168 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ 169 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ 170 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ 171 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ 172 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) 173 /** 174 * @} 175 */ 176 177 178 /** @defgroup PREDIV1_clock_source 179 * @{ 180 */ 181 /* PREDIV1 clock source (only for STM32 connectivity line devices) */ 182 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) 183 #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) 184 185 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ 186 ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 187 /** 188 * @} 189 */ 190 191 192 /** @defgroup PREDIV2_division_factor 193 * @{ 194 */ 195 196 #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) 197 #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) 198 #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) 199 #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) 200 #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) 201 #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) 202 #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) 203 #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) 204 #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) 205 #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) 206 #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) 207 #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) 208 #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) 209 #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) 210 #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) 211 #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) 212 213 #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ 214 ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ 215 ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ 216 ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ 217 ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ 218 ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ 219 ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ 220 ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) 221 /** 222 * @} 223 */ 224 225 226 /** @defgroup PLL2_multiplication_factor 227 * @{ 228 */ 229 230 #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) 231 #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) 232 #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) 233 #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) 234 #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) 235 #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) 236 #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) 237 #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) 238 #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) 239 240 #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ 241 ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ 242 ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ 243 ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ 244 ((MUL) == RCC_PLL2Mul_20)) 245 /** 246 * @} 247 */ 248 249 250 /** @defgroup PLL3_multiplication_factor 251 * @{ 252 */ 253 254 #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) 255 #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) 256 #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) 257 #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) 258 #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) 259 #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) 260 #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) 261 #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) 262 #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) 263 264 #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ 265 ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ 266 ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ 267 ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ 268 ((MUL) == RCC_PLL3Mul_20)) 269 /** 270 * @} 271 */ 272 273 #endif /* STM32F10X_CL */ 274 275 276 /** @defgroup System_clock_source 277 * @{ 278 */ 279 280 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 281 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 282 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 283 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 284 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 285 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 286 /** 287 * @} 288 */ 289 290 /** @defgroup AHB_clock_source 291 * @{ 292 */ 293 294 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 295 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 296 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 297 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 298 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 299 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 300 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 301 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 302 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 303 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 304 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 305 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 306 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 307 ((HCLK) == RCC_SYSCLK_Div512)) 308 /** 309 * @} 310 */ 311 312 /** @defgroup APB1_APB2_clock_source 313 * @{ 314 */ 315 316 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 317 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 318 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 319 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 320 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 321 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 322 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 323 ((PCLK) == RCC_HCLK_Div16)) 324 /** 325 * @} 326 */ 327 328 /** @defgroup RCC_Interrupt_source 329 * @{ 330 */ 331 332 #define RCC_IT_LSIRDY ((uint8_t)0x01) 333 #define RCC_IT_LSERDY ((uint8_t)0x02) 334 #define RCC_IT_HSIRDY ((uint8_t)0x04) 335 #define RCC_IT_HSERDY ((uint8_t)0x08) 336 #define RCC_IT_PLLRDY ((uint8_t)0x10) 337 #define RCC_IT_CSS ((uint8_t)0x80) 338 339 #ifndef STM32F10X_CL 340 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 341 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 342 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 343 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 344 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 345 #else 346 #define RCC_IT_PLL2RDY ((uint8_t)0x20) 347 #define RCC_IT_PLL3RDY ((uint8_t)0x40) 348 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 349 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 350 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 351 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 352 ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) 353 #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) 354 #endif /* STM32F10X_CL */ 355 356 357 /** 358 * @} 359 */ 360 361 #ifndef STM32F10X_CL 362 /** @defgroup USB_Device_clock_source 363 * @{ 364 */ 365 366 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) 367 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) 368 369 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ 370 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 371 #else 372 /** @defgroup USB_OTG_FS_clock_source 373 * @{ 374 */ 375 #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) 376 #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) 377 378 #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ 379 ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) 380 #endif /* STM32F10X_CL */ 381 /** 382 * @} 383 */ 384 385 #ifdef STM32F10X_CL 386 /** @defgroup I2S2_clock_source 387 * @{ 388 */ 389 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) 390 #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) 391 392 #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ 393 ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) 394 /** 395 * @} 396 */ 397 398 /** @defgroup I2S3_clock_source 399 * @{ 400 */ 401 #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) 402 #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) 403 404 #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ 405 ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) 406 /** 407 * @} 408 */ 409 #endif /* STM32F10X_CL */ 410 411 412 /** @defgroup ADC_clock_source 413 * @{ 414 */ 415 416 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 417 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 418 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 419 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 420 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 421 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 422 /** 423 * @} 424 */ 425 426 /** @defgroup LSE_configuration 427 * @{ 428 */ 429 430 #define RCC_LSE_OFF ((uint8_t)0x00) 431 #define RCC_LSE_ON ((uint8_t)0x01) 432 #define RCC_LSE_Bypass ((uint8_t)0x04) 433 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 434 ((LSE) == RCC_LSE_Bypass)) 435 /** 436 * @} 437 */ 438 439 /** @defgroup RTC_clock_source 440 * @{ 441 */ 442 443 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 444 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 445 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 446 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 447 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 448 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 449 /** 450 * @} 451 */ 452 453 /** @defgroup AHB_peripheral 454 * @{ 455 */ 456 457 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 458 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) 459 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 460 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 461 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) 462 463 #ifndef STM32F10X_CL 464 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) 465 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 466 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 467 #else 468 #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) 469 #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) 470 #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) 471 #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) 472 473 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) 474 #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) 475 #endif /* STM32F10X_CL */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup APB2_peripheral 481 * @{ 482 */ 483 484 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 485 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 486 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) 487 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 488 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 489 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) 490 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) 491 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) 492 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 493 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) 494 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 495 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 496 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) 497 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) 498 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) 499 500 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) 501 /** 502 * @} 503 */ 504 505 /** @defgroup APB1_peripheral 506 * @{ 507 */ 508 509 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 510 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 511 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 512 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 513 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 514 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 515 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 516 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 517 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 518 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 519 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 520 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 521 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 522 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 523 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 524 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 525 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 526 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) 527 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 528 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 529 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 530 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00)) 531 532 /** 533 * @} 534 */ 535 536 /** @defgroup Clock_source_to_output_on_MCO_pin 537 * @{ 538 */ 539 540 #define RCC_MCO_NoClock ((uint8_t)0x00) 541 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 542 #define RCC_MCO_HSI ((uint8_t)0x05) 543 #define RCC_MCO_HSE ((uint8_t)0x06) 544 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 545 546 #ifndef STM32F10X_CL 547 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 548 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 549 ((MCO) == RCC_MCO_PLLCLK_Div2)) 550 #else 551 #define RCC_MCO_PLL2CLK ((uint8_t)0x08) 552 #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) 553 #define RCC_MCO_XT1 ((uint8_t)0x0A) 554 #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) 555 556 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 557 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 558 ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ 559 ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ 560 ((MCO) == RCC_MCO_PLL3CLK)) 561 #endif /* STM32F10X_CL */ 562 563 /** 564 * @} 565 */ 566 567 /** @defgroup RCC_Flag 568 * @{ 569 */ 570 571 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 572 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 573 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 574 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 575 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 576 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 577 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 578 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 579 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 580 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 581 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 582 583 #ifndef STM32F10X_CL 584 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 585 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 586 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 587 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 588 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 589 ((FLAG) == RCC_FLAG_LPWRRST)) 590 #else 591 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) 592 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) 593 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 594 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 595 ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ 596 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 597 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 598 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 599 ((FLAG) == RCC_FLAG_LPWRRST)) 600 #endif /* STM32F10X_CL */ 601 602 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 603 /** 604 * @} 605 */ 606 607 /** 608 * @} 609 */ 610 611 /** @defgroup RCC_Exported_Macros 612 * @{ 613 */ 614 615 /** 616 * @} 617 */ 618 619 /** @defgroup RCC_Exported_Functions 620 * @{ 621 */ 622 623 void RCC_DeInit(void); 624 void RCC_HSEConfig(uint32_t RCC_HSE); 625 ErrorStatus RCC_WaitForHSEStartUp(void); 626 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 627 void RCC_HSICmd(FunctionalState NewState); 628 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 629 void RCC_PLLCmd(FunctionalState NewState); 630 631 #ifdef STM32F10X_CL 632 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); 633 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); 634 void RCC_PLL2Config(uint32_t RCC_PLL2Mul); 635 void RCC_PLL2Cmd(FunctionalState NewState); 636 void RCC_PLL3Config(uint32_t RCC_PLL3Mul); 637 void RCC_PLL3Cmd(FunctionalState NewState); 638 #endif /* STM32F10X_CL */ 639 640 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 641 uint8_t RCC_GetSYSCLKSource(void); 642 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 643 void RCC_PCLK1Config(uint32_t RCC_HCLK); 644 void RCC_PCLK2Config(uint32_t RCC_HCLK); 645 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 646 647 #ifndef STM32F10X_CL 648 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 649 #else 650 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); 651 #endif /* STM32F10X_CL */ 652 653 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 654 655 #ifdef STM32F10X_CL 656 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); 657 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); 658 #endif /* STM32F10X_CL */ 659 660 void RCC_LSEConfig(uint8_t RCC_LSE); 661 void RCC_LSICmd(FunctionalState NewState); 662 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 663 void RCC_RTCCLKCmd(FunctionalState NewState); 664 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 665 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 666 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 667 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 668 669 #ifdef STM32F10X_CL 670 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 671 #endif /* STM32F10X_CL */ 672 673 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 674 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 675 void RCC_BackupResetCmd(FunctionalState NewState); 676 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 677 void RCC_MCOConfig(uint8_t RCC_MCO); 678 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 679 void RCC_ClearFlag(void); 680 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 681 void RCC_ClearITPendingBit(uint8_t RCC_IT); 682 683 #ifdef __cplusplus 684 } 685 #endif 686 687 #endif /* __STM32F10x_RCC_H */ 688 /** 689 * @} 690 */ 691 692 /** 693 * @} 694 */ 695 696 /** 697 * @} 698 */ 699 700 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ 701