1 // --------------------------------------------------------------------------- 2 // This file is part of reSID, a MOS6581 SID emulator engine. 3 // Copyright (C) 2010 Dag Lem <resid@nimrod.no> 4 // 5 // This program is free software; you can redistribute it and/or modify 6 // it under the terms of the GNU General Public License as published by 7 // the Free Software Foundation; either version 2 of the License, or 8 // (at your option) any later version. 9 // 10 // This program is distributed in the hope that it will be useful, 11 // but WITHOUT ANY WARRANTY; without even the implied warranty of 12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 // GNU General Public License for more details. 14 // 15 // You should have received a copy of the GNU General Public License 16 // along with this program; if not, write to the Free Software 17 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 // --------------------------------------------------------------------------- 19 20 #ifndef RESID_WAVE_H 21 #define RESID_WAVE_H 22 23 #include "resid-config.h" test(const CharT * fmt)24 25 namespace reSID 26 { 27 28 // ---------------------------------------------------------------------------- 29 // A 24 bit accumulator is the basis for waveform generation. FREQ is added to 30 // the lower 16 bits of the accumulator each cycle. 31 // The accumulator is set to zero when TEST is set, and starts counting 32 // when TEST is cleared. 33 // The noise waveform is taken from intermediate bits of a 23 bit shift 34 // register. This register is clocked by bit 19 of the accumulator. 35 // ---------------------------------------------------------------------------- 36 class WaveformGenerator 37 { 38 public: 39 WaveformGenerator(); 40 41 void set_sync_source(WaveformGenerator*); 42 void set_chip_model(chip_model model); 43 44 void clock(); 45 void clock(cycle_count delta_t); 46 void synchronize(); 47 void reset(); 48 49 void writeFREQ_LO(reg8); 50 void writeFREQ_HI(reg8); 51 void writePW_LO(reg8); 52 void writePW_HI(reg8); 53 void writeCONTROL_REG(reg8); 54 reg8 readOSC(); 55 56 // 12-bit waveform output. 57 short output(); 58 59 // Calculate and set waveform output value. 60 void set_waveform_output(); 61 void set_waveform_output(cycle_count delta_t); 62 63 protected: 64 void clock_shift_register(); 65 void write_shift_register(); 66 void set_noise_output(); 67 void wave_bitfade(); 68 void shiftreg_bitfade(); 69 70 const WaveformGenerator* sync_source; 71 WaveformGenerator* sync_dest; 72 73 reg24 accumulator; 74 75 // Tell whether the accumulator MSB was set high on this cycle. 76 bool msb_rising; 77 78 // Fout = (Fn*Fclk/16777216)Hz 79 // reg16 freq; 80 reg24 freq; 81 // PWout = (PWn/40.95)% 82 reg12 pw; 83 84 reg24 shift_register; 85 86 // Remaining time to fully reset shift register. 87 cycle_count shift_register_reset; 88 // Emulation of pipeline causing bit 19 to clock the shift register. 89 cycle_count shift_pipeline; 90 91 // Helper variables for waveform table lookup. 92 reg24 ring_msb_mask; 93 unsigned short no_noise; 94 unsigned short noise_output; 95 unsigned short no_noise_or_noise_output; 96 unsigned short no_pulse; 97 unsigned short pulse_output; 98 99 // The control register right-shifted 4 bits; used for waveform table lookup. 100 reg8 waveform; 101 102 // 8580 tri/saw pipeline 103 reg12 tri_saw_pipeline; 104 reg12 osc3; 105 106 // The remaining control register bits. 107 reg8 test; 108 reg8 ring_mod; 109 reg8 sync; 110 // The gate bit is handled by the EnvelopeGenerator. 111 112 // DAC input. 113 reg12 waveform_output; 114 // Fading time for floating DAC input (waveform 0). 115 cycle_count floating_output_ttl; 116 117 chip_model sid_model; 118 119 // Sample data for waveforms, not including noise. 120 unsigned short* wave; 121 static unsigned short model_wave[2][8][1 << 12]; 122 // DAC lookup tables. 123 static unsigned short model_dac[2][1 << 12]; 124 125 friend class Voice; 126 friend class SID; 127 }; 128 129 130 // ---------------------------------------------------------------------------- 131 // Inline functions. 132 // The following functions are defined inline because they are called every 133 // time a sample is calculated. 134 // ---------------------------------------------------------------------------- 135 136 #if RESID_INLINING || defined(RESID_WAVE_CC) 137 138 // ---------------------------------------------------------------------------- 139 // SID clocking - 1 cycle. 140 // ---------------------------------------------------------------------------- 141 RESID_INLINE 142 void WaveformGenerator::clock() 143 { 144 if (unlikely(test)) { 145 // Count down time to fully reset shift register. 146 if (unlikely(shift_register_reset) && unlikely(!--shift_register_reset)) { 147 shiftreg_bitfade(); 148 } 149 150 // The test bit sets pulse high. 151 pulse_output = 0xfff; 152 } 153 else { 154 // Calculate new accumulator value; 155 reg24 accumulator_next = (accumulator + freq) & 0xffffff; 156 reg24 accumulator_bits_set = ~accumulator & accumulator_next; 157 accumulator = accumulator_next; 158 159 // Check whether the MSB is set high. This is used for synchronization. 160 msb_rising = (accumulator_bits_set & 0x800000) ? true : false; 161 162 // Shift noise register once for each time accumulator bit 19 is set high. 163 // The shift is delayed 2 cycles. 164 if (unlikely(accumulator_bits_set & 0x080000)) { 165 // Pipeline: Detect rising bit, shift phase 1, shift phase 2. 166 shift_pipeline = 2; 167 } 168 else if (unlikely(shift_pipeline) && !--shift_pipeline) { 169 clock_shift_register(); 170 } 171 } 172 } 173 174 // ---------------------------------------------------------------------------- 175 // SID clocking - delta_t cycles. 176 // ---------------------------------------------------------------------------- 177 RESID_INLINE 178 void WaveformGenerator::clock(cycle_count delta_t) 179 { 180 if (unlikely(test)) { 181 // Count down time to fully reset shift register. 182 if (shift_register_reset) { 183 shift_register_reset -= delta_t; 184 if (unlikely(shift_register_reset <= 0)) { 185 shift_register = 0x7fffff; 186 shift_register_reset = 0; 187 188 // New noise waveform output. 189 set_noise_output(); 190 } 191 } 192 193 // The test bit sets pulse high. 194 pulse_output = 0xfff; 195 } 196 else { 197 // Calculate new accumulator value; 198 reg24 delta_accumulator = delta_t*freq; 199 reg24 accumulator_next = (accumulator + delta_accumulator) & 0xffffff; 200 reg24 accumulator_bits_set = ~accumulator & accumulator_next; 201 accumulator = accumulator_next; 202 203 // Check whether the MSB is set high. This is used for synchronization. 204 msb_rising = (accumulator_bits_set & 0x800000) ? true : false; 205 206 // NB! Any pipelined shift register clocking from single cycle clocking 207 // will be lost. It is not worth the trouble to flush the pipeline here. 208 209 // Shift noise register once for each time accumulator bit 19 is set high. 210 // Bit 19 is set high each time 2^20 (0x100000) is added to the accumulator. 211 reg24 shift_period = 0x100000; 212 213 while (delta_accumulator) { 214 if (likely(delta_accumulator < shift_period)) { 215 shift_period = delta_accumulator; 216 // Determine whether bit 19 is set on the last period. 217 // NB! Requires two's complement integer. 218 if (likely(shift_period <= 0x080000)) { 219 // Check for flip from 0 to 1. 220 if (((accumulator - shift_period) & 0x080000) || !(accumulator & 0x080000)) 221 { 222 break; 223 } 224 } 225 else { 226 // Check for flip from 0 (to 1 or via 1 to 0) or from 1 via 0 to 1. 227 if (((accumulator - shift_period) & 0x080000) && !(accumulator & 0x080000)) 228 { 229 break; 230 } 231 } 232 } 233 234 // Shift the noise/random register. 235 // NB! The two-cycle pipeline delay is only modeled for 1 cycle clocking. 236 clock_shift_register(); 237 238 delta_accumulator -= shift_period; 239 } 240 241 // Calculate pulse high/low. 242 // NB! The one-cycle pipeline delay is only modeled for 1 cycle clocking. 243 pulse_output = (accumulator >> 12) >= pw ? 0xfff : 0x000; 244 } 245 } 246 247 248 // ---------------------------------------------------------------------------- 249 // Synchronize oscillators. 250 // This must be done after all the oscillators have been clock()'ed since the 251 // oscillators operate in parallel. 252 // Note that the oscillators must be clocked exactly on the cycle when the 253 // MSB is set high for hard sync to operate correctly. See SID::clock(). 254 // ---------------------------------------------------------------------------- 255 RESID_INLINE 256 void WaveformGenerator::synchronize() 257 { 258 // A special case occurs when a sync source is synced itself on the same 259 // cycle as when its MSB is set high. In this case the destination will 260 // not be synced. This has been verified by sampling OSC3. 261 if (unlikely(msb_rising) && sync_dest->sync && !(sync && sync_source->msb_rising)) { 262 sync_dest->accumulator = 0; 263 } 264 } 265 266 267 // ---------------------------------------------------------------------------- 268 // Waveform output. 269 // The output from SID 8580 is delayed one cycle compared to SID 6581; 270 // this is only modeled for single cycle clocking (see sid.cc). 271 // ---------------------------------------------------------------------------- 272 273 // No waveform: 274 // When no waveform is selected, the DAC input is floating. 275 // 276 277 // Triangle: 278 // The upper 12 bits of the accumulator are used. 279 // The MSB is used to create the falling edge of the triangle by inverting 280 // the lower 11 bits. The MSB is thrown away and the lower 11 bits are 281 // left-shifted (half the resolution, full amplitude). 282 // Ring modulation substitutes the MSB with MSB EOR NOT sync_source MSB. 283 // 284 285 // Sawtooth: 286 // The output is identical to the upper 12 bits of the accumulator. 287 // 288 289 // Pulse: 290 // The upper 12 bits of the accumulator are used. 291 // These bits are compared to the pulse width register by a 12 bit digital 292 // comparator; output is either all one or all zero bits. 293 // The pulse setting is delayed one cycle after the compare; this is only 294 // modeled for single cycle clocking. 295 // 296 // The test bit, when set to one, holds the pulse waveform output at 0xfff 297 // regardless of the pulse width setting. 298 // 299 300 // Noise: 301 // The noise output is taken from intermediate bits of a 23-bit shift register 302 // which is clocked by bit 19 of the accumulator. 303 // The shift is delayed 2 cycles after bit 19 is set high; this is only 304 // modeled for single cycle clocking. 305 // 306 // Operation: Calculate EOR result, shift register, set bit 0 = result. 307 // 308 // reset ------------------------------------------- 309 // | | | 310 // test--OR-->EOR<-- | 311 // | | | 312 // 2 2 2 1 1 1 1 1 1 1 1 1 1 | 313 // Register bits: 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <--- 314 // | | | | | | | | 315 // Waveform bits: 1 1 9 8 7 6 5 4 316 // 1 0 317 // 318 // The low 4 waveform bits are zero (grounded). 319 // 320 321 RESID_INLINE void WaveformGenerator::clock_shift_register() 322 { 323 // bit0 = (bit22 | test) ^ bit17 324 reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1; 325 shift_register = ((shift_register << 1) | bit0) & 0x7fffff; 326 327 // New noise waveform output. 328 set_noise_output(); 329 } 330 331 RESID_INLINE void WaveformGenerator::write_shift_register() 332 { 333 // Write changes to the shift register output caused by combined waveforms 334 // back into the shift register. 335 // A bit once set to zero cannot be changed, hence the and'ing. 336 // FIXME: Write test program to check the effect of 1 bits and whether 337 // neighboring bits are affected. 338 339 shift_register &= 340 ~((1<<20)|(1<<18)|(1<<14)|(1<<11)|(1<<9)|(1<<5)|(1<<2)|(1<<0)) | 341 ((waveform_output & 0x800) << 9) | // Bit 11 -> bit 20 342 ((waveform_output & 0x400) << 8) | // Bit 10 -> bit 18 343 ((waveform_output & 0x200) << 5) | // Bit 9 -> bit 14 344 ((waveform_output & 0x100) << 3) | // Bit 8 -> bit 11 345 ((waveform_output & 0x080) << 2) | // Bit 7 -> bit 9 346 ((waveform_output & 0x040) >> 1) | // Bit 6 -> bit 5 347 ((waveform_output & 0x020) >> 3) | // Bit 5 -> bit 2 348 ((waveform_output & 0x010) >> 4); // Bit 4 -> bit 0 349 350 noise_output &= waveform_output; 351 no_noise_or_noise_output = no_noise | noise_output; 352 } 353 354 RESID_INLINE void WaveformGenerator::set_noise_output() 355 { 356 noise_output = 357 ((shift_register & 0x100000) >> 9) | 358 ((shift_register & 0x040000) >> 8) | 359 ((shift_register & 0x004000) >> 5) | 360 ((shift_register & 0x000800) >> 3) | 361 ((shift_register & 0x000200) >> 2) | 362 ((shift_register & 0x000020) << 1) | 363 ((shift_register & 0x000004) << 3) | 364 ((shift_register & 0x000001) << 4); 365 366 no_noise_or_noise_output = no_noise | noise_output; 367 } 368 369 // Combined waveforms: 370 // By combining waveforms, the bits of each waveform are effectively short 371 // circuited. A zero bit in one waveform will result in a zero output bit 372 // (thus the infamous claim that the waveforms are AND'ed). 373 // However, a zero bit in one waveform may also affect the neighboring bits 374 // in the output. 375 // 376 // Example: 377 // 378 // 1 1 379 // Bit # 1 0 9 8 7 6 5 4 3 2 1 0 380 // ----------------------- 381 // Sawtooth 0 0 0 1 1 1 1 1 1 0 0 0 382 // 383 // Triangle 0 0 1 1 1 1 1 1 0 0 0 0 384 // 385 // AND 0 0 0 1 1 1 1 1 0 0 0 0 386 // 387 // Output 0 0 0 0 1 1 1 0 0 0 0 0 388 // 389 // 390 // Re-vectorized die photographs reveal the mechanism behind this behavior. 391 // Each waveform selector bit acts as a switch, which directly connects 392 // internal outputs into the waveform DAC inputs as follows: 393 // 394 // * Noise outputs the shift register bits to DAC inputs as described above. 395 // Each output is also used as input to the next bit when the shift register 396 // is shifted. 397 // * Pulse connects a single line to all DAC inputs. The line is connected to 398 // either 5V (pulse on) or 0V (pulse off) at bit 11, and ends at bit 0. 399 // * Triangle connects the upper 11 bits of the (MSB EOR'ed) accumulator to the 400 // DAC inputs, so that DAC bit 0 = 0, DAC bit n = accumulator bit n - 1. 401 // * Sawtooth connects the upper 12 bits of the accumulator to the DAC inputs, 402 // so that DAC bit n = accumulator bit n. Sawtooth blocks out the MSB from 403 // the EOR used to generate the triangle waveform. 404 // 405 // We can thus draw the following conclusions: 406 // 407 // * The shift register may be written to by combined waveforms. 408 // * The pulse waveform interconnects all bits in combined waveforms via the 409 // pulse line. 410 // * The combination of triangle and sawtooth interconnects neighboring bits 411 // of the sawtooth waveform. 412 // 413 // This behavior would be quite difficult to model exactly, since the short 414 // circuits are not binary, but are subject to analog effects. Tests show that 415 // minor (1 bit) differences can actually occur in the output from otherwise 416 // identical samples from OSC3 when waveforms are combined. To further 417 // complicate the situation the output changes slightly with time (more 418 // neighboring bits are successively set) when the 12-bit waveform 419 // registers are kept unchanged. 420 // 421 // The output is instead approximated by using the upper bits of the 422 // accumulator as an index to look up the combined output in a table 423 // containing actual combined waveform samples from OSC3. 424 // These samples are 8 bit, so 4 bits of waveform resolution is lost. 425 // All OSC3 samples are taken with FREQ=0x1000, adding a 1 to the upper 12 426 // bits of the accumulator each cycle for a sample period of 4096 cycles. 427 // 428 // Sawtooth+Triangle: 429 // The accumulator is used to look up an OSC3 sample. 430 // 431 // Pulse+Triangle: 432 // The accumulator is used to look up an OSC3 sample. When ring modulation is 433 // selected, the accumulator MSB is substituted with MSB EOR NOT sync_source MSB. 434 // 435 // Pulse+Sawtooth: 436 // The accumulator is used to look up an OSC3 sample. 437 // The sample is output if the pulse output is on. 438 // 439 // Pulse+Sawtooth+Triangle: 440 // The accumulator is used to look up an OSC3 sample. 441 // The sample is output if the pulse output is on. 442 // 443 // Combined waveforms including noise: 444 // All waveform combinations including noise output zero after a few cycles, 445 // since the waveform bits are and'ed into the shift register via the shift 446 // register outputs. 447 448 static reg12 noise_pulse6581(reg12 noise) 449 { 450 return (noise < 0xf00) ? 0x000 : noise & (noise<<1) & (noise<<2); 451 } 452 453 static reg12 noise_pulse8580(reg12 noise) 454 { 455 return (noise < 0xfc0) ? noise & (noise << 1) : 0xfc0; 456 } 457 458 RESID_INLINE 459 void WaveformGenerator::set_waveform_output() 460 { 461 // Set output value. 462 if (likely(waveform)) { 463 // The bit masks no_pulse and no_noise are used to achieve branch-free 464 // calculation of the output value. 465 int ix = (accumulator ^ (~sync_source->accumulator & ring_msb_mask)) >> 12; 466 467 waveform_output = wave[ix] & (no_pulse | pulse_output) & no_noise_or_noise_output; 468 469 if (unlikely((waveform & 0xc) == 0xc)) 470 { 471 waveform_output = (sid_model == MOS6581) ? 472 noise_pulse6581(waveform_output) : noise_pulse8580(waveform_output); 473 } 474 475 // Triangle/Sawtooth output is delayed half cycle on 8580. 476 // This will appear as a one cycle delay on OSC3 as it is 477 // latched in the first phase of the clock. 478 if ((waveform & 3) && (sid_model == MOS8580)) 479 { 480 osc3 = tri_saw_pipeline & (no_pulse | pulse_output) & no_noise_or_noise_output; 481 tri_saw_pipeline = wave[ix]; 482 } 483 else 484 { 485 osc3 = waveform_output; 486 } 487 488 if ((waveform & 0x2) && unlikely(waveform & 0xd) && (sid_model == MOS6581)) { 489 // In the 6581 the top bit of the accumulator may be driven low by combined waveforms 490 // when the sawtooth is selected 491 accumulator &= (waveform_output << 12) | 0x7fffff; 492 } 493 494 if (unlikely(waveform > 0x8) && likely(!test) && likely(shift_pipeline != 1)) { 495 // Combined waveforms write to the shift register. 496 write_shift_register(); 497 } 498 } 499 else { 500 // Age floating DAC input. 501 if (likely(floating_output_ttl) && unlikely(!--floating_output_ttl)) { 502 wave_bitfade(); 503 } 504 } 505 506 // The pulse level is defined as (accumulator >> 12) >= pw ? 0xfff : 0x000. 507 // The expression -((accumulator >> 12) >= pw) & 0xfff yields the same 508 // results without any branching (and thus without any pipeline stalls). 509 // NB! This expression relies on that the result of a boolean expression 510 // is either 0 or 1, and furthermore requires two's complement integer. 511 // A few more cycles may be saved by storing the pulse width left shifted 512 // 12 bits, and dropping the and with 0xfff (this is valid since pulse is 513 // used as a bit mask on 12 bit values), yielding the expression 514 // -(accumulator >= pw24). However this only results in negligible savings. 515 516 // The result of the pulse width compare is delayed one cycle. 517 // Push next pulse level into pulse level pipeline. 518 pulse_output = -((accumulator >> 12) >= pw) & 0xfff; 519 } 520 521 RESID_INLINE 522 void WaveformGenerator::set_waveform_output(cycle_count delta_t) 523 { 524 // Set output value. 525 if (likely(waveform)) { 526 // The bit masks no_pulse and no_noise are used to achieve branch-free 527 // calculation of the output value. 528 int ix = (accumulator ^ (~sync_source->accumulator & ring_msb_mask)) >> 12; 529 waveform_output = 530 wave[ix] & (no_pulse | pulse_output) & no_noise_or_noise_output; 531 // Triangle/Sawtooth output delay for the 8580 is not modeled 532 osc3 = waveform_output; 533 534 if ((waveform & 0x2) && unlikely(waveform & 0xd) && (sid_model == MOS6581)) { 535 accumulator &= (waveform_output << 12) | 0x7fffff; 536 } 537 538 if (unlikely(waveform > 0x8) && likely(!test)) { 539 // Combined waveforms write to the shift register. 540 // NB! Since cycles are skipped in delta_t clocking, writes will be 541 // missed. Single cycle clocking must be used for 100% correct operation. 542 write_shift_register(); 543 } 544 } 545 else { 546 if (likely(floating_output_ttl)) { 547 // Age floating D/A output. 548 floating_output_ttl -= delta_t; 549 if (unlikely(floating_output_ttl <= 0)) { 550 floating_output_ttl = 0; 551 osc3 = waveform_output = 0; 552 } 553 } 554 } 555 } 556 557 558 // ---------------------------------------------------------------------------- 559 // Waveform output (12 bits). 560 // ---------------------------------------------------------------------------- 561 562 // The digital waveform output is converted to an analog signal by a 12-bit 563 // DAC. Re-vectorized die photographs reveal that the DAC is an R-2R ladder 564 // built up as follows: 565 // 566 // 12V 11 10 9 8 7 6 5 4 3 2 1 0 GND 567 // Strange | | | | | | | | | | | | | | Missing 568 // part 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R term. 569 // (bias) | | | | | | | | | | | | | | 570 // --R- --R---R---R---R---R---R---R---R---R---R---R-- --- 571 // | _____ 572 // __|__ __|__ | 573 // ----- ===== | 574 // | | | | | 575 // 12V --- ----- ------- GND 576 // | 577 // wout 578 // 579 // Bit on: 5V 580 // Bit off: 0V (GND) 581 // 582 // As is the case with all MOS 6581 DACs, the termination to (virtual) ground 583 // at bit 0 is missing. The MOS 8580 has correct termination, and has also 584 // done away with the bias part on the left hand side of the figure above. 585 // 586 587 RESID_INLINE 588 short WaveformGenerator::output() 589 { 590 // DAC imperfections are emulated by using waveform_output as an index 591 // into a DAC lookup table. readOSC() uses waveform_output directly. 592 return model_dac[sid_model][waveform_output]; 593 } 594 595 #endif // RESID_INLINING || defined(RESID_WAVE_CC) 596 597 } // namespace reSID 598 599 #endif // not RESID_WAVE_H 600