1 /**CFile****************************************************************
2
3 FileName [fpgaCore.c]
4
5 PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
6
7 Synopsis [Technology mapping for variable-size-LUT FPGAs.]
8
9 Author [MVSIS Group]
10
11 Affiliation [UC Berkeley]
12
13 Date [Ver. 2.0. Started - August 18, 2004.]
14
15 Revision [$Id: fpgaCore.c,v 1.7 2004/10/01 23:41:04 satrajit Exp $]
16
17 ***********************************************************************/
18
19 #include "fpgaInt.h"
20
21 ABC_NAMESPACE_IMPL_START
22
23
24 ////////////////////////////////////////////////////////////////////////
25 /// DECLARATIONS ///
26 ////////////////////////////////////////////////////////////////////////
27
28 static int Fpga_MappingPostProcess( Fpga_Man_t * p );
29
30 extern clock_t s_MappingTime;
31 extern int s_MappingMem;
32
33
34 ////////////////////////////////////////////////////////////////////////
35 /// FUNCTION DEFINITIONS ///
36 ////////////////////////////////////////////////////////////////////////
37
38 /**Function*************************************************************
39
40 Synopsis [Performs technology mapping for the given object graph.]
41
42 Description [The object graph is stored in the mapping manager.
43 First, all the AND-nodes, which fanout into the POs, are collected
44 in the DFS fashion. Next, three steps are performed: the k-feasible
45 cuts are computed for each node, the truth tables are computed for
46 each cut, and the delay-optimal matches are assigned for each node.]
47
48 SideEffects []
49
50 SeeAlso []
51
52 ***********************************************************************/
Fpga_Mapping(Fpga_Man_t * p)53 int Fpga_Mapping( Fpga_Man_t * p )
54 {
55 clock_t clk, clkTotal = clock();
56
57 // collect the nodes reachable from POs in the DFS order (including the choices)
58 p->vAnds = Fpga_MappingDfs( p, 1 );
59 Fpga_ManReportChoices( p ); // recomputes levels
60 Fpga_MappingSetChoiceLevels( p );
61
62 // compute the cuts of nodes in the DFS order
63 clk = clock();
64 Fpga_MappingCuts( p );
65 p->timeCuts = clock() - clk;
66
67 // match the truth tables to the supergates
68 clk = clock();
69 if ( !Fpga_MappingMatches( p, 1 ) )
70 return 0;
71 p->timeMatch = clock() - clk;
72
73 // perform area recovery
74 clk = clock();
75 if ( !Fpga_MappingPostProcess( p ) )
76 return 0;
77 p->timeRecover = clock() - clk;
78 //ABC_PRT( "Total mapping time", clock() - clkTotal );
79
80 s_MappingTime = clock() - clkTotal;
81 s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
82
83 // print the AI-graph used for mapping
84 //Fpga_ManShow( p, "test" );
85 // if ( p->fVerbose )
86 // Fpga_MappingPrintOutputArrivals( p );
87 if ( p->fVerbose )
88 {
89 ABC_PRT( "Total time", clock() - clkTotal );
90 }
91 return 1;
92 }
93
94 /**Function*************************************************************
95
96 Synopsis [Postprocesses the mapped network for area recovery.]
97
98 Description [This procedure assumes that the mapping is assigned.
99 It iterates the loop, in which the required times are computed and
100 the mapping is updated. It is conceptually similar to the paper:
101 V. Manohararajah, S. D. Brown, Z. G. Vranesic, Heuristics for area
102 minimization in LUT-based FPGA technology mapping. Proc. IWLS '04.]
103
104 SideEffects []
105
106 SeeAlso []
107
108 ***********************************************************************/
Fpga_MappingPostProcess(Fpga_Man_t * p)109 int Fpga_MappingPostProcess( Fpga_Man_t * p )
110 {
111 int fShowSwitching = 0;
112 int fRecoverAreaFlow = 1;
113 int fRecoverArea = 1;
114 float aAreaTotalCur, aAreaTotalCur2;
115 int Iter;
116 clock_t clk;
117
118 //if ( p->fVerbose )
119 // printf( "Best clock period = %5.2f\n", Fpga_TimeComputeArrivalMax(p) );
120
121 // compute area, set references, and collect nodes used in the mapping
122 Iter = 1;
123 aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
124 if ( p->fVerbose )
125 {
126 printf( "Iteration %dD : Area = %8.1f ", Iter++, aAreaTotalCur );
127 if ( fShowSwitching )
128 printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
129 else
130 printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
131
132 ABC_PRT( "Time", p->timeMatch );
133 }
134
135 if ( !p->fAreaRecovery )
136 return 1;
137
138 if ( fRecoverAreaFlow )
139 {
140 clk = clock();
141 // compute the required times and the fanouts
142 Fpga_TimeComputeRequiredGlobal( p, 1 );
143 // remap topologically
144 Fpga_MappingMatches( p, 0 );
145 // get the resulting area
146 // aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
147 aAreaTotalCur = Fpga_MappingAreaTrav( p );
148 // note that here we do not update the reference counter
149 // for some reason, this works better on benchmarks
150 if ( p->fVerbose )
151 {
152 printf( "Iteration %dF : Area = %8.1f ", Iter++, aAreaTotalCur );
153 if ( fShowSwitching )
154 printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
155 else
156 printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
157 ABC_PRT( "Time", clock() - clk );
158 }
159 }
160
161 // update reference counters
162 aAreaTotalCur2 = Fpga_MappingSetRefsAndArea( p );
163 assert( aAreaTotalCur == aAreaTotalCur2 );
164
165 if ( fRecoverArea )
166 {
167 clk = clock();
168 // compute the required times and the fanouts
169 Fpga_TimeComputeRequiredGlobal( p, 0 );
170 // remap topologically
171 if ( p->fSwitching )
172 Fpga_MappingMatchesSwitch( p );
173 else
174 Fpga_MappingMatchesArea( p );
175 // get the resulting area
176 aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
177 if ( p->fVerbose )
178 {
179 printf( "Iteration %d%s : Area = %8.1f ", Iter++, (p->fSwitching?"S":"A"), aAreaTotalCur );
180 if ( fShowSwitching )
181 printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
182 else
183 printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
184 ABC_PRT( "Time", clock() - clk );
185 }
186 }
187
188 p->fAreaGlo = aAreaTotalCur;
189 return 1;
190 }
191
192
193 ABC_NAMESPACE_IMPL_END
194
195