1-- ### -------------------------------------------------------------- ### 2-- # # 3-- # file : mips_cpu.vst # 4-- # date : september 25 1996 # 5-- # version : v0.2 # 6-- # author : fahim RAHIM # 7-- # descr. : mips cpu board with on board ram (512 bytes), rom # 8-- # (512 bytes = 128 instructions) and, timer # 9-- # # 10-- ### -------------------------------------------------------------- ### 11 12entity mips_cpu is 13 port ( 14 CK : in bit ; 15 TEST : in bit ; 16 SCIN : in bit ; 17 SCOUT : out bit ; 18 RESET : in bit ; 19 FRZ : in bit ; 20 RW : inout bit ; 21 W : inout bit_vector ( 0 to 1) ; 22 DATA : inout mux_vector (31 downto 0) bus; 23 DATA_ADR : inout mux_vector (31 downto 0) bus; 24 VDD : in bit ; 25 VSS : in bit 26 ); 27 28end mips_cpu; 29 30architecture structral of mips_cpu is 31 32 signal E_RAMU_N : bit_vector ( 0 to 3) ; 33 signal E_RAMS_N : bit_vector ( 0 to 3) ; 34 signal E_ROMU_N : bit ; 35 signal E_ROMS_N : bit ; 36 signal E_TIME_N : bit ; 37 signal E_ROMR_N : bit ; 38 signal E_ROME_N : bit ; 39 40 signal rst : bit ; 41 signal berr : bit ; 42 signal IRQ_N : bit_vector( 5 downto 0) ; 43 44 component mips_chip 45 port ( 46 CK : in bit ; 47 RESET : in bit ; 48 FRZ : in bit ; 49 INT : in bit_vector ( 5 downto 0) ; 50 DATA : inout mux_vector (31 downto 0) bus ; 51 W : out bit_vector ( 0 to 1) ; 52 RW : out bit ; 53 ADR : out mux_vector (31 downto 0) bus ; 54 SCIN : in bit ; 55 BERR : in bit ; 56 TEST : in bit ; 57 SCOUT : out bit ; 58 VDD : in bit ; 59 VSS : in bit ; 60 VDDP : in bit ; 61 VSSP : in bit 62 ) ; 63 end component; 64 65 component mips_dec 66 port ( 67 CK : in bit ; 68 mips_DADR : in bit_vector (31 downto 0) ; 69 RW : in bit ; 70 W : in bit_vector ( 0 to 1) ; 71 berr : out bit ; 72 SEL_ROMU_N : out bit ; 73 SEL_RAMU_N : out bit_vector ( 0 to 3) ; 74 SEL_ROMS_N : out bit ; 75 SEL_RAMS_N : out bit_vector ( 0 to 3) ; 76 SEL_TIMER_N : out bit ; 77 SEL_ROMR_N : OUT BIT ; 78 SEL_ROME_N : OUT BIT ; 79 VDD : in bit ; 80 VSS : in bit 81 ); 82 end component; 83 84 component sr64_32a 85 port ( 86 E_N : in bit_vector ( 0 to 3) ; 87 W_N : in bit ; 88 DAT : inout mux_vector (31 downto 0) bus; 89 ADR : in bit_vector ( 5 downto 0) ; 90 VDD : in bit ; 91 VSS : in bit 92 ); 93 end component; 94 95 component romu 96 port ( 97 ADDRESS : in bit_vector (5 downto 0) ; 98 E_N : in bit ; 99 DATA : out mux_vector (31 downto 0) bus; 100 VDD : in bit ; 101 VSS : in bit 102 ); 103 end component; 104 105 component roms 106 port ( 107 ADDRESS : in bit_vector (5 downto 0) ; 108 E_N : in bit ; 109 DATA : out mux_vector (31 downto 0) bus; 110 VDD : in bit ; 111 VSS : in bit 112 ); 113 end component; 114 115 component romr 116 port ( 117 ADDRESS : in bit_vector (5 downto 0) ; 118 E_N : in bit ; 119 DATA : out mux_vector (31 downto 0) bus; 120 VDD : in bit ; 121 VSS : in bit 122 ); 123 end component; 124 125 component rome 126 port ( 127 ADDRESS : in bit_vector (5 downto 0) ; 128 E_N : in bit ; 129 DATA : out mux_vector (31 downto 0) bus; 130 VDD : in bit ; 131 VSS : in bit 132 ); 133 end component; 134 135 component timer 136 port ( 137 CK : in bit ; -- external clock 138 FRZ : in bit ; -- freeze 139 RESET_I : in bit ; -- reset input 140 SEL : in bit_vector ( 2 downto 0) ; -- register selection 141 DATA : inout mux_vector (31 downto 0) bus; -- data 142 RW : in bit ; -- access mode 143 E_N : in bit ; -- chip enable 144 RESET_O : out bit ; -- reset output (= TIMER_RESET OR RESET_I) 145 IRQ_N : out bit_vector(5 downto 0) ; -- interrupt request 146 VDD : in bit ; -- 147 VSS : in bit -- 148 ); 149 end component; 150 151begin 152 153 mips1 : mips_chip 154 port map ( 155 INT => IRQ_N , 156 TEST => TEST , 157 SCIN => SCIN , 158 SCOUT => SCOUT , 159 FRZ => FRZ , 160 RESET => RST , 161 ADR => DATA_ADR , 162 W => W , 163 RW => RW , 164 CK => CK , 165 BERR => BERR , 166 DATA => DATA , 167 VDDP => VDD , 168 VSSP => VSS , 169 VDD => VDD , 170 VSS => VSS 171 ); 172 173 mips_dec : mips_dec 174 port map ( 175 CK => CK , 176 MIPS_DADR => DATA_ADR , 177 RW => RW , 178 W => W , 179 berr => berr , 180 SEL_ROMU_N => E_ROMU_N , 181 SEL_RAMU_N => E_RAMU_N , 182 SEL_ROMS_N => E_ROMS_N , 183 SEL_RAMS_N => E_RAMS_N , 184 SEL_TIMER_N => E_TIME_N , 185 SEL_ROMR_N => E_ROMR_N , 186 SEL_ROME_N => E_ROME_N , 187 VDD => VDD , 188 VSS => VSS 189 ); 190 191 timer : timer 192 port map ( 193 CK => CK, 194 FRZ => VSS, 195 RESET_I => RESET, 196 SEL => DATA_ADR(4 downto 2), 197 DATA => DATA, 198 RW => RW, 199 E_N => E_TIME_N, 200 RESET_O => RST, 201 IRQ_N => IRQ_N, 202 VDD => VDD, 203 VSS => VSS 204 ); 205 206 ramu : sr64_32a 207 port map ( 208 E_N => E_RAMU_N , 209 W_N => RW , 210 DAT => DATA , 211 ADR => DATA_ADR ( 7 downto 2) , 212 VDD => VDD , 213 VSS => VSS 214 ); 215 216 romu : romu 217 port map ( 218 ADDRESS => DATA_ADR (7 downto 2) , 219 E_N => E_ROMU_N , 220 DATA => DATA , 221 VDD => VDD , 222 VSS => VSS 223 ); 224 225 rams : sr64_32a 226 port map ( 227 E_N => E_RAMS_N , 228 W_N => RW , 229 DAT => DATA , 230 ADR => DATA_ADR ( 7 downto 2) , 231 VDD => VDD , 232 VSS => VSS 233 ); 234 235 roms : roms 236 port map ( 237 ADDRESS => DATA_ADR (7 downto 2) , 238 E_N => E_ROMS_N , 239 DATA => DATA , 240 VDD => VDD , 241 VSS => VSS 242 ); 243 244 romr : romr 245 port map ( 246 ADDRESS => DATA_ADR (7 downto 2) , 247 E_N => E_ROMR_N , 248 DATA => DATA , 249 VDD => VDD , 250 VSS => VSS 251 ); 252rome : rome 253 port map ( 254 ADDRESS => DATA_ADR (7 downto 2) , 255 E_N => E_ROME_N , 256 DATA => DATA , 257 VDD => VDD , 258 VSS => VSS 259 ); 260 261end; 262