1.. program:: ghdl
2.. _USING:QuickStart:Simulation:
3
4Simulation
5##########
6
7As explained in :ref:`INTRO:GHDL`, `GHDL` is a compiler which translates `VHDL`
8files to machine code. Hence, the regular workflow is composed of three steps:
9
10* :ref:`Analysis:command`: convert design units (`VHDL` sources) to an internal
11  representation.
12* :ref:`Elaboration:command`: generate executable machine code for a target module
13  (top-level entity).
14* :ref:`Run:command`: execute the design to test the behaviour, generate
15  output/waveforms, etc.
16
17The following tips might be useful:
18
19* Don't forget to select the version of the VHDL standard you want to use (see
20  :ref:`VHDL_standards`). The default is :option:`--std=93c <--std>`. Use
21  :option:`--std=08 <--std>` for VHDL-2008 (albeit not fully implemented).
22
23  * Use :option:`--ieee=synopsys <--ieee>` if your design depends on a non-standard
24    implementation of the IEEE library.
25
26  * Use :option:`-fexplicit` and :option:`-frelaxed-rules` if needed. For instance,
27    if you would like to use VHDL 2008 and also use shared variables with an
28    ordinary type (deprecated in VHDL 2000), you can use ``--std=08 -frelaxed-rules``.
29
30* Use :option:`--work=LIB_NAME <--work>` to analyze files into the ``LIB_NAME`` library.
31  To use files analyzed to a different directory, give the path
32  to the ``LIB_NAME`` library using :option:`-P/path/to/name/directory/ <-P>`.
33
34* Use the same options for analysis and elaboration. E.g., first analyse with
35  ``ghdl -a --std=08 --work=mylib myfile.vhdl``; and then elaborate and run with
36  ``ghdl --elab-run --std=08 top``.
37
38Due to the fact that `VHDL` is processed as a general purpose language
39(instead of an `HDL`), all the language features are to be supported. I.e., `VHDL`
40sources do not need to be limited to the synthesisable subset. However, distinction
41between synthesisable and non-synthesisable (simulation-only) subsets is often
42misleading for users who are new to the language. Different examples are provided,
43in the hope of helping understand the different use cases:
44
45.. toctree::
46
47   hello/index
48   heartbeat/index
49   adder/index
50   DLXModelSuite
51
52.. TIP:: See :ghdlissue:`Learning VHDL with GHDL <1291>`.
53