1.. program:: ghdl 2.. _REF:ImplVHDL: 3 4Implementation of VHDL 5###################### 6 7.. _VHDL_standards: 8 9VHDL standards 10============== 11 12.. index:: VHDL standards 13 14.. index:: IEEE 1076 15 16.. index:: IEEE 1076a 17 18.. index:: 1076 19 20.. index:: 1076a 21 22.. index:: v87 23 24.. index:: v93 25 26.. index:: v93c 27 28.. index:: v00 29 30.. index:: v02 31 32.. index:: v08 33 34Unfortunately, there are many versions of the VHDL 35language, and they aren't backward compatible. 36 37The VHDL language was first standardized in 1987 by IEEE as IEEE 1076-1987, and 38is commonly referred as VHDL-87. This is certainly the most important version, 39since most of the VHDL tools are still based on this standard. 40 41Various problems of this first standard have been analyzed by experts groups 42to give reasonable ways of interpreting the unclear portions of the standard. 43 44VHDL was revised in 1993 by IEEE as IEEE 1076-1993. This revision is still 45well-known. 46 47Unfortunately, VHDL-93 is not fully compatible with VHDL-87, i.e. some perfectly 48valid VHDL-87 programs are invalid VHDL-93 programs. Here are some of the 49reasons: 50 51* the syntax of file declaration has changed (this is the most visible source 52 of incompatibility), 53* new keywords were introduced (group, impure, inertial, literal, 54 postponed, pure, reject, rol, ror, shared, sla, sll, sra, srl, 55 unaffected, xnor), 56* some dynamic behaviours have changed (the concatenation is one of them), 57* rules have been added. 58 59Shared variables were replaced by protected types in the 2000 revision of 60the VHDL standard. This modification is also known as 1076a. Note that this 61standard is not fully backward compatible with VHDL-93, since the type of a 62shared variable must now be a protected type (there was no such restriction 63before). 64 65Minor corrections were added by the 2002 revision of the VHDL standard. This 66revision is not fully backward compatible with VHDL-00 since, for example, 67the value of the `'instance_name` attribute has slightly changed. 68 69The latest version is 2008. Many features have been added, and GHDL 70doesn't implement all of them. 71 72You can select the VHDL standard expected by GHDL with the 73:option:`--std=STANDARD <--std>` option, where ``STANDARD`` is one of the list below: 74 75 7687 77 Select VHDL-87 standard as defined by IEEE 1076-1987. LRM bugs corrected by 78 later revisions are taken into account. 79 8093 81 Select VHDL-93; VHDL-87 file declarations are not accepted. 82 8393c 84 Same as 93 and :option:`-frelaxed`. 85 8600 87 Select VHDL-2000 standard, which adds protected types. 88 8902 90 Select VHDL-2002 standard. 91 9208 93 Select VHDL-2008 standard (partially implemented). 94 95Multiple standards can be used in a design: 96 97+-----+----------------+ 98|GROUP| VHDL Standard | 99+=====+================+ 100| 87 | 87 | 101+-----+----------------+ 102| 93 | 93, 93c, 00, 02| 103+-----+----------------+ 104| 08 | 08 | 105+-----+----------------+ 106 107.. note:: 108 109 The standards in each group are considered compatible: you can elaborate a design mixing these standards. However, standards of different groups are not compatible. 110 111.. _psl_implementation: 112 113PSL support 114=========== 115 116GHDL implements a subset of :wikipedia:`PSL <Property_Specification_Language>`. 117 118PSL implementation 119------------------ 120 121A PSL statement is considered as a process, so it's not allowed within 122a process. 123 124All PSL directives (`assert`, `assume`, `restrict`, `cover`) must be clocked (GHDL doesn't support unclocked directives). 125Furthermore only one clock per directive is allowed. 126 127You can either use a default clock like this: 128 129.. code-block:: VHDL 130 131 default clock is rising_edge (CLK); 132 assert always 133 a -> eventually! b; 134 135or use a clocked expression (note the use of parentheses): 136 137.. code-block:: 138 139 assert (always a -> next[3](b)) @rising_edge(clk); 140 141 142Of course only the simple subset of PSL is allowed. 143 144Currently the built-in functions are not implemented, see `issue #662 <https://github.com/ghdl/ghdl/issues/662>`_. 145PSL functions `prev()`, `stable()`, `rose()` and `fell()` are supported with GHDL synthesis. 146 147PSL usage 148--------- 149 150PSL annotations embedded in comments 151^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 152 153GHDL understands embedded PSL annotations in VHDL files: 154 155.. code-block:: VHDL 156 157 -- psl default clock is rising_edge (CLK); 158 -- psl assert always 159 -- a -> eventually! b; 160 end architecture rtl; 161 162* A PSL assertion statement must appear within a comment that starts 163 with the `psl` keyword. The keyword must be followed (on the 164 same line) by a PSL keyword such as `assert` or `default`. 165 To continue a PSL statement on the next line, just start a new comment. 166 167.. HINT:: 168 169 As PSL annotations are embedded within comments, you must analyze 170 your design with option :option:`-fpsl` to enable PSL annotations: 171 172 .. code-block:: bash 173 174 ghdl -a -fpsl vhdl_design.vhdl 175 ghdl -e vhdl_design 176 177PSL annotations (VHDL-2008 only) 178^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 179 180Since VHDL-2008 PSL is integrated in the VHDL language. You can use 181PSL in a VHDL(-2008) design without embedding it in comments. 182 183.. code-block:: VHDL 184 185 default clock is rising_edge (CLK); 186 assert always 187 a -> eventually! b; 188 end architecture rtl; 189 190.. HINT:: 191 192 You have to use the :option:`--std=08 <--std>` option: 193 194 .. code-block:: bash 195 196 ghdl -a --std=08 vhdl_design.vhdl 197 ghdl -e --std=08 vhdl_design 198 199PSL vunit files (VHDL-2008 / Synthesis only) 200^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 201 202GHDL supports vunit (Verification Unit) files. 203 204.. code-block:: 205 206 vunit vunit_name (entity_name(architecture_name)) 207 { 208 default clock is rising_edge(clk); 209 assert always cnt /= 5 abort rst; 210 } 211 212* A vunit can contain PSL and VHDL code. 213 214* It is bound to a VHDL entity or an instance of it. 215 216* The PSL vunit is in the same scope as the VHDL design it is bound 217 to. You have access to all objects (ports, types, signals) of the 218 VHDL design. 219 220.. HINT:: 221 222 The PSL vunit file has to be analyzed together with the VHDL design file, for example: 223 224 .. code-block:: bash 225 226 ghdl -a --std=08 vhdl_design.vhdl vunit.psl 227 228 Or when using the `--synth` command: 229 230 .. code-block:: bash 231 232 ghdl --synth --std=08 vhdl_design.vhdl vunit.psl -e vhdl_design 233 234 235Source representation 236===================== 237 238According to the VHDL standard, design units (i.e. entities, 239architectures, packages, package bodies, and configurations) may be 240independently analyzed. 241 242Several design units may be grouped into a design file. 243 244In GHDL, a system file represents a design file. That is, a file compiled by 245GHDL may contain one or more design units. 246 247It is common to have several design units in a design file. 248 249GHDL does not impose any restriction on the name of a design file 250(except that the filename may not contain any control character or 251spaces). 252 253GHDL does not keep a binary representation of the design units analyzed like 254other VHDL analyzers. The sources of the design units are re-read when 255needed (for example, an entity is re-read when one of its architectures is 256analyzed). Therefore, if you delete or modify a source file of a unit 257analyzed, GHDL will refuse to use it. 258 259.. _Library_database: 260 261Library database 262================ 263 264Each design unit analyzed is placed into a design library. By default, 265the name of this design library is ``work``; however, this can be 266changed with the :option:`--work` option of GHDL. 267 268To keep the list of design units in a design library, GHDL creates 269library files. The name of these files is :file:`<LIB_NAME>-obj<GROUP>.cf`, where 270`<LIB_NAME>` is the name of the library, and `<GROUP>` the VHDL version (87, 27193 or 08) used to analyze the design units. 272 273For details on ``GROUP`` values see section :ref:`VHDL_standards`. 274 275You don't have to know how to read a library file. You can display it 276using the *-d* of `ghdl`. The file contains the name of the 277design units, as well as the location and the dependencies. 278 279The format may change with the next version of GHDL. 280 281.. _Top_entity: 282 283Top entity 284========== 285 286There are some restrictions on the entity being at the apex of a design 287hierarchy: 288 289* The generic must have a default value, and the value of a generic is its 290 default value. 291* The ports type must be constrained. 292 293Using vendor libraries 294====================== 295 296Many vendors libraries have been analyzed with `GHDL`. There are usually no problems. Be sure to use the 297:option:`--work` option. However, some problems have been encountered. `GHDL` follows the `VHDL` LRM (the manual which 298defines `VHDL`) more strictly than other `VHDL` tools. You could try to relax the restrictions by using the 299:option:`--std=93c <--std>`, :option:`-fexplicit`, :option:`-frelaxed-rules` and 300:option:`--warn-no-vital-generic <--warn-vital-generic>`. 301