1--  Instantiation synthesis.
2--  Copyright (C) 2019 Tristan Gingold
3--
4--  This file is part of GHDL.
5--
6--  This program is free software; you can redistribute it and/or modify
7--  it under the terms of the GNU General Public License as published by
8--  the Free Software Foundation; either version 2 of the License, or
9--  (at your option) any later version.
10--
11--  This program is distributed in the hope that it will be useful,
12--  but WITHOUT ANY WARRANTY; without even the implied warranty of
13--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14--  GNU General Public License for more details.
15--
16--  You should have received a copy of the GNU General Public License
17--  along with this program; if not, write to the Free Software
18--  Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19--  MA 02110-1301, USA.
20
21with Vhdl.Nodes; use Vhdl.Nodes;
22
23with Synth.Context; use Synth.Context;
24with Synth.Flags; use Synth.Flags;
25
26package Synth.Insts is
27   --  Create the declaration of the top entity.
28   procedure Synth_Top_Entity (Global_Instance : Synth_Instance_Acc;
29                               Arch : Node;
30                               Config : Node;
31                               Encoding : Name_Encoding;
32                               Inst : out Synth_Instance_Acc);
33
34   --  Synthesize the top entity and all the sub-modules.
35   procedure Synth_All_Instances;
36
37   --  Apply block configuration CFG to BLK.
38   --  Must be done before synthesis of BLK.
39   --  The synthesis of BLK will clear all configuration of it.
40   procedure Apply_Block_Configuration (Cfg : Node; Blk : Node);
41
42   procedure Synth_Design_Instantiation_Statement
43     (Syn_Inst : Synth_Instance_Acc; Stmt : Node);
44   procedure Synth_Blackbox_Instantiation_Statement
45     (Syn_Inst : Synth_Instance_Acc; Stmt : Node);
46
47   procedure Synth_Component_Instantiation_Statement
48     (Syn_Inst : Synth_Instance_Acc; Stmt : Node);
49end Synth.Insts;
50