1 2library ieee; 3use ieee.std_logic_1164.all; 4use ieee.numeric_std.all; 5 6entity tb_test is end; 7 8architecture arch_tb of tb_test is 9-- signal reset_s, clk_s : std_logic; 10 signal i_s : integer := -1; 11-- signal j_s : integer := -2; 12 -- Here, as it should, an error will be raised during compilation 13-- signal u_s : unsigned(7 downto 0) := to_unsigned(-1, 8); 14 -- 15 signal v_s : unsigned(7 downto 0); 16-- signal w_s : unsigned(7 downto 0); 17begin 18 -- Here, as it should, a bound check failure will be raised during simulation 19-- w_s <= to_unsigned(j_s, 8); 20 -- 21 -- Here it won't have any error during simulation, but it should 22 v_s <= to_unsigned(i_s, 8); 23 -- 24end architecture arch_tb; 25