1------------------------------------------------
2--!  Test intent : Procedure calls with signals parameters.
3--!  Test scope  : Checking activity with  'active
4--!  Keywords    : [procedure, parameters, signal]
5--!  References  : [VH2000 1.1:]
6--!                [Rlink REQ00:2.1.1.2.1]
7--!                [Rlink REQ00:2.1.1.2.4]
8--
9-------------------------------------------------
10--  'active
11--
12library ieee;
13use ieee.std_logic_1164.all;
14use ieee.std_logic_unsigned.all;
15use work.subs_pkg.all;
16use work.proc_pkg.all;
17use work.all;
18
19entity pf7 is
20end entity;
21
22architecture tb of pf7 is
23
24  signal tclk : std_logic := '0';
25  signal trst : std_logic := '0';
26  signal tper : integer := 1;
27
28  signal u1_in:  std_logic_vector(7 downto 0);
29  signal u1_out: std_logic_vector(7 downto 0);
30  signal u2_in:  std_logic_vector(7 downto 0);
31  signal u2_out: std_logic_vector(7 downto 0);
32
33  signal gen_out : std_logic_vector(15 downto 0);
34
35  signal mems : arr_marr_t;
36
37  signal mem_if_in : ctl_if_t;
38  signal mem_if_out : rsp_if_t;
39  signal mon_if_in : ctl_if_t;
40  signal mon_if_out : rsp_if_t;
41  signal ackm : std_logic;
42
43  signal sig_act : boolean;
44
45begin
46
47  act_mon(mem_if_in, mem_if_out, sig_act);
48
49  process(mem_if_in)
50  begin
51    for i in mem_if_in.d1'range loop
52      if mem_if_in.d1(i)'active then
53        report "Bit : " & integer'image(i) & " is active";
54      end if;
55    end loop;
56  end process;
57
58  -- clock
59  clock: process
60  begin
61    tclk <= '0';
62    wait for 1 ns;
63    tclk <= '1';
64    wait for 1 ns;
65  end process;
66
67  sim_ctl: process
68    variable v_cnt : integer := 0;
69  begin
70    while v_cnt < 5 loop
71      v_cnt := v_cnt + 1;
72      --report "Tick ...";
73      wait until tclk'event and tclk = '1';
74    end loop;
75    report "Passed, END SIM ..." severity failure;
76  end process;
77
78  -- generate some data
79  dgen: process(tclk)
80    variable vec : bit_vector(15 downto 0) := (others => '1');
81  begin
82    if tclk'event and tclk = '1' then
83      vec := klsfr(vec);
84      --report bv2str(vec);
85      gen_out <= to_stdlogicvector(vec);
86      u1_in  <= to_stdlogicvector(vec(7 downto 0));
87      u2_in  <= to_stdlogicvector(vec(15 downto 8));
88    end if;
89  end process;
90
91  --  memory access process
92  mem_acc: process
93    variable addr : std_logic_vector(15 downto 0) := (others => '0');
94    variable idx : integer;
95    variable  init : integer := 0;
96    variable v_tmp_dat : std_logic_vector(63 downto 0);
97  begin
98    if init = 0 then
99      for i in 3 downto 0 loop
100        for j in marr_t'range loop
101          mems(i)(j) <= (others => '0');
102          wait for 0 ps;
103        end loop;
104      end loop;
105      report "Done.";
106      wait for 0 ps;
107      for i in 3 downto 0 loop
108        for j in marr_t'range loop
109          assert kslv2int(mems(i)(j)) = 0
110            report "ERROR: Ram not initialized"
111            severity failure;
112        end loop;
113      end loop;
114      mem_if_in.d1 <= (others => '0');
115      init := 1;
116
117    elsif tclk'event and tclk = '1' then
118      mem_access(mem_if_in, mem_if_out, mems, ackm);
119      mem_if_in.wr <= '0';
120      mem_access(mem_if_in, mem_if_out, mems, ackm);
121      --report "Active Drive state: " & slv2str(active_bits(mem_if_out.do));
122      --report "Inactive outputs Drive state: " & slv2str(active_bits(mem_if_out.do1));
123      wait for 0 ps;
124      --report "Inactive Drive state: " & slv2str(active_bits(mem_if_out.do));
125      --report "Data: " & slv2str(mem_if_out.do);
126      if now > 2 ns then
127        assert v_tmp_dat(63 downto 16) = mem_if_out.do(63 downto 16)
128          report "Error:  data missmatch on read ..."
129          severity failure;
130      end if;
131    elsif tclk'event and tclk = '0' then
132      mem_if_in.a1 <= addr;
133      mem_if_in.wr <= '1';
134      addr := addr + 16#0001#;
135      --report "Address: " & slv2str(addr);
136      mem_if_in.di <= gen_out & gen_out(7 downto 0) & gen_out(15 downto 8) & gen_out & gen_out;
137      v_tmp_dat := gen_out & gen_out(7 downto 0) & gen_out(15 downto 8) & gen_out & gen_out;
138
139      -- generate events on ctl.d1
140      wait for 2 ps;
141      if now > 2 ns then
142        for i in mem_if_in.d1'range loop
143          mem_if_in.d1(i) <= not mem_if_in.d1(i);
144          wait for 0 ps;
145        end loop;
146        report slv2str(mem_if_in.d1);
147      end if;
148    end if;
149    wait on tclk;
150  end process;
151
152end tb;
153