1library ieee; 2use ieee.std_logic_1164.all; 3 4 5library ieee; 6use ieee.numeric_std.all; 7 8entity decis_levl is 9 port ( 10 clk : in std_logic; 11 ra0_data : out std_logic_vector(31 downto 0); 12 ra0_addr : in std_logic_vector(4 downto 0) 13 ); 14end decis_levl; 15architecture augh of decis_levl is 16 17 -- Embedded RAM 18 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); 20 signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", "00000000000000000000001101110000", "00000000000000000000010010110000", "00000000000000000000010111110000", "00000000000000000000011101001000", "00000000000000000000100010100000", "00000000000000000000101000011000", "00000000000000000000101110010000", "00000000000000000000110100110000", "00000000000000000000111011001000", "00000000000000000001000010010000", "00000000000000000001001001011000", "00000000000000000001010001010000", "00000000000000000001011001010000", "00000000000000000001100010010000", "00000000000000000001101011010000", "00000000000000000001110101100000", "00000000000000000001111111111000", "00000000000000000010001100001000", "00000000000000000010011000011000", "00000000000000000010100111011000", "00000000000000000010110110010000", "00000000000000000011001001100000", "00000000000000000011011100101000", "00000000000000000011110111100000", "00000000000000000100010010011000", "00000000000000000100111111101000", "00000000000000000101101100111000", "00000000000000000111111111111111", "00000000000000000000000000000000", "00000000000000000000000000000000"); 21 22 23 -- Little utility functions to make VHDL syntactically correct 24 -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. 25 -- This happens when accessing arrays with <= 2 cells, for example. 26 27 function to_integer(B: std_logic) return integer is 28 variable V: std_logic_vector(0 to 0); 29 begin 30 V(0) := B; 31 return to_integer(unsigned(V)); 32 end; 33 34 function to_integer(V: std_logic_vector) return integer is 35 begin 36 return to_integer(unsigned(V)); 37 end; 38 39begin 40 41 -- The component is a ROM. 42 -- There is no Write side. 43 44 -- The Read side (the outputs) 45 46 ra0_data <= ram( to_integer(ra0_addr) ); 47 48end architecture; 49