1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4-- library std;
5use std.textio.all;
6
7entity morten is
8end entity;
9
10architecture foo of morten is
11
12    signal clk: std_logic := '0';
13    signal rst: std_logic := '1';
14    signal cnt_1: unsigned (7 downto 0);
15    signal cnt_3: unsigned (7 downto 0);
16
17    function to_bstring(sl : std_logic) return string is
18    begin
19      return "" & std_logic'image(sl)(2);  -- "" & character to get string
20    end function;
21
22    function to_bstring(slv : std_logic_vector) return string is
23      alias slv_norm : std_logic_vector(1 to slv'length) is slv;
24    begin
25      if slv_norm'length = 0 then
26        return "";
27      elsif slv_norm'length = 1 then
28        return to_bstring(slv_norm(1));
29      else  -- slv_norm'length > 0
30        return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
31      end if;
32    end function;
33
34begin
35
36
37PRINT:
38    process (clk) is
39        variable line_v   : line;
40        file     out_file : text open write_mode is "out.txt";
41    begin
42        if rising_edge(clk) then
43            write(line_v, to_bstring(rst) & " " &
44                          to_bstring(std_logic_vector(cnt_1)) & " " &
45                          to_bstring(std_logic_vector(cnt_3))
46                 );
47            writeline(out_file, line_v);
48      end if;
49    end process;
50
51COUNTER1:
52    process (clk,rst)
53    begin
54        if rst = '1' then
55            cnt_1 <= (others => '0');
56        elsif rising_edge(clk) then
57            cnt_1 <= cnt_1 + 1;
58        end if;
59    end process;
60
61COUNTER3:
62    process (clk,rst)
63    begin
64        if rst = '1' then
65            cnt_3 <= (others => '0');
66        elsif rising_edge(clk) then
67            cnt_3 <= cnt_3 + 3;
68        end if;
69    end process;
70
71RESET:
72    process
73    begin
74        wait until rising_edge(clk);
75        wait until rising_edge(clk);
76        wait until rising_edge(clk);
77        rst <= '0';
78        wait;
79    end process;
80
81CLOCK:
82    process
83    begin
84        wait for 10 ns;
85        clk <= not clk;
86        if Now > 210 ns then
87            wait;
88        end if;
89    end process;
90
91end architecture;