1-- ent.vhd 2library ieee; 3use ieee.std_logic_1164.all; 4use ieee.numeric_std_unsigned.all; 5 6entity ent is 7 port ( 8 clk_i : in std_logic; 9 done_o : out std_logic 10 ); 11end entity ent; 12 13architecture synthesis of ent is 14 signal u0 : std_logic_vector(2 downto 0) := "101"; 15begin 16 done_o <= '0'; 17end architecture synthesis; 18