1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ap_a_fg_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27-- code from book
28
29library ieee;  use ieee.std_logic_1164.all;
30
31               entity bidir_buffer is
32                 port ( bidir : inout std_logic;
33                        ena : in std_ulogic;
34                        going_out : in std_ulogic;
35                        coming_in : out std_ulogic );
36               end entity bidir_buffer;
37
38--------------------------------------------------
39
40               architecture behavior of bidir_buffer is
41               begin
42                 bidir <= going_out when ena = '1' else
43                          'Z';
44                 coming_in <= bidir;
45               end architecture behavior;
46
47-- end code from book
48
49
50
51               entity fg_a_07 is
52               end entity fg_a_07;
53
54
55               library ieee;  use ieee.std_logic_1164.all;
56
57               architecture test of fg_a_07 is
58
59                 signal bidir : std_logic;
60                 signal ena, going_out, coming_in : std_ulogic;
61
62               begin
63
64                 dut : entity work.bidir_buffer
65                   port map ( bidir, ena, going_out, coming_in );
66
67                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
68
69                 going_out <= '0', '1' after 20 ns;
70
71                 bidir <= 'Z', '0' after 40 ns, '1' after 50 ns, 'Z' after 60 ns;
72
73               end architecture test;
74