1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ 23-- $Revision: 1.1.1.1 $ 24-- 25-- --------------------------------------------------------------------- 26 27entity add_1 is 28 port ( d0, d1, d2, d3 : in bit; 29 y0, y1, y2, y3 : out bit ); 30end entity add_1; 31 32 33architecture boolean_eqn of add_1 is 34begin 35 36 y0 <= not d0 after 4 ns; 37 38 y1 <= (not d1 and d0) 39 or (d1 and not d0) after 4 ns; 40 41 y2 <= (not d2 and d1 and d0) 42 or (d2 and not (d1 and d0)) after 4 ns; 43 44 y3 <= (not d3 and d2 and d1 and d0) 45 or (d3 and not (d2 and d1 and d0)) after 4 ns; 46 47end architecture boolean_eqn; 48 49 50entity buf4 is 51 port ( a0, a1, a2, a3 : in bit; 52 y0, y1, y2, y3 : out bit ); 53end entity buf4; 54 55 56architecture basic of buf4 is 57begin 58 59 y0 <= a0 after 2 ns; 60 y1 <= a1 after 2 ns; 61 y2 <= a2 after 2 ns; 62 y3 <= a3 after 2 ns; 63 64end architecture basic; 65 66 67package counter_types is 68 69 subtype digit is bit_vector(3 downto 0); 70 71end package counter_types; 72 73