1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27architecture behavioral of synch_sr_ff is
28begin
29
30  behavior : process (clk) is
31
32                             constant Tpd_clk_out : time := 3 ns;
33
34  begin
35    if rising_edge(clk) then
36      if To_X01(clr) = '1' then
37        q <= '0' after Tpd_clk_out;
38      elsif To_X01(set) = '1' then
39        q <= '1' after Tpd_clk_out;
40      end if;
41    end if;
42  end process behavior;
43
44end architecture behavioral;
45