1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
23-- $Revision: 1.3 $
24--
25-- ---------------------------------------------------------------------
26
27entity nand3 is
28  generic ( Tpd : delay_length );
29  port ( a, b, c : in bit;  y : out bit );
30end entity nand3;
31
32architecture basic of nand3 is
33begin
34  y <= not (a and b and c) after Tpd;
35end architecture basic;
36
37
38library project_lib;
39library stimulus;
40use stimulus.stimulus_generators.all;
41
42entity misc_logic is
43end entity misc_logic;
44
45-- code from book
46
47architecture gate_level of misc_logic is
48
49  component nand3 is
50                    generic ( Tpd : delay_length );
51                  port ( a, b, c : in bit;  y : out bit );
52  end component nand3;
53
54  for all : nand3
55    use entity project_lib.nand3(basic);
56
57  -- . . .
58
59  -- not in book
60  signal sig1, sig2, sig3, out_sig : bit;
61  signal test_vector : bit_vector(1 to 3);
62  -- end not in book
63
64begin
65
66  gate1 : component nand3
67    generic map ( Tpd => 2 ns )
68    port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
69
70  -- . . .
71
72  -- not in book
73
74  all_possible_values(test_vector, 10 ns);
75
76  (sig1, sig2, sig3) <= test_vector;
77
78  -- end not in book
79
80end architecture gate_level;
81
82-- end code from book
83