1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ch_14_fg_14_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27library ieee;  use ieee.std_logic_1164.all;
28
29               entity ms_flipflop is
30                 port ( phi1, phi2 : in std_logic;
31                        d : in std_logic;
32                        q : out std_logic );
33               end entity ms_flipflop;
34
35
36               architecture normal_drive of ms_flipflop is
37                 signal master_d : std_logic;
38               begin
39                 master_d <= d when phi1 = '1';
40                 q <= master_d when phi2 = '1';
41               end architecture normal_drive;
42
43
44               architecture high_drive of ms_flipflop is
45                 signal master_d : std_logic;
46               begin
47                 master_d <= d when phi1 = '1';
48                 q <= master_d when phi2 = '1';
49               end architecture high_drive;
50
51
52
53-- code from book
54
55               library cell_lib;
56
57               configuration last_high_drive of shift_reg is
58
59                 for cell_level
60
61                   -- workaround for MTI bug mt026
62                   -- for reg_array ( 0 to parallel_data'length - 2 )
63                   for reg_array ( 0 to 2 )
64                   -- end workaround
65
66                   for first_cell
67                   for cell : master_slave_flipflop
68                   use entity cell_lib.ms_flipflop(normal_drive);
69               end for;
70               end for;
71
72               for other_cell
73                 for cell : master_slave_flipflop
74                 use entity cell_lib.ms_flipflop(normal_drive);
75               end for;
76               end for;
77
78               end for;
79
80               -- workaround for MTI bug mt026
81               -- for reg_array ( parallel_data'length - 1 )
82               for reg_array ( 3 )
83                 -- end workaround
84
85                 for other_cell
86                 for cell : master_slave_flipflop
87                 use entity cell_lib.ms_flipflop(high_drive);
88               end for;
89               end for;
90
91               end for;
92
93               end for;
94
95               end configuration last_high_drive;
96
97-- end code from book
98
99
100               library ieee;  use ieee.std_logic_1164.all;
101
102               entity fg_14_13 is
103               end entity fg_14_13;
104
105
106               architecture test of fg_14_13 is
107
108                 signal phi1, phi2, serial_data_in : std_logic := '0';
109                 signal parallel_data : std_logic_vector(3 downto 0);
110
111               begin
112
113                 dut : configuration work.last_high_drive
114                   port map ( phi1 => phi1, phi2 => phi2,
115                              serial_data_in => serial_data_in,
116                              parallel_data => parallel_data );
117
118                 clock_gen : process is
119                 begin
120                   phi1 <= '1', '0' after 4 ns;
121                   phi2 <= '1' after 5 ns, '0' after 9 ns;
122                   wait for 10 ns;
123                 end process clock_gen;
124
125                 stimulus : process is
126                 begin
127                   serial_data_in <= '0';  wait until phi2 = '1';
128                   serial_data_in <= '1';  wait until phi2 = '1';
129                   serial_data_in <= '1';  wait until phi2 = '1';
130                   serial_data_in <= '0';  wait until phi2 = '1';
131                   serial_data_in <= '1';  wait until phi2 = '1';
132                   serial_data_in <= '1';  wait until phi2 = '1';
133                   serial_data_in <= '0';  wait until phi2 = '1';
134                   serial_data_in <= '1';  wait until phi2 = '1';
135                   serial_data_in <= '1';  wait until phi2 = '1';
136                   serial_data_in <= '0';  wait until phi2 = '1';
137                   serial_data_in <= '1';  wait until phi2 = '1';
138                   serial_data_in <= '1';  wait until phi2 = '1';
139                   serial_data_in <= '0';  wait until phi2 = '1';
140                   serial_data_in <= '1';  wait until phi2 = '1';
141                   serial_data_in <= '1';  wait until phi2 = '1';
142                   serial_data_in <= '0';
143
144                   wait;
145                 end process stimulus;
146
147               end architecture test;
148