1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ 23-- $Revision: 1.3 $ 24-- 25-- --------------------------------------------------------------------- 26 27use work.alu_types.all, 28 work.reg_file_types.all; 29 30architecture rtl of dlx is 31 32 component alu is 33 port ( s1 : in dlx_word; 34 s2 : in dlx_word; 35 result : out dlx_word; 36 func : in alu_func; 37 zero, negative, overflow : out std_logic ); 38 end component alu; 39 40 component reg_file is 41 port ( a1 : in reg_file_addr; 42 q1 : out dlx_word; 43 a2 : in reg_file_addr; 44 q2 : out dlx_word; 45 a3 : in reg_file_addr; 46 d3 : in dlx_word; 47 write_en : in std_logic ); 48 end component reg_file; 49 50 component latch is 51 port ( d : in dlx_word; 52 q : out dlx_word; 53 latch_en : in std_logic ); 54 end component latch; 55 56 component ir_extender is 57 port ( d : in dlx_word; 58 q : out dlx_word; 59 immed_size_26 : in std_logic; 60 immed_unsigned : in std_logic; 61 immed_en : in std_logic ); 62 end component ir_extender; 63 64 component reg_multiple_out is 65 generic ( num_outputs : positive ); 66 port ( d : in dlx_word; 67 q : out dlx_word_array(1 to num_outputs); 68 latch_en : in std_logic; 69 out_en : in std_logic_vector(1 to num_outputs) ); 70 end component reg_multiple_out; 71 72 component reg_multiple_plus_one_out is 73 generic ( num_outputs : positive ); 74 port ( d : in dlx_word; 75 q0 : out dlx_word; 76 q : out dlx_word_array(1 to num_outputs); 77 latch_en : in std_logic; 78 out_en : in std_logic_vector(1 to num_outputs) ); 79 end component reg_multiple_plus_one_out; 80 81 component reg_multiple_plus_one_out_reset is 82 generic ( num_outputs : positive ); 83 port ( d : in dlx_word; 84 q0 : out dlx_word; 85 q : out dlx_word_array(1 to num_outputs); 86 latch_en : in std_logic; 87 out_en : in std_logic_vector(1 to num_outputs); 88 reset : in std_logic ); 89 end component reg_multiple_plus_one_out_reset; 90 91 component mux2 is 92 port ( i0, i1 : in dlx_word; 93 y : out dlx_word; 94 sel : in std_logic); 95 end component mux2; 96 97 component controller is 98 port ( phi1, phi2 : in std_logic; 99 reset : in std_logic; 100 halt : out std_logic; 101 width : out dlx_mem_width; 102 write_enable : out std_logic; 103 mem_enable : out std_logic; 104 ifetch : out std_logic; 105 ready : in std_logic; 106 alu_in_latch_en : out std_logic; 107 alu_function : out alu_func; 108 alu_zero, alu_negative, alu_overflow : in std_logic; 109 reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr; 110 reg_write : out std_logic; 111 c_latch_en : out std_logic; 112 a_latch_en, a_out_en : out std_logic; 113 b_latch_en, b_out_en : out std_logic; 114 temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic; 115 iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic; 116 pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic; 117 mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic; 118 mem_addr_mux_sel : out std_logic; 119 mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic; 120 mdr_mux_sel : out std_logic; 121 ir_latch_en : out std_logic; 122 ir_immed1_size_26, ir_immed2_size_26 : out std_logic; 123 ir_immed1_unsigned, ir_immed2_unsigned : out std_logic; 124 ir_immed1_en, ir_immed2_en : out std_logic; 125 current_instruction : in dlx_word; 126 mem_addr : std_logic_vector(1 downto 0); 127 const1, const2 : out dlx_word ); 128 end component controller; 129 130 131 signal s1_bus, s2_bus : dlx_word; 132 signal dest_bus : dlx_word; 133 signal alu_in1, alu_in2 : dlx_word; 134 signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word; 135 signal mdr_in : dlx_word; 136 signal current_instruction : dlx_word; 137 signal pc_to_mem : dlx_address; 138 signal mar_to_mem : dlx_address; 139 140 signal alu_in_latch_en : std_logic; 141 signal alu_function : alu_func; 142 signal alu_zero, alu_negative, alu_overflow : std_logic; 143 signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr; 144 signal reg_write : std_logic; 145 signal a_out_en, a_latch_en : std_logic; 146 signal b_out_en, b_latch_en : std_logic; 147 signal c_latch_en : std_logic; 148 signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic; 149 signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic; 150 signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic; 151 signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic; 152 signal mem_addr_mux_sel : std_logic; 153 signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic; 154 signal mdr_mux_sel : std_logic; 155 signal ir_latch_en : std_logic; 156 signal ir_immed1_size_26, ir_immed2_size_26 : std_logic; 157 signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic; 158 signal ir_immed1_en, ir_immed2_en : std_logic; 159 160begin 161 162 alu_s1_reg : component latch 163 port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en ); 164 165 alu_s2_reg : component latch 166 port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en ); 167 168 the_alu : component alu 169 port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus, 170 func => alu_function, 171 zero => alu_zero, negative => alu_negative, overflow => alu_overflow ); 172 173 the_reg_file : component reg_file 174 port map ( a1 => reg_s1_addr, q1 => reg_file_out1, 175 a2 => reg_s2_addr, q2 => reg_file_out2, 176 a3 => reg_dest_addr, d3 => reg_file_in, 177 write_en => reg_write ); 178 179 c_reg : component latch 180 port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en ); 181 182 a_reg : component reg_multiple_out 183 generic map ( num_outputs => 1 ) 184 port map ( d => reg_file_out1, q(1) => s1_bus, 185 latch_en => a_latch_en, out_en(1) => a_out_en ); 186 187 b_reg : component reg_multiple_out 188 generic map ( num_outputs => 1 ) 189 port map ( d => reg_file_out2, q(1) => s2_bus, 190 latch_en => b_latch_en, out_en(1) => b_out_en ); 191 192 temp_reg : component reg_multiple_out 193 generic map ( num_outputs => 2 ) 194 port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, 195 latch_en => temp_latch_en, 196 out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 ); 197 198 iar_reg : component reg_multiple_out 199 generic map ( num_outputs => 2 ) 200 port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, 201 latch_en => iar_latch_en, 202 out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 ); 203 204 pc_reg : component reg_multiple_plus_one_out_reset 205 generic map ( num_outputs => 2 ) 206 port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem, 207 latch_en => pc_latch_en, 208 out_en(1) => pc_out_en1, out_en(2) => pc_out_en2, 209 reset => reset ); 210 211 mar_reg : component reg_multiple_plus_one_out 212 generic map ( num_outputs => 2 ) 213 port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem, 214 latch_en => mar_latch_en, 215 out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 ); 216 217 mem_addr_mux : component mux2 218 port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a, 219 sel => mem_addr_mux_sel ); 220 221 mdr_reg : component reg_multiple_out 222 generic map ( num_outputs => 3 ) 223 port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d, 224 latch_en => mdr_latch_en, 225 out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2, 226 out_en(3) => mdr_out_en3 ); 227 228 mdr_mux : component mux2 229 port map ( i0 => dest_bus, i1 => d, y => mdr_in, 230 sel => mdr_mux_sel ); 231 232 instr_reg : component latch 233 port map ( d => d, q => current_instruction, 234 latch_en => ir_latch_en ); 235 236 ir_extender1 : component ir_extender 237 port map ( d => current_instruction, q => s1_bus, 238 immed_size_26 => ir_immed1_size_26, 239 immed_unsigned => ir_immed1_unsigned, 240 immed_en => ir_immed1_en ); 241 242 ir_extender2 : component ir_extender 243 port map ( d => current_instruction, q => s2_bus, 244 immed_size_26 => ir_immed2_size_26, 245 immed_unsigned => ir_immed2_unsigned, 246 immed_en => ir_immed2_en ); 247 248 the_controller : component controller 249 port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt, 250 width => width, write_enable => write_enable, mem_enable => mem_enable, 251 ifetch => ifetch, ready => ready, 252 alu_in_latch_en => alu_in_latch_en, alu_function => alu_function, 253 alu_zero => alu_zero, alu_negative => alu_negative, 254 alu_overflow => alu_overflow, 255 reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr, 256 reg_dest_addr => reg_dest_addr, reg_write => reg_write, 257 c_latch_en => c_latch_en, 258 a_latch_en => a_latch_en, a_out_en => a_out_en, 259 b_latch_en => b_latch_en, b_out_en => b_out_en, 260 temp_latch_en => temp_latch_en, 261 temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2, 262 iar_latch_en => iar_latch_en, 263 iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2, 264 pc_latch_en => pc_latch_en, 265 pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2, 266 mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en, 267 mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2, 268 mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en, 269 mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2, 270 mdr_out_en3 => mdr_out_en3, 271 ir_latch_en => ir_latch_en, 272 ir_immed1_size_26 => ir_immed1_size_26, 273 ir_immed2_size_26 => ir_immed2_size_26, 274 ir_immed1_unsigned => ir_immed1_unsigned, 275 ir_immed2_unsigned => ir_immed2_unsigned, 276 ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en, 277 current_instruction => current_instruction, 278 mem_addr => mar_to_mem(1 downto 0), 279 const1 => s1_bus, const2 => s2_bus ); 280 281end architecture rtl; 282