1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ch_16_fg_16_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27architecture detailed_timing of counter is
28
29  signal reset_ipd,                   -- data input port delayed
30    clk_ipd : bit;               -- clock input port delayed
31  signal q_zd : bit_vector(q'range);  -- q output with zero delay
32
33begin
34
35  input_port_delay : block is
36  begin
37    reset_ipd <= reset after tipd_reset;
38    clk_ipd <= clk after tipd_clk;
39  end block input_port_delay;
40
41  functionality : block is
42
43                          function increment ( bv : bit_vector ) return bit_vector is
44    variable result : bit_vector(bv'range) := bv;
45    variable carry : bit := '1';
46  begin
47    for index in result'reverse_range loop
48      result(index) := bv(index) xor carry;
49      carry :=  bv(index) and carry;
50      exit when carry = '0';
51    end loop;
52    return result;
53  end function increment;
54
55  signal next_count : bit_vector(q'range);
56
57  begin
58    next_count <= increment(q_zd) when reset_ipd = '0' else
59                  (others => '0');
60    q_zd <= next_count when clk_ipd = '1' and clk_ipd'event;
61  end block functionality;
62
63  output_port_delay : block is
64  begin
65    q <= q_zd after topd_q;
66  end block output_port_delay;
67
68  timing_checks : block is
69  begin
70    -- check setup time: reset before clk
71    -- . . .
72    -- check hold time: reset after clk
73    -- . . .
74  end block timing_checks;
75
76end architecture detailed_timing;
77
78
79-- not in book
80
81entity fg_16_13 is
82end entity fg_16_13;
83
84
85architecture test of fg_16_13 is
86
87  signal reset, clk : bit := '0';
88  signal q : bit_vector(3 downto 0);
89
90begin
91
92  dut : entity work.counter(detailed_timing)
93    generic map ( tipd_reset => 2 ns,
94                  tipd_clk => 3 ns,
95                  topd_q => 4 ns,
96                  tsetup_reset => 3 ns,
97                  thold_reset => 1 ns )
98    port map ( reset => reset, clk => clk, q => q );
99
100  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
101
102  reset <= '1' after 62 ns, '0' after 106 ns;
103
104end architecture test;
105
106-- end not in book
107