1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ 23-- $Revision: 1.2 $ 24-- 25-- --------------------------------------------------------------------- 26 27entity circuit is 28 generic ( inpad_delay, outpad_delay : delay_length ); 29 port ( in1, in2, in3 : in bit; out1, out2 : out bit ); 30end entity circuit; 31 32-------------------------------------------------- 33 34architecture with_pad_delays of circuit is 35 36 component subcircuit is 37 port ( a, b : in bit; y1, y2 : out bit ); 38 end component subcircuit; 39 40 signal delayed_in1, delayed_in2, delayed_in3 : bit; 41 signal undelayed_out1, undelayed_out2 : bit; 42 43begin 44 45 input_delays : block is 46 begin 47 delayed_in1 <= in1 after inpad_delay; 48 delayed_in2 <= in2 after inpad_delay; 49 delayed_in3 <= in3 after inpad_delay; 50 end block input_delays; 51 52 functionality : block is 53 signal intermediate : bit; 54 begin 55 cell1 : component subcircuit 56 port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate ); 57 cell2 : component subcircuit 58 port map ( intermediate, delayed_in3, undelayed_out2, open ); 59 end block functionality; 60 61 output_delays : block is 62 begin 63 out1 <= undelayed_out1 after outpad_delay; 64 out2 <= undelayed_out2 after outpad_delay; 65 end block output_delays; 66 67end architecture with_pad_delays; 68