1 2-- Copyright (C) 2001 Bill Billowitch. 3 4-- Some of the work to develop this test suite was done with Air Force 5-- support. The Air Force and Bill Billowitch assume no 6-- responsibilities for this software. 7 8-- This file is part of VESTs (Vhdl tESTs). 9 10-- VESTs is free software; you can redistribute it and/or modify it 11-- under the terms of the GNU General Public License as published by the 12-- Free Software Foundation; either version 2 of the License, or (at 13-- your option) any later version. 14 15-- VESTs is distributed in the hope that it will be useful, but WITHOUT 16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18-- for more details. 19 20-- You should have received a copy of the GNU General Public License 21-- along with VESTs; if not, write to the Free Software Foundation, 22-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 24-- --------------------------------------------------------------------- 25-- 26-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $ 27-- $Revision: 1.2 $ 28-- 29-- --------------------------------------------------------------------- 30 31ENTITY c01s01b01x02p10n01i00778ent_a IS 32 port ( c1 : linkage integer; 33 c2 : linkage integer; 34 c3 : linkage integer; 35 c4 : linkage integer; 36 c5 : linkage integer); 37END c01s01b01x02p10n01i00778ent_a; 38 39ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS 40 41BEGIN 42 test : process 43 begin 44 wait; 45 end process test; 46END c01s01b01x02p10n01i00778arch_a; 47 48 49 50ENTITY c01s01b01x02p10n01i00778ent IS 51 port (p1 : in integer; 52 p2 : out integer; 53 p3 : inout integer; 54 p4 : buffer integer; 55 p5 : linkage integer); 56END c01s01b01x02p10n01i00778ent; 57 58ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS 59 component c01s01b01x02p10n01i00778ent_b 60 port ( c1 : linkage integer; 61 c2 : linkage integer; 62 c3 : linkage integer; 63 c4 : linkage integer; 64 c5 : linkage integer); 65 end component; 66 for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a); 67BEGIN 68 L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success 69 TESTING: PROCESS 70 BEGIN 71 assert FALSE 72 report "***PASSED TEST: c01s01b01x02p10n01i00778" 73 severity NOTE; 74 wait; 75 END PROCESS TESTING; 76 77END c01s01b01x02p10n01i00778arch; 78