1**fdspec01.v(105) WARN** [653] $period timing check min:typ:max limit expression needs parentheses under 1364 - unportable
2  There are 1 top level modules.
3... printing drivers and loads for test.t_clr0:
4  Loads:
5   Port (vpiHighConn) object at **fdspec01.v(6)
6... printing drivers and loads for test.t_clr1:
7  Loads:
8   Port (vpiHighConn) object at **fdspec01.v(7)
9... printing drivers and loads for test.t_d0:
10  Loads:
11   Port (vpiHighConn) object at **fdspec01.v(6)
12... printing drivers and loads for test.t_d1:
13  Loads:
14   Port (vpiHighConn) object at **fdspec01.v(7)
15... printing drivers and loads for test.t_q:
16  Drivers:
17   Port (vpiHighConn) object at **fdspec01.v(8)
18... printing drivers and loads for test.t_q0:
19  Drivers:
20   Port (vpiHighConn) object at **fdspec01.v(6)
21... printing drivers and loads for test.t_q1:
22  Drivers:
23   Port (vpiHighConn) object at **fdspec01.v(7)
24... printing drivers and loads for test.t_set0:
25  Loads:
26   Port (vpiHighConn) object at **fdspec01.v(6)
27... printing drivers and loads for test.t_set1:
28  Loads:
29   Port (vpiHighConn) object at **fdspec01.v(7)
30... printing drivers and loads for test.t_clk:
31  Loads:
32   Port (vpiHighConn) object at **fdspec01.v(8)
33... printing drivers and loads for test.t_clk0:
34... printing drivers and loads for test.t_clk1:
35  Loads:
36   Port (vpiHighConn) object at **fdspec01.v(8)
37... printing drivers and loads for test.t_clk2:
38  Loads:
39   Port (vpiHighConn) object at **fdspec01.v(7)
40   Port (vpiHighConn) object at **fdspec01.v(7)
41   Port (vpiHighConn) object at **fdspec01.v(6)
42   Port (vpiHighConn) object at **fdspec01.v(6)
43... printing drivers and loads for test.t_clr:
44  Loads:
45   Port (vpiHighConn) object at **fdspec01.v(8)
46... printing drivers and loads for test.t_d:
47  Loads:
48   Port (vpiHighConn) object at **fdspec01.v(8)
49... printing drivers and loads for test.t_set:
50  Loads:
51   Port (vpiHighConn) object at **fdspec01.v(8)
52  There are 3 instances in test.
53... printing drivers and loads for test.i1.clk:
54  Loads:
55    vpiPrimTerm object at **fdspec01.v(110)
56  Drivers:
57   Port (vpiLowConn) object at **fdspec01.v(76)
58  Path terminals:
59    vpiModPathIn object at **NONE(0)
60  Timing check terminals:
61    vpiTchkTerm object at **fdspec01.v(104)
62    vpiTchkTerm object at **fdspec01.v(104)
63    vpiTchkTerm object at **fdspec01.v(103)
64    vpiTchkTerm object at **fdspec01.v(103)
65    vpiTchkTerm object at **fdspec01.v(101)
66... printing drivers and loads for test.i1.clk1:
67  Drivers:
68   Port (vpiLowConn) object at **fdspec01.v(76)
69  Timing check terminals:
70    vpiTchkTerm object at **fdspec01.v(106)
71... printing drivers and loads for test.i1.clr:
72  Loads:
73    vpiPrimTerm object at **fdspec01.v(110)
74  Drivers:
75   Port (vpiLowConn) object at **fdspec01.v(76)
76  Path terminals:
77    vpiModPathIn object at **NONE(0)
78... printing drivers and loads for test.i1.d:
79  Loads:
80    vpiPrimTerm object at **fdspec01.v(110)
81  Drivers:
82   Port (vpiLowConn) object at **fdspec01.v(76)
83  Timing check terminals:
84    vpiTchkTerm object at **fdspec01.v(107)
85    vpiTchkTerm object at **fdspec01.v(101)
86... printing drivers and loads for test.i1.q:
87  Loads:
88   Port (vpiLowConn) object at **fdspec01.v(76)
89  Drivers:
90    vpiPrimTerm object at **fdspec01.v(110)
91  Path terminals:
92    vpiModPathOut object at **NONE(0)
93    vpiModPathOut object at **NONE(0)
94... printing drivers and loads for test.i1.set:
95  Loads:
96    vpiPrimTerm object at **fdspec01.v(110)
97  Drivers:
98   Port (vpiLowConn) object at **fdspec01.v(76)
99  Path terminals:
100    vpiModPathIn object at **NONE(0)
101... printing drivers and loads for test.i2.clk:
102  Loads:
103    vpiPrimTerm object at **fdspec01.v(110)
104  Drivers:
105   Port (vpiLowConn) object at **fdspec01.v(76)
106  Path terminals:
107    vpiModPathIn object at **NONE(0)
108  Timing check terminals:
109    vpiTchkTerm object at **fdspec01.v(104)
110    vpiTchkTerm object at **fdspec01.v(104)
111    vpiTchkTerm object at **fdspec01.v(103)
112    vpiTchkTerm object at **fdspec01.v(103)
113    vpiTchkTerm object at **fdspec01.v(101)
114... printing drivers and loads for test.i2.clk1:
115  Drivers:
116   Port (vpiLowConn) object at **fdspec01.v(76)
117  Timing check terminals:
118    vpiTchkTerm object at **fdspec01.v(106)
119... printing drivers and loads for test.i2.clr:
120  Loads:
121    vpiPrimTerm object at **fdspec01.v(110)
122  Drivers:
123   Port (vpiLowConn) object at **fdspec01.v(76)
124  Path terminals:
125    vpiModPathIn object at **NONE(0)
126... printing drivers and loads for test.i2.d:
127  Loads:
128    vpiPrimTerm object at **fdspec01.v(110)
129  Drivers:
130   Port (vpiLowConn) object at **fdspec01.v(76)
131  Timing check terminals:
132    vpiTchkTerm object at **fdspec01.v(107)
133    vpiTchkTerm object at **fdspec01.v(101)
134... printing drivers and loads for test.i2.q:
135  Loads:
136   Port (vpiLowConn) object at **fdspec01.v(76)
137  Drivers:
138    vpiPrimTerm object at **fdspec01.v(110)
139  Path terminals:
140    vpiModPathOut object at **NONE(0)
141    vpiModPathOut object at **NONE(0)
142... printing drivers and loads for test.i2.set:
143  Loads:
144    vpiPrimTerm object at **fdspec01.v(110)
145  Drivers:
146   Port (vpiLowConn) object at **fdspec01.v(76)
147  Path terminals:
148    vpiModPathIn object at **NONE(0)
149... printing drivers and loads for test.i3.clk:
150  Loads:
151    vpiPrimTerm object at **fdspec01.v(110)
152  Drivers:
153   Port (vpiLowConn) object at **fdspec01.v(76)
154  Path terminals:
155    vpiModPathIn object at **NONE(0)
156  Timing check terminals:
157    vpiTchkTerm object at **fdspec01.v(104)
158    vpiTchkTerm object at **fdspec01.v(104)
159    vpiTchkTerm object at **fdspec01.v(103)
160    vpiTchkTerm object at **fdspec01.v(103)
161    vpiTchkTerm object at **fdspec01.v(101)
162... printing drivers and loads for test.i3.clk1:
163  Drivers:
164   Port (vpiLowConn) object at **fdspec01.v(76)
165  Timing check terminals:
166    vpiTchkTerm object at **fdspec01.v(106)
167... printing drivers and loads for test.i3.clr:
168  Loads:
169    vpiPrimTerm object at **fdspec01.v(110)
170  Drivers:
171   Port (vpiLowConn) object at **fdspec01.v(76)
172  Path terminals:
173    vpiModPathIn object at **NONE(0)
174... printing drivers and loads for test.i3.d:
175  Loads:
176    vpiPrimTerm object at **fdspec01.v(110)
177  Drivers:
178   Port (vpiLowConn) object at **fdspec01.v(76)
179  Timing check terminals:
180    vpiTchkTerm object at **fdspec01.v(107)
181    vpiTchkTerm object at **fdspec01.v(101)
182... printing drivers and loads for test.i3.q:
183  Loads:
184   Port (vpiLowConn) object at **fdspec01.v(76)
185  Drivers:
186    vpiPrimTerm object at **fdspec01.v(110)
187  Path terminals:
188    vpiModPathOut object at **NONE(0)
189    vpiModPathOut object at **NONE(0)
190... printing drivers and loads for test.i3.set:
191  Loads:
192    vpiPrimTerm object at **fdspec01.v(110)
193  Drivers:
194   Port (vpiLowConn) object at **fdspec01.v(76)
195  Path terminals:
196    vpiModPathIn object at **NONE(0)
197  >>> All instances processed - continuing with simulation.
198         0 q=x, clk=x, data=x, clr=x, set=x
199testing set/clear logic
200      2000 q=x, clk=x, data=x, clr=x, set=0
201      2040 q=1, clk=x, data=x, clr=x, set=0
202      3000 q=1, clk=x, data=x, clr=0, set=0
203      4000 q=1, clk=x, data=x, clr=0, set=1
204      4050 q=0, clk=x, data=x, clr=0, set=1
205      5000 q=0, clk=x, data=x, clr=0, set=0
206      5040 q=1, clk=x, data=x, clr=0, set=0
207      6000 q=1, clk=x, data=x, clr=0, set=1
208      6050 q=0, clk=x, data=x, clr=0, set=1
209      7000 q=0, clk=x, data=x, clr=x, set=1
210      7040 q=x, clk=x, data=x, clr=x, set=1
211testing normal logic
212      8000 q=x, clk=x, data=0, clr=1, set=1
213      9000 q=x, clk=1, data=0, clr=1, set=1
214     10000 q=x, clk=0, data=0, clr=1, set=1
215     11000 q=x, clk=1, data=0, clr=1, set=1
216     11250 q=0, clk=1, data=0, clr=1, set=1
217     12000 q=0, clk=0, data=0, clr=1, set=1
218     13000 q=0, clk=1, data=0, clr=1, set=1
219     14000 q=0, clk=0, data=0, clr=1, set=1
220     15000 q=0, clk=x, data=0, clr=1, set=1
221     16000 q=0, clk=0, data=0, clr=1, set=1
222     17000 q=0, clk=z, data=0, clr=1, set=1
223     18000 q=0, clk=0, data=0, clr=1, set=1
224     19000 q=0, clk=x, data=0, clr=1, set=1
225**fdspec01.v(105) WARN** now 20000 [566] timing violation in test.i3 (diff. 1000)
226 $period((posedge clk):19000, (posedge clk):20000, 1200);
227     20000 q=0, clk=1, data=0, clr=1, set=1
228     21000 q=0, clk=1, data=1, clr=1, set=1
229     22000 q=0, clk=0, data=1, clr=1, set=1
230     23000 q=0, clk=1, data=1, clr=1, set=1
231     23140 q=1, clk=1, data=1, clr=1, set=1
232     24000 q=1, clk=0, data=1, clr=1, set=1
233     25000 q=1, clk=1, data=1, clr=1, set=1
234     26000 q=1, clk=0, data=1, clr=1, set=1
235**fdspec01.v(105) WARN** now 26100 [566] timing violation in test.i3 (diff. 1100)
236 $period((posedge clk):25000, (posedge clk):26100, 1200);
237**fdspec01.v(104) WARN** now 26100 [566] timing violation in test.i3 (diff. 100)
238 $width((negedge clk):26000, (posedge clk):26100, 500);
239     26100 q=1, clk=x, data=1, clr=1, set=1
240     27100 q=1, clk=0, data=1, clr=1, set=1
241     28100 q=1, clk=z, data=1, clr=1, set=1
242     29100 q=1, clk=0, data=1, clr=1, set=1
243     30100 q=1, clk=x, data=1, clr=1, set=1
244**fdspec01.v(105) WARN** now 31100 [566] timing violation in test.i3 (diff. 1000)
245 $period((posedge clk):30100, (posedge clk):31100, 1200);
246     31100 q=1, clk=1, data=1, clr=1, set=1
247**fdspec01.v(103) WARN** now 31130 [566] timing violation in test.i3 (diff. 30)
248 $width((posedge clk):31100, (negedge clk):31130, 600);
249     31130 q=1, clk=0, data=1, clr=1, set=1
250**fdspec01.v(105) WARN** now 31190 [566] timing violation in test.i3 (diff. 90)
251 $period((posedge clk):31100, (posedge clk):31190, 1200);
252**fdspec01.v(104) WARN** now 31190 [566] timing violation in test.i3 (diff. 60)
253 $width((negedge clk):31130, (posedge clk):31190, 500);
254     31190 q=1, clk=1, data=1, clr=1, set=1
255**fdspec01.v(101) WARN** now 31220 [566] timing violation in test.i3 (diff. 30)
256 hold(of setuphold)((posedge clk):31190, d:31220, 50);
257     31220 q=1, clk=1, data=0, clr=1, set=1
258**fdspec01.v(103) WARN** now 31250 [566] timing violation in test.i3 (diff. 60)
259 $width((posedge clk):31190, (negedge clk):31250, 600);
260     31250 q=1, clk=0, data=0, clr=1, set=1
261     31280 q=1, clk=0, data=1, clr=1, set=1
262**fdspec01.v(107) WARN** now 31310 [566] timing violation in test.i3 (diff. 30)
263 $recovery((posedge d):31280, clk:31310, 200);
264**fdspec01.v(105) WARN** now 31310 [566] timing violation in test.i3 (diff. 120)
265 $period((posedge clk):31190, (posedge clk):31310, 1200);
266**fdspec01.v(104) WARN** now 31310 [566] timing violation in test.i3 (diff. 60)
267 $width((negedge clk):31250, (posedge clk):31310, 500);
268**fdspec01.v(101) WARN** now 31310 [566] timing violation in test.i3 (diff. 30)
269 setup(of setuphold)(d:31280, (posedge clk):31310, 70);
270     31310 q=1, clk=1, data=1, clr=1, set=1
271**fdspec01.v(107) WARN** now 31410 [566] timing violation in test.i3 (diff. 130)
272 $recovery((posedge d):31280, clk:31410, 200);
273**fdspec01.v(103) WARN** now 31410 [566] timing violation in test.i3 (diff. 100)
274 $width((posedge clk):31310, (negedge clk):31410, 600);
275     31410 q=1, clk=0, data=1, clr=1, set=1
276**fdspec01.v(106) WARN** now 33510 [566] timing violation in test.i3 (diff. 2000)
277 $skew((posedge clk1):31510, (posedge clk):33510, 50);
278     33510 q=1, clk=1, data=1, clr=1, set=1
279