1 #ifndef IVL_PUdp_H
2 #define IVL_PUdp_H
3 /*
4  * Copyright (c) 1998-2014 Stephen Williams (steve@picturel.com)
5  *
6  *    This source code is free software; you can redistribute it
7  *    and/or modify it in source code form under the terms of the GNU
8  *    General Public License as published by the Free Software
9  *    Foundation; either version 2 of the License, or (at your option)
10  *    any later version.
11  *
12  *    This program is distributed in the hope that it will be useful,
13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *    GNU General Public License for more details.
16  *
17  *    You should have received a copy of the GNU General Public License
18  *    along with this program; if not, write to the Free Software
19  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20  */
21 
22 # include  <map>
23 # include  "LineInfo.h"
24 # include  "StringHeap.h"
25 # include  "svector.h"
26 # include  "verinum.h"
27 
28 class PExpr;
29 
30 /*
31  * This class represents a parsed UDP. This is a much simpler object
32  * than a module or macromodule.
33  *
34  *   - all ports are scalar,
35  *   - pin 0 (the first port) is always output,
36  *     and the remaining pins are input.
37  *
38  * Thus, the ports can be represented as an ordered list of pin names.
39  * If the output port is declared as a register in the Verilog source,
40  * then this is a sequential UDP and the sequential flag is set to true.
41  *
42  * STATE TABLE
43  * Each entry in the state table is given as a string with the same
44  * number of characters as inputs. If the UDP is sequential, a
45  * character is also included at the end of the string to represent
46  * the current output.
47  *
48  * If the UDP is sequential, the "initial" member is taken to be the
49  * initial value assigned in the source, or 'x' if none is given.
50  */
51 class PUdp : public LineInfo {
52 
53     public:
54       explicit PUdp(perm_string n, unsigned nports);
55 
56       svector<string>ports;
57       unsigned find_port(const char*name);
58 
59       bool sequential;
60 
61       svector<string>tinput;
62       svector<char>  tcurrent;
63       svector<char>  toutput;
64 
65       verinum::V initial;
66 
67       map<string,PExpr*> attributes;
68 
69       void dump(ostream&out) const;
70 
71       perm_string name_;
72     private:
73 
74     private: // Not implemented
75       PUdp(const PUdp&);
76       PUdp& operator= (const PUdp&);
77 };
78 
79 #endif /* IVL_PUdp_H */
80