1* counter, latch DAC
2
3* 10 bit synchronous digital counter
4* inhibit at overflow, no revolving
5.subckt count10 din dinb dclk drs dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
6
7* j k clk set reset out nout
8ajk1 din dinb diclk ds1 drs dout1 dnout1 jkflop
9ajk2 dout1 dout1 diclk ds2 drs dout2 dnout2 jkflop
10ajk3 djk3 djk3 diclk ds3 drs dout3 dnout3 jkflop
11ajk4 djk4 djk4 diclk ds4 drs dout4 dnout4 jkflop
12ajk5 djk5 djk5 diclk ds1 drs dout5 dnout5 jkflop
13ajk6 djk6 djk6 diclk ds2 drs dout6 dnout6 jkflop
14ajk7 djk7 djk7 diclk ds3 drs dout7 dnout8 jkflop
15ajk8 djk8 djk8 diclk ds4 drs dout8 dnout8 jkflop
16ajk9 djk9 djk9 diclk ds3 drs dout9 dnout9 jkflop
17ajk10 djk10 djk10 diclk ds4 drs dout10 dnout10 jkflop
18
19aand1 [dout1 dout2] djk3 and1
20aand2 [dout1 dout2 dout3] djk4 and1
21aand3 [dout1 dout2 dout3 dout4] djk5 and1
22aand4 [dout1 dout2 dout3 dout4 dout5] djk6 and1
23aand5 [dout1 dout2 dout3 dout4 dout5 dout6] djk7 and1
24aand6 [dout1 dout2 dout3 dout4 dout5 dout6 dout7] djk8 and1
25aand7 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8] djk9 and1
26aand8 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9] djk10 and1
27
28* inhibit revolving of counter, just let it saturate
29* (footnote p. 57)
30aand_all [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10] dinhibit nand1
31aandclk [dclk dinhibit] diclk and1
32
33
34.model nand1 d_nand(rise_delay = 1e-9 fall_delay = 1e-9
35+ input_load = 0.5e-12)
36
37.model and1 d_and(rise_delay = 1e-9 fall_delay = 1e-9
38+ input_load = 0.5e-12)
39
40.model jkflop d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9
41+ reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9
42+ fall_delay = 1e-9)
43
44.ends count 10
45
46** 10 bit edge triggered latch
47.subckt latch10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10
48+ dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dclk
49
50*data clk set reset out nout
51aff1 din1 dclk dzero dzero dout1 dnout1 flop1
52aff2 din2 dclk dzero dzero dout2 dnout2 flop1
53aff3 din3 dclk dzero dzero dout3 dnout3 flop1
54aff4 din4 dclk dzero dzero dout4 dnout4 flop1
55aff5 din5 dclk dzero dzero dout5 dnout5 flop1
56aff6 din6 dclk dzero dzero dout6 dnout6 flop1
57aff7 din7 dclk dzero dzero dout7 dnout7 flop1
58aff8 din8 dclk dzero dzero dout8 dnout8 flop1
59aff9 din9 dclk dzero dzero dout9 dnout9 flop1
60aff10 din10 dclk dzero dzero dout10 dnout10 flop1
61
62.model flop1 d_dff(clk_delay = 1e-9 set_delay = 0
63+ reset_delay = 0 ic = 0 rise_delay = 1e-9
64+ fall_delay = 1e-9)
65
66.ends latch10
67
68** emulation of 10 bit DAC
69.subckt dac10  din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 aout
70.param vref=1
71abridge1 [din1 din2 din3 din4 din5 din6 din7 din8 din9 din10]
72+ [ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10] dac1
73BVout aout 0 V = 'vref'*(v(ain10)/2 + v(ain9)/4 + v(ain8)/8 + v(ain7)/16 + v(ain6)/32 +
74+ v(ain5)/64 + v(ain4)/128 + v(ain3)/256 + v(ain2)/512 + v(ain1)/1024)
75
76.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
77+ input_load = 5.0e-12 t_rise = 1e-9
78+ t_fall = 1e-9)
79
80.ends dac10
81
82