1Mixed IO types 2* 3* This circuit contains a mixture of IO types, including 4* analog, digital, user-defined (real), and 'null'. 5* 6* The circuit demonstrates the use of the digital and 7* user-defined node capability to model system-level designs 8* such as sampled-data filters. The simulated circuit 9* contains a digital oscillator enabled after 100us. The 10* square wave oscillator output is divided by 8 with a 11* ripple counter. The result is passed through a digital 12* filter to convert it to a sine wave. 13* 14.tran 1e-5 1e-3 15* 16v1 1 0 0.0 pulse(0 1 1e-4 1e-6) 17r1 1 0 1k 18* 19abridge1 [1] [enable] atod 20.model atod adc_bridge 21* 22aclk [enable clk] clk nand 23.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) 24* 25adiv2 div2_out clk NULL NULL NULL div2_out dff 26adiv4 div4_out div2_out NULL NULL NULL div4_out dff 27adiv8 div8_out div4_out NULL NULL NULL div8_out dff 28.model dff d_dff 29* 30abridge2 div8_out enable filt_in node_bridge2 31.model node_bridge2 d_to_real (zero=-1 one=1) 32* 33xfilter filt_in clk filt_out dig_filter 34* 35abridge3 filt_out a_out node_bridge3 36.model node_bridge3 real_to_v 37* 38rlpf1 a_out oa_minus 10k 39* 40xlpf 0 oa_minus lpf_out opamp 41* 42rlpf2 oa_minus lpf_out 10k 43clpf lpf_out oa_minus 0.01uF 44* 45* 46.subckt dig_filter filt_in clk filt_out 47* 48.model n0 real_gain (gain=1.0) 49.model n1 real_gain (gain=2.0) 50.model n2 real_gain (gain=1.0) 51.model g1 real_gain (gain=0.125) 52.model zm1 real_delay 53.model d0a real_gain (gain=-0.75) 54.model d1a real_gain (gain=0.5625) 55.model d0b real_gain (gain=-0.3438) 56.model d1b real_gain (gain=1.0) 57* 58an0a filt_in x0a n0 59an1a filt_in x1a n1 60an2a filt_in x2a n2 61* 62az0a x0a clk x1a zm1 63az1a x1a clk x2a zm1 64* 65ad0a x2a x0a d0a 66ad1a x2a x1a d1a 67* 68az2a x2a filt1_out g1 69az3a filt1_out clk filt2_in zm1 70* 71an0b filt2_in x0b n0 72an1b filt2_in x1b n1 73an2b filt2_in x2b n2 74* 75az0b x0b clk x1b zm1 76az1b x1b clk x2b zm1 77* 78ad0 x2b x0b d0b 79ad1 x2b x1b d1b 80* 81az2b x2b clk filt_out zm1 82* 83.ends dig_filter 84* 85* 86.subckt opamp plus minus out 87* 88r1 plus minus 300k 89a1 %vd (plus minus) outint lim 90.model lim limit (out_lower_limit = -12 out_upper_limit = 12 91+ fraction = true limit_range = 0.2 gain=300e3) 92r3 outint out 50.0 93r2 out 0 1e12 94* 95.ends opamp 96* 97* 98.end 99