1 /**** BSIM3v3.2.4, Released by Xuemei Xi 12/21/2001 ****/
2
3 /**********
4 * Copyright 2001 Regents of the University of California. All rights reserved.
5 * File: b3ld.c of BSIM3v3.2.4
6 * Author: 1991 JianHui Huang and Min-Chie Jeng.
7 * Modified by Mansun Chan (1995).
8 * Author: 1997-1999 Weidong Liu.
9 * Author: 2001 Xuemei Xi
10 * Modified by Xuemei Xi, 10/05, 12/21, 2001.
11 * Modified by Paolo Nenzi 2002 and Dietmar Warning 2003
12 **********/
13
14 #include "ngspice/ngspice.h"
15 #include "ngspice/cktdefs.h"
16 #include "bsim3v32def.h"
17 #include "ngspice/trandefs.h"
18 #include "ngspice/const.h"
19 #include "ngspice/sperror.h"
20 #include "ngspice/devdefs.h"
21 #include "ngspice/suffix.h"
22
23 #define MAX_EXP 5.834617425e14
24 #define MIN_EXP 1.713908431e-15
25 #define EXP_THRESHOLD 34.0
26 #define EPSOX 3.453133e-11
27 #define EPSSI 1.03594e-10
28 #define Charge_q 1.60219e-19
29 #define DELTA_1 0.02
30 #define DELTA_2 0.02
31 #define DELTA_3 0.02
32 #define DELTA_4 0.02
33
34 #ifdef USE_OMP
35 int BSIM3v32LoadOMP(BSIM3v32instance *here, CKTcircuit *ckt);
36 void BSIM3v32LoadRhsMat(GENmodel *inModel, CKTcircuit *ckt);
37 #endif
38
39 int
BSIM3v32load(GENmodel * inModel,CKTcircuit * ckt)40 BSIM3v32load (GENmodel *inModel, CKTcircuit *ckt)
41 {
42 #ifdef USE_OMP
43 int idx;
44 BSIM3v32model *model = (BSIM3v32model*)inModel;
45 int error = 0;
46 BSIM3v32instance **InstArray;
47 InstArray = model->BSIM3v32InstanceArray;
48
49 #pragma omp parallel for
50 for (idx = 0; idx < model->BSIM3v32InstCount; idx++) {
51 BSIM3v32instance *here = InstArray[idx];
52 int local_error = BSIM3v32LoadOMP(here, ckt);
53 if (local_error)
54 error = local_error;
55 }
56
57 BSIM3v32LoadRhsMat(inModel, ckt);
58
59 return error;
60 }
61
62
BSIM3v32LoadOMP(BSIM3v32instance * here,CKTcircuit * ckt)63 int BSIM3v32LoadOMP(BSIM3v32instance *here, CKTcircuit *ckt) {
64 BSIM3v32model *model = BSIM3v32modPtr(here);
65 #else
66 BSIM3v32model *model = (BSIM3v32model*)inModel;
67 BSIM3v32instance *here;
68 #endif
69 double SourceSatCurrent, DrainSatCurrent;
70 double ag0, qgd, qgs, qgb, von, cbhat, VgstNVt, ExpVgst;
71 double cdrain, cdhat, cdreq, ceqbd, ceqbs, ceqqb, ceqqd, ceqqg, ceq, geq;
72 double czbd, czbdsw, czbdswg, czbs, czbssw, czbsswg, evbd, evbs, arg, sarg;
73 double delvbd, delvbs, delvds, delvgd, delvgs;
74 double Vfbeff, dVfbeff_dVg, dVfbeff_dVd = 0.0, dVfbeff_dVb, V3, V4;
75 double gcbdb, gcbgb, gcbsb, gcddb, gcdgb, gcdsb, gcgdb, gcggb, gcgsb, gcsdb;
76 #ifndef NEWCONV
77 double tol;
78 #endif
79 double gcsgb, gcssb, MJ, MJSW, MJSWG;
80 double vbd, vbs, vds, vgb, vgd, vgs, vgdo;
81 #ifndef PREDICTOR
82 double xfact;
83 #endif
84 double qgate = 0.0, qbulk = 0.0, qdrn = 0.0, qsrc;
85 double qinoi, cqgate, cqbulk, cqdrn;
86 double Vds, Vgs, Vbs, Gmbs, FwdSum, RevSum;
87 double Vgs_eff, Vfb, dVfb_dVb = 0.0, dVfb_dVd = 0.0;
88 double Phis, dPhis_dVb, sqrtPhis, dsqrtPhis_dVb, Vth, dVth_dVb, dVth_dVd;
89 double Vgst, dVgst_dVg, dVgst_dVb, dVgs_eff_dVg, Nvtm;
90 double Vtm;
91 double n, dn_dVb, dn_dVd, voffcv, noff, dnoff_dVd, dnoff_dVb;
92 double ExpArg, V0, CoxWLcen, QovCox, LINK;
93 double DeltaPhi, dDeltaPhi_dVg, dDeltaPhi_dVd, dDeltaPhi_dVb;
94 double Cox, Tox, Tcen, dTcen_dVg, dTcen_dVd, dTcen_dVb;
95 double Ccen, Coxeff, dCoxeff_dVg, dCoxeff_dVd, dCoxeff_dVb;
96 double Denomi, dDenomi_dVg, dDenomi_dVd, dDenomi_dVb;
97 double ueff, dueff_dVg, dueff_dVd, dueff_dVb;
98 double Esat, Vdsat;
99 double EsatL, dEsatL_dVg, dEsatL_dVd, dEsatL_dVb;
100 double dVdsat_dVg, dVdsat_dVb, dVdsat_dVd, Vasat, dAlphaz_dVg, dAlphaz_dVb;
101 double dVasat_dVg, dVasat_dVb, dVasat_dVd, Va, dVa_dVd, dVa_dVg, dVa_dVb;
102 double Vbseff, dVbseff_dVb, VbseffCV, dVbseffCV_dVb;
103 double Arg1, One_Third_CoxWL, Two_Third_CoxWL, Alphaz, CoxWL;
104 double T0, dT0_dVg, dT0_dVd, dT0_dVb;
105 double T1, dT1_dVg, dT1_dVd, dT1_dVb;
106 double T2, dT2_dVg, dT2_dVd, dT2_dVb;
107 double T3, dT3_dVg, dT3_dVd, dT3_dVb;
108 double T4;
109 double T5;
110 double T6;
111 double T7;
112 double T8;
113 double T9;
114 double T10;
115 double T11, T12;
116 double tmp, Abulk, dAbulk_dVb, Abulk0, dAbulk0_dVb;
117 double VACLM, dVACLM_dVg, dVACLM_dVd, dVACLM_dVb;
118 double VADIBL, dVADIBL_dVg, dVADIBL_dVd, dVADIBL_dVb;
119 double Xdep, dXdep_dVb, lt1, dlt1_dVb, ltw, dltw_dVb, Delt_vth, dDelt_vth_dVb;
120 double Theta0, dTheta0_dVb;
121 double TempRatio, tmp1, tmp2, tmp3, tmp4;
122 double DIBL_Sft, dDIBL_Sft_dVd, Lambda, dLambda_dVg;
123 double Idtot, Ibtot;
124 #ifndef NOBYPASS
125 double tempv;
126 #endif
127 double a1, ScalingFactor;
128
129 double Vgsteff, dVgsteff_dVg, dVgsteff_dVd, dVgsteff_dVb;
130 double Vdseff, dVdseff_dVg, dVdseff_dVd, dVdseff_dVb;
131 double VdseffCV, dVdseffCV_dVg, dVdseffCV_dVd, dVdseffCV_dVb;
132 double diffVds, dAbulk_dVg;
133 double beta, dbeta_dVg, dbeta_dVd, dbeta_dVb;
134 double gche, dgche_dVg, dgche_dVd, dgche_dVb;
135 double fgche1, dfgche1_dVg, dfgche1_dVd, dfgche1_dVb;
136 double fgche2, dfgche2_dVg, dfgche2_dVd, dfgche2_dVb;
137 double Idl, dIdl_dVg, dIdl_dVd, dIdl_dVb;
138 double Idsa, dIdsa_dVg, dIdsa_dVd, dIdsa_dVb;
139 double Ids, Gm, Gds, Gmb;
140 double Isub, Gbd, Gbg, Gbb;
141 double VASCBE, dVASCBE_dVg, dVASCBE_dVd, dVASCBE_dVb;
142 double CoxWovL;
143 double Rds, dRds_dVg, dRds_dVb, WVCox, WVCoxRds;
144 double Vgst2Vtm, VdsatCV, dVdsatCV_dVg, dVdsatCV_dVb;
145 double Leff, Weff, dWeff_dVg, dWeff_dVb;
146 double AbulkCV, dAbulkCV_dVb;
147 double qgdo, qgso, cgdo, cgso;
148
149 double qcheq = 0.0, qdef, gqdef = 0.0, cqdef, cqcheq, gtau_diff, gtau_drift;
150 double gcqdb = 0.0,gcqsb = 0.0, gcqgb = 0.0,gcqbb = 0.0;
151 double dxpart, sxpart, ggtg, ggtd, ggts, ggtb;
152 double ddxpart_dVd, ddxpart_dVg, ddxpart_dVb, ddxpart_dVs;
153 double dsxpart_dVd, dsxpart_dVg, dsxpart_dVb, dsxpart_dVs;
154
155 double gbspsp, gbbdp, gbbsp, gbspg, gbspb, gbspdp;
156 double gbdpdp, gbdpg, gbdpb, gbdpsp;
157 double Cgg, Cgd, Cgb, Cdg, Cdd, Cds;
158 double Csg, Csd, Css, Csb, Cbg, Cbd, Cbb;
159 double Cgg1, Cgb1, Cgd1, Cbg1, Cbb1, Cbd1, Qac0, Qsub0;
160 double dQac0_dVg, dQac0_dVd = 0.0, dQac0_dVb, dQsub0_dVg;
161 double dQsub0_dVd, dQsub0_dVb;
162
163 double m;
164
165 struct bsim3v32SizeDependParam *pParam;
166 int ByPass, Check, ChargeComputationNeeded, error;
167
168 ScalingFactor = 1.0e-9;
169 ChargeComputationNeeded =
170 ((ckt->CKTmode & (MODEDCTRANCURVE | MODEAC | MODETRAN | MODEINITSMSIG)) ||
171 ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)))
172 ? 1 : 0;
173 #ifndef USE_OMP
174 for (; model != NULL; model = BSIM3v32nextModel(model))
175 { for (here = BSIM3v32instances(model); here != NULL;
176 here = BSIM3v32nextInstance(here))
177 {
178 #endif
179 Check = 1;
180 ByPass = 0;
181 pParam = here->pParam;
182 if ((ckt->CKTmode & MODEINITSMSIG))
183 { vbs = *(ckt->CKTstate0 + here->BSIM3v32vbs);
184 vgs = *(ckt->CKTstate0 + here->BSIM3v32vgs);
185 vds = *(ckt->CKTstate0 + here->BSIM3v32vds);
186 qdef = *(ckt->CKTstate0 + here->BSIM3v32qdef);
187 }
188 else if ((ckt->CKTmode & MODEINITTRAN))
189 { vbs = *(ckt->CKTstate1 + here->BSIM3v32vbs);
190 vgs = *(ckt->CKTstate1 + here->BSIM3v32vgs);
191 vds = *(ckt->CKTstate1 + here->BSIM3v32vds);
192 qdef = *(ckt->CKTstate1 + here->BSIM3v32qdef);
193 }
194 else if ((ckt->CKTmode & MODEINITJCT) && !here->BSIM3v32off)
195 { vds = model->BSIM3v32type * here->BSIM3v32icVDS;
196 vgs = model->BSIM3v32type * here->BSIM3v32icVGS;
197 vbs = model->BSIM3v32type * here->BSIM3v32icVBS;
198 qdef = 0.0;
199
200 if ((vds == 0.0) && (vgs == 0.0) && (vbs == 0.0) &&
201 ((ckt->CKTmode & (MODETRAN | MODEAC|MODEDCOP |
202 MODEDCTRANCURVE)) || (!(ckt->CKTmode & MODEUIC))))
203 { vbs = 0.0;
204 vgs = model->BSIM3v32type * here->BSIM3v32vth0 + 0.1;
205 vds = 0.1;
206 }
207 }
208 else if ((ckt->CKTmode & (MODEINITJCT | MODEINITFIX)) &&
209 (here->BSIM3v32off))
210 { qdef = vbs = vgs = vds = 0.0;
211 }
212 else
213 {
214 #ifndef PREDICTOR
215 if ((ckt->CKTmode & MODEINITPRED))
216 { xfact = ckt->CKTdelta / ckt->CKTdeltaOld[1];
217 *(ckt->CKTstate0 + here->BSIM3v32vbs) =
218 *(ckt->CKTstate1 + here->BSIM3v32vbs);
219 vbs = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v32vbs))
220 - (xfact * (*(ckt->CKTstate2 + here->BSIM3v32vbs)));
221 *(ckt->CKTstate0 + here->BSIM3v32vgs) =
222 *(ckt->CKTstate1 + here->BSIM3v32vgs);
223 vgs = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v32vgs))
224 - (xfact * (*(ckt->CKTstate2 + here->BSIM3v32vgs)));
225 *(ckt->CKTstate0 + here->BSIM3v32vds) =
226 *(ckt->CKTstate1 + here->BSIM3v32vds);
227 vds = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v32vds))
228 - (xfact * (*(ckt->CKTstate2 + here->BSIM3v32vds)));
229 *(ckt->CKTstate0 + here->BSIM3v32vbd) =
230 *(ckt->CKTstate0 + here->BSIM3v32vbs)
231 - *(ckt->CKTstate0 + here->BSIM3v32vds);
232 *(ckt->CKTstate0 + here->BSIM3v32qdef) =
233 *(ckt->CKTstate1 + here->BSIM3v32qdef);
234 qdef = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v32qdef))
235 -(xfact * (*(ckt->CKTstate2 + here->BSIM3v32qdef)));
236 }
237 else
238 {
239 #endif /* PREDICTOR */
240 vbs = model->BSIM3v32type
241 * (*(ckt->CKTrhsOld + here->BSIM3v32bNode)
242 - *(ckt->CKTrhsOld + here->BSIM3v32sNodePrime));
243 vgs = model->BSIM3v32type
244 * (*(ckt->CKTrhsOld + here->BSIM3v32gNode)
245 - *(ckt->CKTrhsOld + here->BSIM3v32sNodePrime));
246 vds = model->BSIM3v32type
247 * (*(ckt->CKTrhsOld + here->BSIM3v32dNodePrime)
248 - *(ckt->CKTrhsOld + here->BSIM3v32sNodePrime));
249 qdef = model->BSIM3v32type
250 * (*(ckt->CKTrhsOld + here->BSIM3v32qNode));
251 #ifndef PREDICTOR
252 }
253 #endif /* PREDICTOR */
254
255 vbd = vbs - vds;
256 vgd = vgs - vds;
257 vgdo = *(ckt->CKTstate0 + here->BSIM3v32vgs)
258 - *(ckt->CKTstate0 + here->BSIM3v32vds);
259 delvbs = vbs - *(ckt->CKTstate0 + here->BSIM3v32vbs);
260 delvbd = vbd - *(ckt->CKTstate0 + here->BSIM3v32vbd);
261 delvgs = vgs - *(ckt->CKTstate0 + here->BSIM3v32vgs);
262 delvds = vds - *(ckt->CKTstate0 + here->BSIM3v32vds);
263 delvgd = vgd - vgdo;
264
265 if (here->BSIM3v32mode >= 0)
266 { Idtot = here->BSIM3v32cd + here->BSIM3v32csub - here->BSIM3v32cbd;
267 cdhat = Idtot - here->BSIM3v32gbd * delvbd
268 + (here->BSIM3v32gmbs + here->BSIM3v32gbbs) * delvbs
269 + (here->BSIM3v32gm + here->BSIM3v32gbgs) * delvgs
270 + (here->BSIM3v32gds + here->BSIM3v32gbds) * delvds;
271 Ibtot = here->BSIM3v32cbs + here->BSIM3v32cbd - here->BSIM3v32csub;
272 cbhat = Ibtot + here->BSIM3v32gbd * delvbd
273 + (here->BSIM3v32gbs - here->BSIM3v32gbbs) * delvbs
274 - here->BSIM3v32gbgs * delvgs
275 - here->BSIM3v32gbds * delvds;
276 }
277 else
278 { Idtot = here->BSIM3v32cd - here->BSIM3v32cbd;
279 cdhat = Idtot - (here->BSIM3v32gbd - here->BSIM3v32gmbs) * delvbd
280 + here->BSIM3v32gm * delvgd
281 - here->BSIM3v32gds * delvds;
282 Ibtot = here->BSIM3v32cbs + here->BSIM3v32cbd - here->BSIM3v32csub;
283 cbhat = Ibtot + here->BSIM3v32gbs * delvbs
284 + (here->BSIM3v32gbd - here->BSIM3v32gbbs) * delvbd
285 - here->BSIM3v32gbgs * delvgd
286 + here->BSIM3v32gbds * delvds;
287 }
288
289 #ifndef NOBYPASS
290 /* following should be one big if connected by && all over
291 * the place, but some C compilers can't handle that, so
292 * we split it up here to let them digest it in stages
293 */
294
295 if ((!(ckt->CKTmode & MODEINITPRED)) && (ckt->CKTbypass))
296 if ((fabs(delvbs) < (ckt->CKTreltol * MAX(fabs(vbs),
297 fabs(*(ckt->CKTstate0+here->BSIM3v32vbs))) + ckt->CKTvoltTol)))
298 if ((fabs(delvbd) < (ckt->CKTreltol * MAX(fabs(vbd),
299 fabs(*(ckt->CKTstate0+here->BSIM3v32vbd))) + ckt->CKTvoltTol)))
300 if ((fabs(delvgs) < (ckt->CKTreltol * MAX(fabs(vgs),
301 fabs(*(ckt->CKTstate0+here->BSIM3v32vgs))) + ckt->CKTvoltTol)))
302 if ((fabs(delvds) < (ckt->CKTreltol * MAX(fabs(vds),
303 fabs(*(ckt->CKTstate0+here->BSIM3v32vds))) + ckt->CKTvoltTol)))
304 if ((fabs(cdhat - Idtot) < ckt->CKTreltol
305 * MAX(fabs(cdhat),fabs(Idtot)) + ckt->CKTabstol))
306 { tempv = MAX(fabs(cbhat),fabs(Ibtot)) + ckt->CKTabstol;
307 if ((fabs(cbhat - Ibtot)) < ckt->CKTreltol * tempv)
308 { /* bypass code */
309 vbs = *(ckt->CKTstate0 + here->BSIM3v32vbs);
310 vbd = *(ckt->CKTstate0 + here->BSIM3v32vbd);
311 vgs = *(ckt->CKTstate0 + here->BSIM3v32vgs);
312 vds = *(ckt->CKTstate0 + here->BSIM3v32vds);
313 qdef = *(ckt->CKTstate0 + here->BSIM3v32qdef);
314
315 vgd = vgs - vds;
316 vgb = vgs - vbs;
317
318 cdrain = here->BSIM3v32cd;
319 if ((ckt->CKTmode & (MODETRAN | MODEAC)) ||
320 ((ckt->CKTmode & MODETRANOP) &&
321 (ckt->CKTmode & MODEUIC)))
322 { ByPass = 1;
323 qgate = here->BSIM3v32qgate;
324 qbulk = here->BSIM3v32qbulk;
325 qdrn = here->BSIM3v32qdrn;
326 goto line755;
327 }
328 else
329 { goto line850;
330 }
331 }
332 }
333
334 #endif /*NOBYPASS*/
335 von = here->BSIM3v32von;
336 if (*(ckt->CKTstate0 + here->BSIM3v32vds) >= 0.0)
337 { vgs = DEVfetlim(vgs, *(ckt->CKTstate0+here->BSIM3v32vgs), von);
338 vds = vgs - vgd;
339 vds = DEVlimvds(vds, *(ckt->CKTstate0 + here->BSIM3v32vds));
340 vgd = vgs - vds;
341
342 }
343 else
344 { vgd = DEVfetlim(vgd, vgdo, von);
345 vds = vgs - vgd;
346 vds = -DEVlimvds(-vds, -(*(ckt->CKTstate0+here->BSIM3v32vds)));
347 vgs = vgd + vds;
348 }
349
350 if (vds >= 0.0)
351 { vbs = DEVpnjlim(vbs, *(ckt->CKTstate0 + here->BSIM3v32vbs),
352 CONSTvt0, model->BSIM3v32vcrit, &Check);
353 vbd = vbs - vds;
354
355 }
356 else
357 { vbd = DEVpnjlim(vbd, *(ckt->CKTstate0 + here->BSIM3v32vbd),
358 CONSTvt0, model->BSIM3v32vcrit, &Check);
359 vbs = vbd + vds;
360 }
361 }
362
363 /* determine DC current and derivatives */
364 vbd = vbs - vds;
365 vgd = vgs - vds;
366 vgb = vgs - vbs;
367
368 /* Source/drain junction diode DC model begins */
369 Nvtm = model->BSIM3v32vtm * model->BSIM3v32jctEmissionCoeff;
370 /* acm model */
371 if (model->BSIM3v32acmMod == 0)
372 {
373 if ((here->BSIM3v32sourceArea <= 0.0)
374 && (here->BSIM3v32sourcePerimeter <= 0.0))
375 {
376 SourceSatCurrent = 1.0e-14;
377 }
378 else
379 {
380 SourceSatCurrent = here->BSIM3v32sourceArea
381 * model->BSIM3v32jctTempSatCurDensity
382 + here->BSIM3v32sourcePerimeter
383 * model->BSIM3v32jctSidewallTempSatCurDensity;
384 }
385 if ((here->BSIM3v32drainArea <= 0.0) && (here->BSIM3v32drainPerimeter <= 0.0))
386 { DrainSatCurrent = 1.0e-14;
387 }
388 else
389 { DrainSatCurrent = here->BSIM3v32drainArea
390 * model->BSIM3v32jctTempSatCurDensity
391 + here->BSIM3v32drainPerimeter
392 * model->BSIM3v32jctSidewallTempSatCurDensity;
393 }
394 }
395 else
396 {
397 error = ACM_saturationCurrents(
398 model->BSIM3v32acmMod,
399 model->BSIM3v32calcacm,
400 here->BSIM3v32geo,
401 model->BSIM3v32hdif,
402 model->BSIM3v32wmlt,
403 here->BSIM3v32w,
404 model->BSIM3v32xw,
405 model->BSIM3v32jctTempSatCurDensity,
406 model->BSIM3v32jctSidewallTempSatCurDensity,
407 here->BSIM3v32drainAreaGiven,
408 here->BSIM3v32drainArea,
409 here->BSIM3v32drainPerimeterGiven,
410 here->BSIM3v32drainPerimeter,
411 here->BSIM3v32sourceAreaGiven,
412 here->BSIM3v32sourceArea,
413 here->BSIM3v32sourcePerimeterGiven,
414 here->BSIM3v32sourcePerimeter,
415 &DrainSatCurrent,
416 &SourceSatCurrent
417 );
418 if (error)
419 return(error);
420 }
421 if (SourceSatCurrent <= 0.0)
422 { here->BSIM3v32gbs = ckt->CKTgmin;
423 here->BSIM3v32cbs = here->BSIM3v32gbs * vbs;
424 }
425 else
426 { if (model->BSIM3v32ijth == 0.0)
427 { evbs = exp(vbs / Nvtm);
428 here->BSIM3v32gbs = SourceSatCurrent * evbs / Nvtm + ckt->CKTgmin;
429 here->BSIM3v32cbs = SourceSatCurrent * (evbs - 1.0)
430 + ckt->CKTgmin * vbs;
431 }
432 else
433 { if (vbs < here->BSIM3v32vjsm)
434 { evbs = exp(vbs / Nvtm);
435 here->BSIM3v32gbs = SourceSatCurrent * evbs / Nvtm + ckt->CKTgmin;
436 here->BSIM3v32cbs = SourceSatCurrent * (evbs - 1.0)
437 + ckt->CKTgmin * vbs;
438 }
439 else
440 {
441 /* Added revision dependent code */
442 switch (model->BSIM3v32intVersion) {
443 case BSIM3v32V324:
444 case BSIM3v32V323:
445 case BSIM3v32V322:
446 T0 = here->BSIM3v32IsEvjsm / Nvtm;
447 here->BSIM3v32gbs = T0 + (ckt->CKTgmin);
448 here->BSIM3v32cbs = here->BSIM3v32IsEvjsm - SourceSatCurrent
449 + T0 * (vbs - here->BSIM3v32vjsm) + (ckt->CKTgmin) * vbs;
450 break;
451 case BSIM3v32V32:
452 default:
453 T0 = (SourceSatCurrent + model->BSIM3v32ijth) / Nvtm;
454 here->BSIM3v32gbs = T0 + (ckt->CKTgmin);
455 here->BSIM3v32cbs = model->BSIM3v32ijth + (ckt->CKTgmin) * vbs
456 + T0 * (vbs - here->BSIM3v32vjsm);
457 }
458 }
459 }
460 }
461
462 if (DrainSatCurrent <= 0.0)
463 { here->BSIM3v32gbd = ckt->CKTgmin;
464 here->BSIM3v32cbd = here->BSIM3v32gbd * vbd;
465 }
466 else
467 { if (model->BSIM3v32ijth == 0.0)
468 { evbd = exp(vbd / Nvtm);
469 here->BSIM3v32gbd = DrainSatCurrent * evbd / Nvtm + ckt->CKTgmin;
470 here->BSIM3v32cbd = DrainSatCurrent * (evbd - 1.0)
471 + ckt->CKTgmin * vbd;
472 }
473 else
474 { if (vbd < here->BSIM3v32vjdm)
475 { evbd = exp(vbd / Nvtm);
476 here->BSIM3v32gbd = DrainSatCurrent * evbd / Nvtm + ckt->CKTgmin;
477 here->BSIM3v32cbd = DrainSatCurrent * (evbd - 1.0)
478 + ckt->CKTgmin * vbd;
479 }
480 else
481 {
482 /* Added revision dependent code */
483 switch (model->BSIM3v32intVersion) {
484 case BSIM3v32V324:
485 case BSIM3v32V323:
486 case BSIM3v32V322:
487 T0 = here->BSIM3v32IsEvjdm / Nvtm;
488 here->BSIM3v32gbd = T0 + (ckt->CKTgmin);
489 here->BSIM3v32cbd = here->BSIM3v32IsEvjdm - DrainSatCurrent
490 + T0 * (vbd - here->BSIM3v32vjdm) + (ckt->CKTgmin) * vbd;
491 break;
492 case BSIM3v32V32:
493 default:
494 T0 = (DrainSatCurrent + model->BSIM3v32ijth) / Nvtm;
495 here->BSIM3v32gbd = T0 + (ckt->CKTgmin);
496 here->BSIM3v32cbd = model->BSIM3v32ijth + (ckt->CKTgmin) * vbd
497 + T0 * (vbd - here->BSIM3v32vjdm);
498 }
499 }
500 }
501 }
502 /* End of diode DC model */
503
504 if (vds >= 0.0)
505 { /* normal mode */
506 here->BSIM3v32mode = 1;
507 Vds = vds;
508 Vgs = vgs;
509 Vbs = vbs;
510 }
511 else
512 { /* inverse mode */
513 here->BSIM3v32mode = -1;
514 Vds = -vds;
515 Vgs = vgd;
516 Vbs = vbd;
517 }
518
519 T0 = Vbs - pParam->BSIM3v32vbsc - 0.001;
520 T1 = sqrt(T0 * T0 - 0.004 * pParam->BSIM3v32vbsc);
521 Vbseff = pParam->BSIM3v32vbsc + 0.5 * (T0 + T1);
522 dVbseff_dVb = 0.5 * (1.0 + T0 / T1);
523 if (Vbseff < Vbs)
524 { Vbseff = Vbs;
525 }
526
527 if (Vbseff > 0.0)
528 { T0 = pParam->BSIM3v32phi / (pParam->BSIM3v32phi + Vbseff);
529 Phis = pParam->BSIM3v32phi * T0;
530 dPhis_dVb = -T0 * T0;
531 sqrtPhis = pParam->BSIM3v32phis3 / (pParam->BSIM3v32phi + 0.5 * Vbseff);
532 dsqrtPhis_dVb = -0.5 * sqrtPhis * sqrtPhis / pParam->BSIM3v32phis3;
533 }
534 else
535 { Phis = pParam->BSIM3v32phi - Vbseff;
536 dPhis_dVb = -1.0;
537 sqrtPhis = sqrt(Phis);
538 dsqrtPhis_dVb = -0.5 / sqrtPhis;
539 }
540 Xdep = pParam->BSIM3v32Xdep0 * sqrtPhis / pParam->BSIM3v32sqrtPhi;
541 dXdep_dVb = (pParam->BSIM3v32Xdep0 / pParam->BSIM3v32sqrtPhi)
542 * dsqrtPhis_dVb;
543
544 Leff = pParam->BSIM3v32leff;
545 Vtm = model->BSIM3v32vtm;
546 /* Vth Calculation */
547 T3 = sqrt(Xdep);
548 V0 = pParam->BSIM3v32vbi - pParam->BSIM3v32phi;
549
550 T0 = pParam->BSIM3v32dvt2 * Vbseff;
551 if (T0 >= - 0.5)
552 { T1 = 1.0 + T0;
553 T2 = pParam->BSIM3v32dvt2;
554 }
555 else /* Added to avoid any discontinuity problems caused by dvt2 */
556 { T4 = 1.0 / (3.0 + 8.0 * T0);
557 T1 = (1.0 + 3.0 * T0) * T4;
558 T2 = pParam->BSIM3v32dvt2 * T4 * T4;
559 }
560 lt1 = model->BSIM3v32factor1 * T3 * T1;
561 dlt1_dVb = model->BSIM3v32factor1 * (0.5 / T3 * T1 * dXdep_dVb + T3 * T2);
562
563 T0 = pParam->BSIM3v32dvt2w * Vbseff;
564 if (T0 >= - 0.5)
565 { T1 = 1.0 + T0;
566 T2 = pParam->BSIM3v32dvt2w;
567 }
568 else /* Added to avoid any discontinuity problems caused by dvt2w */
569 { T4 = 1.0 / (3.0 + 8.0 * T0);
570 T1 = (1.0 + 3.0 * T0) * T4;
571 T2 = pParam->BSIM3v32dvt2w * T4 * T4;
572 }
573 ltw = model->BSIM3v32factor1 * T3 * T1;
574 dltw_dVb = model->BSIM3v32factor1 * (0.5 / T3 * T1 * dXdep_dVb + T3 * T2);
575
576 T0 = -0.5 * pParam->BSIM3v32dvt1 * Leff / lt1;
577 if (T0 > -EXP_THRESHOLD)
578 { T1 = exp(T0);
579 Theta0 = T1 * (1.0 + 2.0 * T1);
580 dT1_dVb = -T0 / lt1 * T1 * dlt1_dVb;
581 dTheta0_dVb = (1.0 + 4.0 * T1) * dT1_dVb;
582 }
583 else
584 { T1 = MIN_EXP;
585 Theta0 = T1 * (1.0 + 2.0 * T1);
586 dTheta0_dVb = 0.0;
587 }
588
589 here->BSIM3v32thetavth = pParam->BSIM3v32dvt0 * Theta0;
590 Delt_vth = here->BSIM3v32thetavth * V0;
591 dDelt_vth_dVb = pParam->BSIM3v32dvt0 * dTheta0_dVb * V0;
592
593 T0 = -0.5 * pParam->BSIM3v32dvt1w * pParam->BSIM3v32weff * Leff / ltw;
594 if (T0 > -EXP_THRESHOLD)
595 { T1 = exp(T0);
596 T2 = T1 * (1.0 + 2.0 * T1);
597 dT1_dVb = -T0 / ltw * T1 * dltw_dVb;
598 dT2_dVb = (1.0 + 4.0 * T1) * dT1_dVb;
599 }
600 else
601 { T1 = MIN_EXP;
602 T2 = T1 * (1.0 + 2.0 * T1);
603 dT2_dVb = 0.0;
604 }
605
606 T0 = pParam->BSIM3v32dvt0w * T2;
607 T2 = T0 * V0;
608 dT2_dVb = pParam->BSIM3v32dvt0w * dT2_dVb * V0;
609
610 TempRatio = ckt->CKTtemp / model->BSIM3v32tnom - 1.0;
611 T0 = sqrt(1.0 + pParam->BSIM3v32nlx / Leff);
612 T1 = pParam->BSIM3v32k1ox * (T0 - 1.0) * pParam->BSIM3v32sqrtPhi
613 + (pParam->BSIM3v32kt1 + pParam->BSIM3v32kt1l / Leff
614 + pParam->BSIM3v32kt2 * Vbseff) * TempRatio;
615 tmp2 = model->BSIM3v32tox * pParam->BSIM3v32phi
616 / (pParam->BSIM3v32weff + pParam->BSIM3v32w0);
617
618 T3 = pParam->BSIM3v32eta0 + pParam->BSIM3v32etab * Vbseff;
619 if (T3 < 1.0e-4) /* avoid discontinuity problems caused by etab */
620 { T9 = 1.0 / (3.0 - 2.0e4 * T3);
621 T3 = (2.0e-4 - T3) * T9;
622 T4 = T9 * T9;
623 }
624 else
625 { T4 = 1.0;
626 }
627 dDIBL_Sft_dVd = T3 * pParam->BSIM3v32theta0vb0;
628 DIBL_Sft = dDIBL_Sft_dVd * Vds;
629
630 Vth = model->BSIM3v32type * here->BSIM3v32vth0 - pParam->BSIM3v32k1
631 * pParam->BSIM3v32sqrtPhi + pParam->BSIM3v32k1ox * sqrtPhis
632 - pParam->BSIM3v32k2ox * Vbseff - Delt_vth - T2 + (pParam->BSIM3v32k3
633 + pParam->BSIM3v32k3b * Vbseff) * tmp2 + T1 - DIBL_Sft;
634
635 here->BSIM3v32von = Vth;
636
637 dVth_dVb = pParam->BSIM3v32k1ox * dsqrtPhis_dVb - pParam->BSIM3v32k2ox
638 - dDelt_vth_dVb - dT2_dVb + pParam->BSIM3v32k3b * tmp2
639 - pParam->BSIM3v32etab * Vds * pParam->BSIM3v32theta0vb0 * T4
640 + pParam->BSIM3v32kt2 * TempRatio;
641 dVth_dVd = -dDIBL_Sft_dVd;
642
643 /* Calculate n */
644 tmp2 = pParam->BSIM3v32nfactor * EPSSI / Xdep;
645 tmp3 = pParam->BSIM3v32cdsc + pParam->BSIM3v32cdscb * Vbseff
646 + pParam->BSIM3v32cdscd * Vds;
647 tmp4 = (tmp2 + tmp3 * Theta0 + pParam->BSIM3v32cit) / model->BSIM3v32cox;
648 if (tmp4 >= -0.5)
649 { n = 1.0 + tmp4;
650 dn_dVb = (-tmp2 / Xdep * dXdep_dVb + tmp3 * dTheta0_dVb
651 + pParam->BSIM3v32cdscb * Theta0) / model->BSIM3v32cox;
652 dn_dVd = pParam->BSIM3v32cdscd * Theta0 / model->BSIM3v32cox;
653 }
654 else
655 /* avoid discontinuity problems caused by tmp4 */
656 { T0 = 1.0 / (3.0 + 8.0 * tmp4);
657 n = (1.0 + 3.0 * tmp4) * T0;
658 T0 *= T0;
659 dn_dVb = (-tmp2 / Xdep * dXdep_dVb + tmp3 * dTheta0_dVb
660 + pParam->BSIM3v32cdscb * Theta0) / model->BSIM3v32cox * T0;
661 dn_dVd = pParam->BSIM3v32cdscd * Theta0 / model->BSIM3v32cox * T0;
662 }
663
664 /* Poly Gate Si Depletion Effect */
665 T0 = here->BSIM3v32vfb + pParam->BSIM3v32phi;
666 if ((pParam->BSIM3v32ngate > 1.e18) && (pParam->BSIM3v32ngate < 1.e25)
667 && (Vgs > T0))
668 /* added to avoid the problem caused by ngate */
669 { T1 = 1.0e6 * Charge_q * EPSSI * pParam->BSIM3v32ngate
670 / (model->BSIM3v32cox * model->BSIM3v32cox);
671 T4 = sqrt(1.0 + 2.0 * (Vgs - T0) / T1);
672 T2 = T1 * (T4 - 1.0);
673 T3 = 0.5 * T2 * T2 / T1; /* T3 = Vpoly */
674 T7 = 1.12 - T3 - 0.05;
675 T6 = sqrt(T7 * T7 + 0.224);
676 T5 = 1.12 - 0.5 * (T7 + T6);
677 Vgs_eff = Vgs - T5;
678 dVgs_eff_dVg = 1.0 - (0.5 - 0.5 / T4) * (1.0 + T7 / T6);
679 }
680 else
681 { Vgs_eff = Vgs;
682 dVgs_eff_dVg = 1.0;
683 }
684 Vgst = Vgs_eff - Vth;
685
686 /* Effective Vgst (Vgsteff) Calculation */
687
688 T10 = 2.0 * n * Vtm;
689 VgstNVt = Vgst / T10;
690 ExpArg = (2.0 * pParam->BSIM3v32voff - Vgst) / T10;
691
692 /* MCJ: Very small Vgst */
693 if (VgstNVt > EXP_THRESHOLD)
694 { Vgsteff = Vgst;
695 dVgsteff_dVg = dVgs_eff_dVg;
696 dVgsteff_dVd = -dVth_dVd;
697 dVgsteff_dVb = -dVth_dVb;
698 }
699 else if (ExpArg > EXP_THRESHOLD)
700 { T0 = (Vgst - pParam->BSIM3v32voff) / (n * Vtm);
701 ExpVgst = exp(T0);
702 Vgsteff = Vtm * pParam->BSIM3v32cdep0 / model->BSIM3v32cox * ExpVgst;
703 dVgsteff_dVg = Vgsteff / (n * Vtm);
704 dVgsteff_dVd = -dVgsteff_dVg * (dVth_dVd + T0 * Vtm * dn_dVd);
705 dVgsteff_dVb = -dVgsteff_dVg * (dVth_dVb + T0 * Vtm * dn_dVb);
706 dVgsteff_dVg *= dVgs_eff_dVg;
707 }
708 else
709 { ExpVgst = exp(VgstNVt);
710 T1 = T10 * log(1.0 + ExpVgst);
711 dT1_dVg = ExpVgst / (1.0 + ExpVgst);
712 dT1_dVb = -dT1_dVg * (dVth_dVb + Vgst / n * dn_dVb)
713 + T1 / n * dn_dVb;
714 dT1_dVd = -dT1_dVg * (dVth_dVd + Vgst / n * dn_dVd)
715 + T1 / n * dn_dVd;
716
717 dT2_dVg = -model->BSIM3v32cox / (Vtm * pParam->BSIM3v32cdep0)
718 * exp(ExpArg);
719 T2 = 1.0 - T10 * dT2_dVg;
720 dT2_dVd = -dT2_dVg * (dVth_dVd - 2.0 * Vtm * ExpArg * dn_dVd)
721 + (T2 - 1.0) / n * dn_dVd;
722 dT2_dVb = -dT2_dVg * (dVth_dVb - 2.0 * Vtm * ExpArg * dn_dVb)
723 + (T2 - 1.0) / n * dn_dVb;
724
725 Vgsteff = T1 / T2;
726 T3 = T2 * T2;
727 dVgsteff_dVg = (T2 * dT1_dVg - T1 * dT2_dVg) / T3 * dVgs_eff_dVg;
728 dVgsteff_dVd = (T2 * dT1_dVd - T1 * dT2_dVd) / T3;
729 dVgsteff_dVb = (T2 * dT1_dVb - T1 * dT2_dVb) / T3;
730 }
731 /* Added revision dependent code */
732 if (model->BSIM3v32intVersion > BSIM3v32V323) {
733 here->BSIM3v32Vgsteff = Vgsteff;
734 }
735
736 /* Calculate Effective Channel Geometry */
737 T9 = sqrtPhis - pParam->BSIM3v32sqrtPhi;
738 Weff = pParam->BSIM3v32weff - 2.0 * (pParam->BSIM3v32dwg * Vgsteff
739 + pParam->BSIM3v32dwb * T9);
740 dWeff_dVg = -2.0 * pParam->BSIM3v32dwg;
741 dWeff_dVb = -2.0 * pParam->BSIM3v32dwb * dsqrtPhis_dVb;
742
743 if (Weff < 2.0e-8) /* to avoid the discontinuity problem due to Weff*/
744 { T0 = 1.0 / (6.0e-8 - 2.0 * Weff);
745 Weff = 2.0e-8 * (4.0e-8 - Weff) * T0;
746 T0 *= T0 * 4.0e-16;
747 dWeff_dVg *= T0;
748 dWeff_dVb *= T0;
749 }
750
751 T0 = pParam->BSIM3v32prwg * Vgsteff + pParam->BSIM3v32prwb * T9;
752 if (T0 >= -0.9)
753 { Rds = pParam->BSIM3v32rds0 * (1.0 + T0);
754 dRds_dVg = pParam->BSIM3v32rds0 * pParam->BSIM3v32prwg;
755 dRds_dVb = pParam->BSIM3v32rds0 * pParam->BSIM3v32prwb * dsqrtPhis_dVb;
756 }
757 else
758 /* to avoid the discontinuity problem due to prwg and prwb*/
759 { T1 = 1.0 / (17.0 + 20.0 * T0);
760 Rds = pParam->BSIM3v32rds0 * (0.8 + T0) * T1;
761 T1 *= T1;
762 dRds_dVg = pParam->BSIM3v32rds0 * pParam->BSIM3v32prwg * T1;
763 dRds_dVb = pParam->BSIM3v32rds0 * pParam->BSIM3v32prwb * dsqrtPhis_dVb
764 * T1;
765 }
766 /* Added revision dependent code */
767 if (model->BSIM3v32intVersion > BSIM3v32V323) {
768 here->BSIM3v32rds = Rds; /* Noise Bugfix */
769 }
770
771 /* Calculate Abulk */
772 T1 = 0.5 * pParam->BSIM3v32k1ox / sqrtPhis;
773 dT1_dVb = -T1 / sqrtPhis * dsqrtPhis_dVb;
774
775 T9 = sqrt(pParam->BSIM3v32xj * Xdep);
776 tmp1 = Leff + 2.0 * T9;
777 T5 = Leff / tmp1;
778 tmp2 = pParam->BSIM3v32a0 * T5;
779 tmp3 = pParam->BSIM3v32weff + pParam->BSIM3v32b1;
780 tmp4 = pParam->BSIM3v32b0 / tmp3;
781 T2 = tmp2 + tmp4;
782 dT2_dVb = -T9 / tmp1 / Xdep * dXdep_dVb;
783 T6 = T5 * T5;
784 T7 = T5 * T6;
785
786 Abulk0 = 1.0 + T1 * T2;
787 dAbulk0_dVb = T1 * tmp2 * dT2_dVb + T2 * dT1_dVb;
788
789 T8 = pParam->BSIM3v32ags * pParam->BSIM3v32a0 * T7;
790 dAbulk_dVg = -T1 * T8;
791 Abulk = Abulk0 + dAbulk_dVg * Vgsteff;
792 dAbulk_dVb = dAbulk0_dVb - T8 * Vgsteff * (dT1_dVb
793 + 3.0 * T1 * dT2_dVb);
794
795 if (Abulk0 < 0.1) /* added to avoid the problems caused by Abulk0 */
796 { T9 = 1.0 / (3.0 - 20.0 * Abulk0);
797 Abulk0 = (0.2 - Abulk0) * T9;
798 dAbulk0_dVb *= T9 * T9;
799 }
800
801 if (Abulk < 0.1)
802 /* added to avoid the problems caused by Abulk */
803 { T9 = 1.0 / (3.0 - 20.0 * Abulk);
804 Abulk = (0.2 - Abulk) * T9;
805 /* Added revision dependent code */
806 if (model->BSIM3v32intVersion > BSIM3v32V32) {
807 T10 = T9 * T9;
808 dAbulk_dVb *= T10;
809 dAbulk_dVg *= T10;
810 } else {
811 dAbulk_dVb *= T9 * T9;
812 }
813 }
814 /* Added revision dependent code */
815 if (model->BSIM3v32intVersion > BSIM3v32V323) {
816 here->BSIM3v32Abulk = Abulk;
817 }
818
819 T2 = pParam->BSIM3v32keta * Vbseff;
820 if (T2 >= -0.9)
821 { T0 = 1.0 / (1.0 + T2);
822 dT0_dVb = -pParam->BSIM3v32keta * T0 * T0;
823 }
824 else
825 /* added to avoid the problems caused by Keta */
826 { T1 = 1.0 / (0.8 + T2);
827 T0 = (17.0 + 20.0 * T2) * T1;
828 dT0_dVb = -pParam->BSIM3v32keta * T1 * T1;
829 }
830 dAbulk_dVg *= T0;
831 dAbulk_dVb = dAbulk_dVb * T0 + Abulk * dT0_dVb;
832 dAbulk0_dVb = dAbulk0_dVb * T0 + Abulk0 * dT0_dVb;
833 Abulk *= T0;
834 Abulk0 *= T0;
835
836
837 /* Mobility calculation */
838 if (model->BSIM3v32mobMod == 1)
839 { T0 = Vgsteff + Vth + Vth;
840 T2 = pParam->BSIM3v32ua + pParam->BSIM3v32uc * Vbseff;
841 T3 = T0 / model->BSIM3v32tox;
842 T5 = T3 * (T2 + pParam->BSIM3v32ub * T3);
843 dDenomi_dVg = (T2 + 2.0 * pParam->BSIM3v32ub * T3) / model->BSIM3v32tox;
844 dDenomi_dVd = dDenomi_dVg * 2.0 * dVth_dVd;
845 dDenomi_dVb = dDenomi_dVg * 2.0 * dVth_dVb + pParam->BSIM3v32uc * T3;
846 }
847 else if (model->BSIM3v32mobMod == 2)
848 { T5 = Vgsteff / model->BSIM3v32tox * (pParam->BSIM3v32ua
849 + pParam->BSIM3v32uc * Vbseff + pParam->BSIM3v32ub * Vgsteff
850 / model->BSIM3v32tox);
851 dDenomi_dVg = (pParam->BSIM3v32ua + pParam->BSIM3v32uc * Vbseff
852 + 2.0 * pParam->BSIM3v32ub * Vgsteff / model->BSIM3v32tox)
853 / model->BSIM3v32tox;
854 dDenomi_dVd = 0.0;
855 dDenomi_dVb = Vgsteff * pParam->BSIM3v32uc / model->BSIM3v32tox;
856 }
857 else
858 { T0 = Vgsteff + Vth + Vth;
859 T2 = 1.0 + pParam->BSIM3v32uc * Vbseff;
860 T3 = T0 / model->BSIM3v32tox;
861 T4 = T3 * (pParam->BSIM3v32ua + pParam->BSIM3v32ub * T3);
862 T5 = T4 * T2;
863 dDenomi_dVg = (pParam->BSIM3v32ua + 2.0 * pParam->BSIM3v32ub * T3) * T2
864 / model->BSIM3v32tox;
865 dDenomi_dVd = dDenomi_dVg * 2.0 * dVth_dVd;
866 dDenomi_dVb = dDenomi_dVg * 2.0 * dVth_dVb + pParam->BSIM3v32uc * T4;
867 }
868
869 if (T5 >= -0.8)
870 { Denomi = 1.0 + T5;
871 }
872 else /* Added to avoid the discontinuity problem caused by ua and ub*/
873 { T9 = 1.0 / (7.0 + 10.0 * T5);
874 Denomi = (0.6 + T5) * T9;
875 T9 *= T9;
876 dDenomi_dVg *= T9;
877 dDenomi_dVd *= T9;
878 dDenomi_dVb *= T9;
879 }
880
881 here->BSIM3v32ueff = ueff = here->BSIM3v32u0temp / Denomi;
882 T9 = -ueff / Denomi;
883 dueff_dVg = T9 * dDenomi_dVg;
884 dueff_dVd = T9 * dDenomi_dVd;
885 dueff_dVb = T9 * dDenomi_dVb;
886
887 /* Saturation Drain Voltage Vdsat */
888 WVCox = Weff * pParam->BSIM3v32vsattemp * model->BSIM3v32cox;
889 WVCoxRds = WVCox * Rds;
890
891 Esat = 2.0 * pParam->BSIM3v32vsattemp / ueff;
892 EsatL = Esat * Leff;
893 T0 = -EsatL /ueff;
894 dEsatL_dVg = T0 * dueff_dVg;
895 dEsatL_dVd = T0 * dueff_dVd;
896 dEsatL_dVb = T0 * dueff_dVb;
897
898 /* Sqrt() */
899 a1 = pParam->BSIM3v32a1;
900 if (a1 == 0.0)
901 { Lambda = pParam->BSIM3v32a2;
902 dLambda_dVg = 0.0;
903 }
904 else if (a1 > 0.0)
905 /* Added to avoid the discontinuity problem
906 caused by a1 and a2 (Lambda) */
907 { T0 = 1.0 - pParam->BSIM3v32a2;
908 T1 = T0 - pParam->BSIM3v32a1 * Vgsteff - 0.0001;
909 T2 = sqrt(T1 * T1 + 0.0004 * T0);
910 Lambda = pParam->BSIM3v32a2 + T0 - 0.5 * (T1 + T2);
911 dLambda_dVg = 0.5 * pParam->BSIM3v32a1 * (1.0 + T1 / T2);
912 }
913 else
914 { T1 = pParam->BSIM3v32a2 + pParam->BSIM3v32a1 * Vgsteff - 0.0001;
915 T2 = sqrt(T1 * T1 + 0.0004 * pParam->BSIM3v32a2);
916 Lambda = 0.5 * (T1 + T2);
917 dLambda_dVg = 0.5 * pParam->BSIM3v32a1 * (1.0 + T1 / T2);
918 }
919
920 Vgst2Vtm = Vgsteff + 2.0 * Vtm;
921 /* Added revision dependent code */
922 if (model->BSIM3v32intVersion > BSIM3v32V323) {
923 here->BSIM3v32AbovVgst2Vtm = Abulk / Vgst2Vtm;
924 }
925
926 if (Rds > 0)
927 { tmp2 = dRds_dVg / Rds + dWeff_dVg / Weff;
928 tmp3 = dRds_dVb / Rds + dWeff_dVb / Weff;
929 }
930 else
931 { tmp2 = dWeff_dVg / Weff;
932 tmp3 = dWeff_dVb / Weff;
933 }
934 if ((Rds == 0.0) && (Lambda == 1.0))
935 { T0 = 1.0 / (Abulk * EsatL + Vgst2Vtm);
936 tmp1 = 0.0;
937 T1 = T0 * T0;
938 T2 = Vgst2Vtm * T0;
939 T3 = EsatL * Vgst2Vtm;
940 Vdsat = T3 * T0;
941
942 dT0_dVg = -(Abulk * dEsatL_dVg + EsatL * dAbulk_dVg + 1.0) * T1;
943 dT0_dVd = -(Abulk * dEsatL_dVd) * T1;
944 dT0_dVb = -(Abulk * dEsatL_dVb + dAbulk_dVb * EsatL) * T1;
945
946 dVdsat_dVg = T3 * dT0_dVg + T2 * dEsatL_dVg + EsatL * T0;
947 dVdsat_dVd = T3 * dT0_dVd + T2 * dEsatL_dVd;
948 dVdsat_dVb = T3 * dT0_dVb + T2 * dEsatL_dVb;
949 }
950 else
951 { tmp1 = dLambda_dVg / (Lambda * Lambda);
952 T9 = Abulk * WVCoxRds;
953 T8 = Abulk * T9;
954 T7 = Vgst2Vtm * T9;
955 T6 = Vgst2Vtm * WVCoxRds;
956 T0 = 2.0 * Abulk * (T9 - 1.0 + 1.0 / Lambda);
957 dT0_dVg = 2.0 * (T8 * tmp2 - Abulk * tmp1
958 + (2.0 * T9 + 1.0 / Lambda - 1.0) * dAbulk_dVg);
959
960 dT0_dVb = 2.0 * (T8 * (2.0 / Abulk * dAbulk_dVb + tmp3)
961 + (1.0 / Lambda - 1.0) * dAbulk_dVb);
962 dT0_dVd = 0.0;
963 T1 = Vgst2Vtm * (2.0 / Lambda - 1.0) + Abulk * EsatL + 3.0 * T7;
964
965 dT1_dVg = (2.0 / Lambda - 1.0) - 2.0 * Vgst2Vtm * tmp1
966 + Abulk * dEsatL_dVg + EsatL * dAbulk_dVg + 3.0 * (T9
967 + T7 * tmp2 + T6 * dAbulk_dVg);
968 dT1_dVb = Abulk * dEsatL_dVb + EsatL * dAbulk_dVb
969 + 3.0 * (T6 * dAbulk_dVb + T7 * tmp3);
970 dT1_dVd = Abulk * dEsatL_dVd;
971
972 T2 = Vgst2Vtm * (EsatL + 2.0 * T6);
973 dT2_dVg = EsatL + Vgst2Vtm * dEsatL_dVg
974 + T6 * (4.0 + 2.0 * Vgst2Vtm * tmp2);
975 dT2_dVb = Vgst2Vtm * (dEsatL_dVb + 2.0 * T6 * tmp3);
976 dT2_dVd = Vgst2Vtm * dEsatL_dVd;
977
978 T3 = sqrt(T1 * T1 - 2.0 * T0 * T2);
979 Vdsat = (T1 - T3) / T0;
980
981 dT3_dVg = (T1 * dT1_dVg - 2.0 * (T0 * dT2_dVg + T2 * dT0_dVg))
982 / T3;
983 dT3_dVd = (T1 * dT1_dVd - 2.0 * (T0 * dT2_dVd + T2 * dT0_dVd))
984 / T3;
985 dT3_dVb = (T1 * dT1_dVb - 2.0 * (T0 * dT2_dVb + T2 * dT0_dVb))
986 / T3;
987
988 dVdsat_dVg = (dT1_dVg - (T1 * dT1_dVg - dT0_dVg * T2
989 - T0 * dT2_dVg) / T3 - Vdsat * dT0_dVg) / T0;
990 dVdsat_dVb = (dT1_dVb - (T1 * dT1_dVb - dT0_dVb * T2
991 - T0 * dT2_dVb) / T3 - Vdsat * dT0_dVb) / T0;
992 dVdsat_dVd = (dT1_dVd - (T1 * dT1_dVd - T0 * dT2_dVd) / T3) / T0;
993 }
994 here->BSIM3v32vdsat = Vdsat;
995
996 /* Effective Vds (Vdseff) Calculation */
997 T1 = Vdsat - Vds - pParam->BSIM3v32delta;
998 dT1_dVg = dVdsat_dVg;
999 dT1_dVd = dVdsat_dVd - 1.0;
1000 dT1_dVb = dVdsat_dVb;
1001
1002 T2 = sqrt(T1 * T1 + 4.0 * pParam->BSIM3v32delta * Vdsat);
1003 T0 = T1 / T2;
1004 T3 = 2.0 * pParam->BSIM3v32delta / T2;
1005 dT2_dVg = T0 * dT1_dVg + T3 * dVdsat_dVg;
1006 dT2_dVd = T0 * dT1_dVd + T3 * dVdsat_dVd;
1007 dT2_dVb = T0 * dT1_dVb + T3 * dVdsat_dVb;
1008
1009 Vdseff = Vdsat - 0.5 * (T1 + T2);
1010 dVdseff_dVg = dVdsat_dVg - 0.5 * (dT1_dVg + dT2_dVg);
1011 dVdseff_dVd = dVdsat_dVd - 0.5 * (dT1_dVd + dT2_dVd);
1012 dVdseff_dVb = dVdsat_dVb - 0.5 * (dT1_dVb + dT2_dVb);
1013 /* Added revision dependent code */
1014 switch (model->BSIM3v32intVersion) {
1015 case BSIM3v32V324:
1016 case BSIM3v32V323:
1017 case BSIM3v32V322:
1018 /* Added to eliminate non-zero Vdseff at Vds=0.0 */
1019 if (Vds == 0.0)
1020 {
1021 Vdseff = 0.0;
1022 dVdseff_dVg = 0.0;
1023 dVdseff_dVb = 0.0;
1024 }
1025 break;
1026 case BSIM3v32V32:
1027 default:
1028 /* Do nothing */
1029 break;
1030 }
1031
1032 /* Calculate VAsat */
1033 tmp4 = 1.0 - 0.5 * Abulk * Vdsat / Vgst2Vtm;
1034 T9 = WVCoxRds * Vgsteff;
1035 T8 = T9 / Vgst2Vtm;
1036 T0 = EsatL + Vdsat + 2.0 * T9 * tmp4;
1037
1038 T7 = 2.0 * WVCoxRds * tmp4;
1039 dT0_dVg = dEsatL_dVg + dVdsat_dVg + T7 * (1.0 + tmp2 * Vgsteff)
1040 - T8 * (Abulk * dVdsat_dVg - Abulk * Vdsat / Vgst2Vtm
1041 + Vdsat * dAbulk_dVg);
1042
1043 dT0_dVb = dEsatL_dVb + dVdsat_dVb + T7 * tmp3 * Vgsteff
1044 - T8 * (dAbulk_dVb * Vdsat + Abulk * dVdsat_dVb);
1045 dT0_dVd = dEsatL_dVd + dVdsat_dVd - T8 * Abulk * dVdsat_dVd;
1046
1047 T9 = WVCoxRds * Abulk;
1048 T1 = 2.0 / Lambda - 1.0 + T9;
1049 dT1_dVg = -2.0 * tmp1 + WVCoxRds * (Abulk * tmp2 + dAbulk_dVg);
1050 dT1_dVb = dAbulk_dVb * WVCoxRds + T9 * tmp3;
1051
1052 Vasat = T0 / T1;
1053 dVasat_dVg = (dT0_dVg - Vasat * dT1_dVg) / T1;
1054 dVasat_dVb = (dT0_dVb - Vasat * dT1_dVb) / T1;
1055 dVasat_dVd = dT0_dVd / T1;
1056
1057 if (Vdseff > Vds)
1058 Vdseff = Vds;
1059 diffVds = Vds - Vdseff;
1060 /* Added revision dependent code */
1061 if (model->BSIM3v32intVersion > BSIM3v32V323) {
1062 here->BSIM3v32Vdseff = Vdseff;
1063 }
1064
1065 /* Calculate VACLM */
1066 if ((pParam->BSIM3v32pclm > 0.0) && (diffVds > 1.0e-10))
1067 { T0 = 1.0 / (pParam->BSIM3v32pclm * Abulk * pParam->BSIM3v32litl);
1068 dT0_dVb = -T0 / Abulk * dAbulk_dVb;
1069 dT0_dVg = -T0 / Abulk * dAbulk_dVg;
1070
1071 T2 = Vgsteff / EsatL;
1072 T1 = Leff * (Abulk + T2);
1073 dT1_dVg = Leff * ((1.0 - T2 * dEsatL_dVg) / EsatL + dAbulk_dVg);
1074 dT1_dVb = Leff * (dAbulk_dVb - T2 * dEsatL_dVb / EsatL);
1075 dT1_dVd = -T2 * dEsatL_dVd / Esat;
1076
1077 T9 = T0 * T1;
1078 VACLM = T9 * diffVds;
1079 dVACLM_dVg = T0 * dT1_dVg * diffVds - T9 * dVdseff_dVg
1080 + T1 * diffVds * dT0_dVg;
1081 dVACLM_dVb = (dT0_dVb * T1 + T0 * dT1_dVb) * diffVds
1082 - T9 * dVdseff_dVb;
1083 dVACLM_dVd = T0 * dT1_dVd * diffVds + T9 * (1.0 - dVdseff_dVd);
1084 }
1085 else
1086 { VACLM = MAX_EXP;
1087 dVACLM_dVd = dVACLM_dVg = dVACLM_dVb = 0.0;
1088 }
1089
1090 /* Calculate VADIBL */
1091 if (pParam->BSIM3v32thetaRout > 0.0)
1092 { T8 = Abulk * Vdsat;
1093 T0 = Vgst2Vtm * T8;
1094 dT0_dVg = Vgst2Vtm * Abulk * dVdsat_dVg + T8
1095 + Vgst2Vtm * Vdsat * dAbulk_dVg;
1096 dT0_dVb = Vgst2Vtm * (dAbulk_dVb * Vdsat + Abulk * dVdsat_dVb);
1097 dT0_dVd = Vgst2Vtm * Abulk * dVdsat_dVd;
1098
1099 T1 = Vgst2Vtm + T8;
1100 dT1_dVg = 1.0 + Abulk * dVdsat_dVg + Vdsat * dAbulk_dVg;
1101 dT1_dVb = Abulk * dVdsat_dVb + dAbulk_dVb * Vdsat;
1102 dT1_dVd = Abulk * dVdsat_dVd;
1103
1104 T9 = T1 * T1;
1105 T2 = pParam->BSIM3v32thetaRout;
1106 VADIBL = (Vgst2Vtm - T0 / T1) / T2;
1107 dVADIBL_dVg = (1.0 - dT0_dVg / T1 + T0 * dT1_dVg / T9) / T2;
1108 dVADIBL_dVb = (-dT0_dVb / T1 + T0 * dT1_dVb / T9) / T2;
1109 dVADIBL_dVd = (-dT0_dVd / T1 + T0 * dT1_dVd / T9) / T2;
1110
1111 T7 = pParam->BSIM3v32pdiblb * Vbseff;
1112 if (T7 >= -0.9)
1113 { T3 = 1.0 / (1.0 + T7);
1114 VADIBL *= T3;
1115 dVADIBL_dVg *= T3;
1116 dVADIBL_dVb = (dVADIBL_dVb - VADIBL * pParam->BSIM3v32pdiblb)
1117 * T3;
1118 dVADIBL_dVd *= T3;
1119 }
1120 else
1121 /* Added to avoid the discontinuity problem caused by pdiblcb */
1122 { T4 = 1.0 / (0.8 + T7);
1123 T3 = (17.0 + 20.0 * T7) * T4;
1124 dVADIBL_dVg *= T3;
1125 dVADIBL_dVb = dVADIBL_dVb * T3
1126 - VADIBL * pParam->BSIM3v32pdiblb * T4 * T4;
1127 dVADIBL_dVd *= T3;
1128 VADIBL *= T3;
1129 }
1130 }
1131 else
1132 { VADIBL = MAX_EXP;
1133 dVADIBL_dVd = dVADIBL_dVg = dVADIBL_dVb = 0.0;
1134 }
1135
1136 /* Calculate VA */
1137
1138 T8 = pParam->BSIM3v32pvag / EsatL;
1139 T9 = T8 * Vgsteff;
1140 if (T9 > -0.9)
1141 { T0 = 1.0 + T9;
1142 dT0_dVg = T8 * (1.0 - Vgsteff * dEsatL_dVg / EsatL);
1143 dT0_dVb = -T9 * dEsatL_dVb / EsatL;
1144 dT0_dVd = -T9 * dEsatL_dVd / EsatL;
1145 }
1146 else /* Added to avoid the discontinuity problems caused by pvag */
1147 { T1 = 1.0 / (17.0 + 20.0 * T9);
1148 T0 = (0.8 + T9) * T1;
1149 T1 *= T1;
1150 dT0_dVg = T8 * (1.0 - Vgsteff * dEsatL_dVg / EsatL) * T1;
1151
1152 T9 *= T1 / EsatL;
1153 dT0_dVb = -T9 * dEsatL_dVb;
1154 dT0_dVd = -T9 * dEsatL_dVd;
1155 }
1156
1157 tmp1 = VACLM * VACLM;
1158 tmp2 = VADIBL * VADIBL;
1159 tmp3 = VACLM + VADIBL;
1160
1161 T1 = VACLM * VADIBL / tmp3;
1162 tmp3 *= tmp3;
1163 dT1_dVg = (tmp1 * dVADIBL_dVg + tmp2 * dVACLM_dVg) / tmp3;
1164 dT1_dVd = (tmp1 * dVADIBL_dVd + tmp2 * dVACLM_dVd) / tmp3;
1165 dT1_dVb = (tmp1 * dVADIBL_dVb + tmp2 * dVACLM_dVb) / tmp3;
1166
1167 Va = Vasat + T0 * T1;
1168 dVa_dVg = dVasat_dVg + T1 * dT0_dVg + T0 * dT1_dVg;
1169 dVa_dVd = dVasat_dVd + T1 * dT0_dVd + T0 * dT1_dVd;
1170 dVa_dVb = dVasat_dVb + T1 * dT0_dVb + T0 * dT1_dVb;
1171
1172 /* Calculate VASCBE */
1173 if (pParam->BSIM3v32pscbe2 > 0.0)
1174 { if (diffVds > pParam->BSIM3v32pscbe1 * pParam->BSIM3v32litl
1175 / EXP_THRESHOLD)
1176 { T0 = pParam->BSIM3v32pscbe1 * pParam->BSIM3v32litl / diffVds;
1177 VASCBE = Leff * exp(T0) / pParam->BSIM3v32pscbe2;
1178 T1 = T0 * VASCBE / diffVds;
1179 dVASCBE_dVg = T1 * dVdseff_dVg;
1180 dVASCBE_dVd = -T1 * (1.0 - dVdseff_dVd);
1181 dVASCBE_dVb = T1 * dVdseff_dVb;
1182 }
1183 else
1184 { VASCBE = MAX_EXP * Leff/pParam->BSIM3v32pscbe2;
1185 dVASCBE_dVg = dVASCBE_dVd = dVASCBE_dVb = 0.0;
1186 }
1187 }
1188 else
1189 { VASCBE = MAX_EXP;
1190 dVASCBE_dVg = dVASCBE_dVd = dVASCBE_dVb = 0.0;
1191 }
1192
1193 /* Calculate Ids */
1194 CoxWovL = model->BSIM3v32cox * Weff / Leff;
1195 beta = ueff * CoxWovL;
1196 dbeta_dVg = CoxWovL * dueff_dVg + beta * dWeff_dVg / Weff;
1197 dbeta_dVd = CoxWovL * dueff_dVd;
1198 dbeta_dVb = CoxWovL * dueff_dVb + beta * dWeff_dVb / Weff;
1199
1200 T0 = 1.0 - 0.5 * Abulk * Vdseff / Vgst2Vtm;
1201 dT0_dVg = -0.5 * (Abulk * dVdseff_dVg
1202 - Abulk * Vdseff / Vgst2Vtm + Vdseff * dAbulk_dVg) / Vgst2Vtm;
1203 dT0_dVd = -0.5 * Abulk * dVdseff_dVd / Vgst2Vtm;
1204 dT0_dVb = -0.5 * (Abulk * dVdseff_dVb + dAbulk_dVb * Vdseff)
1205 / Vgst2Vtm;
1206
1207 fgche1 = Vgsteff * T0;
1208 dfgche1_dVg = Vgsteff * dT0_dVg + T0;
1209 dfgche1_dVd = Vgsteff * dT0_dVd;
1210 dfgche1_dVb = Vgsteff * dT0_dVb;
1211
1212 T9 = Vdseff / EsatL;
1213 fgche2 = 1.0 + T9;
1214 dfgche2_dVg = (dVdseff_dVg - T9 * dEsatL_dVg) / EsatL;
1215 dfgche2_dVd = (dVdseff_dVd - T9 * dEsatL_dVd) / EsatL;
1216 dfgche2_dVb = (dVdseff_dVb - T9 * dEsatL_dVb) / EsatL;
1217
1218 gche = beta * fgche1 / fgche2;
1219 dgche_dVg = (beta * dfgche1_dVg + fgche1 * dbeta_dVg
1220 - gche * dfgche2_dVg) / fgche2;
1221 dgche_dVd = (beta * dfgche1_dVd + fgche1 * dbeta_dVd
1222 - gche * dfgche2_dVd) / fgche2;
1223 dgche_dVb = (beta * dfgche1_dVb + fgche1 * dbeta_dVb
1224 - gche * dfgche2_dVb) / fgche2;
1225
1226 T0 = 1.0 + gche * Rds;
1227 T9 = Vdseff / T0;
1228 Idl = gche * T9;
1229
1230 dIdl_dVg = (gche * dVdseff_dVg + T9 * dgche_dVg) / T0
1231 - Idl * gche / T0 * dRds_dVg ;
1232
1233 dIdl_dVd = (gche * dVdseff_dVd + T9 * dgche_dVd) / T0;
1234 dIdl_dVb = (gche * dVdseff_dVb + T9 * dgche_dVb
1235 - Idl * dRds_dVb * gche) / T0;
1236
1237 T9 = diffVds / Va;
1238 T0 = 1.0 + T9;
1239 Idsa = Idl * T0;
1240 dIdsa_dVg = T0 * dIdl_dVg - Idl * (dVdseff_dVg + T9 * dVa_dVg) / Va;
1241 dIdsa_dVd = T0 * dIdl_dVd + Idl * (1.0 - dVdseff_dVd
1242 - T9 * dVa_dVd) / Va;
1243 dIdsa_dVb = T0 * dIdl_dVb - Idl * (dVdseff_dVb + T9 * dVa_dVb) / Va;
1244
1245 T9 = diffVds / VASCBE;
1246 T0 = 1.0 + T9;
1247 Ids = Idsa * T0;
1248
1249 Gm = T0 * dIdsa_dVg - Idsa * (dVdseff_dVg + T9 * dVASCBE_dVg) / VASCBE;
1250 Gds = T0 * dIdsa_dVd + Idsa * (1.0 - dVdseff_dVd
1251 - T9 * dVASCBE_dVd) / VASCBE;
1252 Gmb = T0 * dIdsa_dVb - Idsa * (dVdseff_dVb
1253 + T9 * dVASCBE_dVb) / VASCBE;
1254
1255 Gds += Gm * dVgsteff_dVd;
1256 Gmb += Gm * dVgsteff_dVb;
1257 Gm *= dVgsteff_dVg;
1258 Gmb *= dVbseff_dVb;
1259
1260 /* Substrate current begins */
1261 tmp = pParam->BSIM3v32alpha0 + pParam->BSIM3v32alpha1 * Leff;
1262 if ((tmp <= 0.0) || (pParam->BSIM3v32beta0 <= 0.0))
1263 { Isub = Gbd = Gbb = Gbg = 0.0;
1264 }
1265 else
1266 { T2 = tmp / Leff;
1267 if (diffVds > pParam->BSIM3v32beta0 / EXP_THRESHOLD)
1268 { T0 = -pParam->BSIM3v32beta0 / diffVds;
1269 T1 = T2 * diffVds * exp(T0);
1270 T3 = T1 / diffVds * (T0 - 1.0);
1271 dT1_dVg = T3 * dVdseff_dVg;
1272 dT1_dVd = T3 * (dVdseff_dVd - 1.0);
1273 dT1_dVb = T3 * dVdseff_dVb;
1274 }
1275 else
1276 { T3 = T2 * MIN_EXP;
1277 T1 = T3 * diffVds;
1278 dT1_dVg = -T3 * dVdseff_dVg;
1279 dT1_dVd = T3 * (1.0 - dVdseff_dVd);
1280 dT1_dVb = -T3 * dVdseff_dVb;
1281 }
1282 Isub = T1 * Idsa;
1283 Gbg = T1 * dIdsa_dVg + Idsa * dT1_dVg;
1284 Gbd = T1 * dIdsa_dVd + Idsa * dT1_dVd;
1285 Gbb = T1 * dIdsa_dVb + Idsa * dT1_dVb;
1286
1287 Gbd += Gbg * dVgsteff_dVd;
1288 Gbb += Gbg * dVgsteff_dVb;
1289 Gbg *= dVgsteff_dVg;
1290 Gbb *= dVbseff_dVb; /* bug fixing */
1291 }
1292
1293 cdrain = Ids;
1294 here->BSIM3v32gds = Gds;
1295 here->BSIM3v32gm = Gm;
1296 here->BSIM3v32gmbs = Gmb;
1297
1298 here->BSIM3v32gbbs = Gbb;
1299 here->BSIM3v32gbgs = Gbg;
1300 here->BSIM3v32gbds = Gbd;
1301
1302 here->BSIM3v32csub = Isub;
1303
1304 /* BSIM3v32 thermal noise Qinv calculated from all capMod
1305 * 0, 1, 2 & 3 stored in here->BSIM3v32qinv 1/1998 */
1306
1307 if ((model->BSIM3v32xpart < 0) || (!ChargeComputationNeeded))
1308 { qgate = qdrn = qsrc = qbulk = 0.0;
1309 here->BSIM3v32cggb = here->BSIM3v32cgsb = here->BSIM3v32cgdb = 0.0;
1310 here->BSIM3v32cdgb = here->BSIM3v32cdsb = here->BSIM3v32cddb = 0.0;
1311 here->BSIM3v32cbgb = here->BSIM3v32cbsb = here->BSIM3v32cbdb = 0.0;
1312 here->BSIM3v32cqdb = here->BSIM3v32cqsb = here->BSIM3v32cqgb
1313 = here->BSIM3v32cqbb = 0.0;
1314 here->BSIM3v32gtau = 0.0;
1315 goto finished;
1316 }
1317 else if (model->BSIM3v32capMod == 0)
1318 {
1319 if (Vbseff < 0.0)
1320 { Vbseff = Vbs;
1321 dVbseff_dVb = 1.0;
1322 }
1323 else
1324 { Vbseff = pParam->BSIM3v32phi - Phis;
1325 dVbseff_dVb = -dPhis_dVb;
1326 }
1327
1328 Vfb = pParam->BSIM3v32vfbcv;
1329 Vth = Vfb + pParam->BSIM3v32phi + pParam->BSIM3v32k1ox * sqrtPhis;
1330 Vgst = Vgs_eff - Vth;
1331 dVth_dVb = pParam->BSIM3v32k1ox * dsqrtPhis_dVb;
1332 dVgst_dVb = -dVth_dVb;
1333 dVgst_dVg = dVgs_eff_dVg;
1334
1335 CoxWL = model->BSIM3v32cox * pParam->BSIM3v32weffCV
1336 * pParam->BSIM3v32leffCV;
1337 Arg1 = Vgs_eff - Vbseff - Vfb;
1338
1339 if (Arg1 <= 0.0)
1340 { qgate = CoxWL * Arg1;
1341 qbulk = -qgate;
1342 qdrn = 0.0;
1343
1344 here->BSIM3v32cggb = CoxWL * dVgs_eff_dVg;
1345 here->BSIM3v32cgdb = 0.0;
1346 here->BSIM3v32cgsb = CoxWL * (dVbseff_dVb - dVgs_eff_dVg);
1347
1348 here->BSIM3v32cdgb = 0.0;
1349 here->BSIM3v32cddb = 0.0;
1350 here->BSIM3v32cdsb = 0.0;
1351
1352 here->BSIM3v32cbgb = -CoxWL * dVgs_eff_dVg;
1353 here->BSIM3v32cbdb = 0.0;
1354 here->BSIM3v32cbsb = -here->BSIM3v32cgsb;
1355 here->BSIM3v32qinv = 0.0;
1356 }
1357 else if (Vgst <= 0.0)
1358 { T1 = 0.5 * pParam->BSIM3v32k1ox;
1359 T2 = sqrt(T1 * T1 + Arg1);
1360 qgate = CoxWL * pParam->BSIM3v32k1ox * (T2 - T1);
1361 qbulk = -qgate;
1362 qdrn = 0.0;
1363
1364 T0 = CoxWL * T1 / T2;
1365 here->BSIM3v32cggb = T0 * dVgs_eff_dVg;
1366 here->BSIM3v32cgdb = 0.0;
1367 here->BSIM3v32cgsb = T0 * (dVbseff_dVb - dVgs_eff_dVg);
1368
1369 here->BSIM3v32cdgb = 0.0;
1370 here->BSIM3v32cddb = 0.0;
1371 here->BSIM3v32cdsb = 0.0;
1372
1373 here->BSIM3v32cbgb = -here->BSIM3v32cggb;
1374 here->BSIM3v32cbdb = 0.0;
1375 here->BSIM3v32cbsb = -here->BSIM3v32cgsb;
1376 here->BSIM3v32qinv = 0.0;
1377 }
1378 else
1379 { One_Third_CoxWL = CoxWL / 3.0;
1380 Two_Third_CoxWL = 2.0 * One_Third_CoxWL;
1381
1382 AbulkCV = Abulk0 * pParam->BSIM3v32abulkCVfactor;
1383 dAbulkCV_dVb = pParam->BSIM3v32abulkCVfactor * dAbulk0_dVb;
1384 Vdsat = Vgst / AbulkCV;
1385 dVdsat_dVg = dVgs_eff_dVg / AbulkCV;
1386 dVdsat_dVb = - (Vdsat * dAbulkCV_dVb + dVth_dVb)/ AbulkCV;
1387
1388 if (model->BSIM3v32xpart > 0.5)
1389 { /* 0/100 Charge partition model */
1390 if (Vdsat <= Vds)
1391 { /* saturation region */
1392 T1 = Vdsat / 3.0;
1393 qgate = CoxWL * (Vgs_eff - Vfb
1394 - pParam->BSIM3v32phi - T1);
1395 T2 = -Two_Third_CoxWL * Vgst;
1396 qbulk = -(qgate + T2);
1397 qdrn = 0.0;
1398
1399 here->BSIM3v32cggb = One_Third_CoxWL * (3.0
1400 - dVdsat_dVg) * dVgs_eff_dVg;
1401 T2 = -One_Third_CoxWL * dVdsat_dVb;
1402 here->BSIM3v32cgsb = -(here->BSIM3v32cggb + T2);
1403 here->BSIM3v32cgdb = 0.0;
1404
1405 here->BSIM3v32cdgb = 0.0;
1406 here->BSIM3v32cddb = 0.0;
1407 here->BSIM3v32cdsb = 0.0;
1408
1409 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1410 - Two_Third_CoxWL * dVgs_eff_dVg);
1411 T3 = -(T2 + Two_Third_CoxWL * dVth_dVb);
1412 here->BSIM3v32cbsb = -(here->BSIM3v32cbgb + T3);
1413 here->BSIM3v32cbdb = 0.0;
1414 here->BSIM3v32qinv = -(qgate + qbulk);
1415 }
1416 else
1417 { /* linear region */
1418 Alphaz = Vgst / Vdsat;
1419 T1 = 2.0 * Vdsat - Vds;
1420 T2 = Vds / (3.0 * T1);
1421 T3 = T2 * Vds;
1422 T9 = 0.25 * CoxWL;
1423 T4 = T9 * Alphaz;
1424 T7 = 2.0 * Vds - T1 - 3.0 * T3;
1425 T8 = T3 - T1 - 2.0 * Vds;
1426 qgate = CoxWL * (Vgs_eff - Vfb
1427 - pParam->BSIM3v32phi - 0.5 * (Vds - T3));
1428 T10 = T4 * T8;
1429 qdrn = T4 * T7;
1430 qbulk = -(qgate + qdrn + T10);
1431
1432 T5 = T3 / T1;
1433 here->BSIM3v32cggb = CoxWL * (1.0 - T5 * dVdsat_dVg)
1434 * dVgs_eff_dVg;
1435 T11 = -CoxWL * T5 * dVdsat_dVb;
1436 here->BSIM3v32cgdb = CoxWL * (T2 - 0.5 + 0.5 * T5);
1437 here->BSIM3v32cgsb = -(here->BSIM3v32cggb + T11
1438 + here->BSIM3v32cgdb);
1439 T6 = 1.0 / Vdsat;
1440 dAlphaz_dVg = T6 * (1.0 - Alphaz * dVdsat_dVg);
1441 dAlphaz_dVb = -T6 * (dVth_dVb + Alphaz * dVdsat_dVb);
1442 T7 = T9 * T7;
1443 T8 = T9 * T8;
1444 T9 = 2.0 * T4 * (1.0 - 3.0 * T5);
1445 here->BSIM3v32cdgb = (T7 * dAlphaz_dVg - T9
1446 * dVdsat_dVg) * dVgs_eff_dVg;
1447 T12 = T7 * dAlphaz_dVb - T9 * dVdsat_dVb;
1448 here->BSIM3v32cddb = T4 * (3.0 - 6.0 * T2 - 3.0 * T5);
1449 here->BSIM3v32cdsb = -(here->BSIM3v32cdgb + T12
1450 + here->BSIM3v32cddb);
1451
1452 T9 = 2.0 * T4 * (1.0 + T5);
1453 T10 = (T8 * dAlphaz_dVg - T9 * dVdsat_dVg)
1454 * dVgs_eff_dVg;
1455 T11 = T8 * dAlphaz_dVb - T9 * dVdsat_dVb;
1456 T12 = T4 * (2.0 * T2 + T5 - 1.0);
1457 T0 = -(T10 + T11 + T12);
1458
1459 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1460 + here->BSIM3v32cdgb + T10);
1461 here->BSIM3v32cbdb = -(here->BSIM3v32cgdb
1462 + here->BSIM3v32cddb + T12);
1463 here->BSIM3v32cbsb = -(here->BSIM3v32cgsb
1464 + here->BSIM3v32cdsb + T0);
1465 here->BSIM3v32qinv = -(qgate + qbulk);
1466 }
1467 }
1468 else if (model->BSIM3v32xpart < 0.5)
1469 { /* 40/60 Charge partition model */
1470 if (Vds >= Vdsat)
1471 { /* saturation region */
1472 T1 = Vdsat / 3.0;
1473 qgate = CoxWL * (Vgs_eff - Vfb
1474 - pParam->BSIM3v32phi - T1);
1475 T2 = -Two_Third_CoxWL * Vgst;
1476 qbulk = -(qgate + T2);
1477 qdrn = 0.4 * T2;
1478
1479 here->BSIM3v32cggb = One_Third_CoxWL * (3.0
1480 - dVdsat_dVg) * dVgs_eff_dVg;
1481 T2 = -One_Third_CoxWL * dVdsat_dVb;
1482 here->BSIM3v32cgsb = -(here->BSIM3v32cggb + T2);
1483 here->BSIM3v32cgdb = 0.0;
1484
1485 T3 = 0.4 * Two_Third_CoxWL;
1486 here->BSIM3v32cdgb = -T3 * dVgs_eff_dVg;
1487 here->BSIM3v32cddb = 0.0;
1488 T4 = T3 * dVth_dVb;
1489 here->BSIM3v32cdsb = -(T4 + here->BSIM3v32cdgb);
1490
1491 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1492 - Two_Third_CoxWL * dVgs_eff_dVg);
1493 T3 = -(T2 + Two_Third_CoxWL * dVth_dVb);
1494 here->BSIM3v32cbsb = -(here->BSIM3v32cbgb + T3);
1495 here->BSIM3v32cbdb = 0.0;
1496 here->BSIM3v32qinv = -(qgate + qbulk);
1497 }
1498 else
1499 { /* linear region */
1500 Alphaz = Vgst / Vdsat;
1501 T1 = 2.0 * Vdsat - Vds;
1502 T2 = Vds / (3.0 * T1);
1503 T3 = T2 * Vds;
1504 T9 = 0.25 * CoxWL;
1505 T4 = T9 * Alphaz;
1506 qgate = CoxWL * (Vgs_eff - Vfb - pParam->BSIM3v32phi
1507 - 0.5 * (Vds - T3));
1508
1509 T5 = T3 / T1;
1510 here->BSIM3v32cggb = CoxWL * (1.0 - T5 * dVdsat_dVg)
1511 * dVgs_eff_dVg;
1512 tmp = -CoxWL * T5 * dVdsat_dVb;
1513 here->BSIM3v32cgdb = CoxWL * (T2 - 0.5 + 0.5 * T5);
1514 here->BSIM3v32cgsb = -(here->BSIM3v32cggb
1515 + here->BSIM3v32cgdb + tmp);
1516
1517 T6 = 1.0 / Vdsat;
1518 dAlphaz_dVg = T6 * (1.0 - Alphaz * dVdsat_dVg);
1519 dAlphaz_dVb = -T6 * (dVth_dVb + Alphaz * dVdsat_dVb);
1520
1521 T6 = 8.0 * Vdsat * Vdsat - 6.0 * Vdsat * Vds
1522 + 1.2 * Vds * Vds;
1523 T8 = T2 / T1;
1524 T7 = Vds - T1 - T8 * T6;
1525 qdrn = T4 * T7;
1526 T7 *= T9;
1527 tmp = T8 / T1;
1528 tmp1 = T4 * (2.0 - 4.0 * tmp * T6
1529 + T8 * (16.0 * Vdsat - 6.0 * Vds));
1530
1531 here->BSIM3v32cdgb = (T7 * dAlphaz_dVg - tmp1
1532 * dVdsat_dVg) * dVgs_eff_dVg;
1533 T10 = T7 * dAlphaz_dVb - tmp1 * dVdsat_dVb;
1534 here->BSIM3v32cddb = T4 * (2.0 - (1.0 / (3.0 * T1
1535 * T1) + 2.0 * tmp) * T6 + T8
1536 * (6.0 * Vdsat - 2.4 * Vds));
1537 here->BSIM3v32cdsb = -(here->BSIM3v32cdgb
1538 + T10 + here->BSIM3v32cddb);
1539
1540 T7 = 2.0 * (T1 + T3);
1541 qbulk = -(qgate - T4 * T7);
1542 T7 *= T9;
1543 T0 = 4.0 * T4 * (1.0 - T5);
1544 T12 = (-T7 * dAlphaz_dVg - here->BSIM3v32cdgb
1545 - T0 * dVdsat_dVg) * dVgs_eff_dVg;
1546 T11 = -T7 * dAlphaz_dVb - T10 - T0 * dVdsat_dVb;
1547 T10 = -4.0 * T4 * (T2 - 0.5 + 0.5 * T5)
1548 - here->BSIM3v32cddb;
1549 tmp = -(T10 + T11 + T12);
1550
1551 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1552 + here->BSIM3v32cdgb + T12);
1553 here->BSIM3v32cbdb = -(here->BSIM3v32cgdb
1554 + here->BSIM3v32cddb + T10); /* bug fix */
1555 here->BSIM3v32cbsb = -(here->BSIM3v32cgsb
1556 + here->BSIM3v32cdsb + tmp);
1557 here->BSIM3v32qinv = -(qgate + qbulk);
1558 }
1559 }
1560 else
1561 { /* 50/50 partitioning */
1562 if (Vds >= Vdsat)
1563 { /* saturation region */
1564 T1 = Vdsat / 3.0;
1565 qgate = CoxWL * (Vgs_eff - Vfb
1566 - pParam->BSIM3v32phi - T1);
1567 T2 = -Two_Third_CoxWL * Vgst;
1568 qbulk = -(qgate + T2);
1569 qdrn = 0.5 * T2;
1570
1571 here->BSIM3v32cggb = One_Third_CoxWL * (3.0
1572 - dVdsat_dVg) * dVgs_eff_dVg;
1573 T2 = -One_Third_CoxWL * dVdsat_dVb;
1574 here->BSIM3v32cgsb = -(here->BSIM3v32cggb + T2);
1575 here->BSIM3v32cgdb = 0.0;
1576
1577 here->BSIM3v32cdgb = -One_Third_CoxWL * dVgs_eff_dVg;
1578 here->BSIM3v32cddb = 0.0;
1579 T4 = One_Third_CoxWL * dVth_dVb;
1580 here->BSIM3v32cdsb = -(T4 + here->BSIM3v32cdgb);
1581
1582 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1583 - Two_Third_CoxWL * dVgs_eff_dVg);
1584 T3 = -(T2 + Two_Third_CoxWL * dVth_dVb);
1585 here->BSIM3v32cbsb = -(here->BSIM3v32cbgb + T3);
1586 here->BSIM3v32cbdb = 0.0;
1587 here->BSIM3v32qinv = -(qgate + qbulk);
1588 }
1589 else
1590 { /* linear region */
1591 Alphaz = Vgst / Vdsat;
1592 T1 = 2.0 * Vdsat - Vds;
1593 T2 = Vds / (3.0 * T1);
1594 T3 = T2 * Vds;
1595 T9 = 0.25 * CoxWL;
1596 T4 = T9 * Alphaz;
1597 qgate = CoxWL * (Vgs_eff - Vfb - pParam->BSIM3v32phi
1598 - 0.5 * (Vds - T3));
1599
1600 T5 = T3 / T1;
1601 here->BSIM3v32cggb = CoxWL * (1.0 - T5 * dVdsat_dVg)
1602 * dVgs_eff_dVg;
1603 tmp = -CoxWL * T5 * dVdsat_dVb;
1604 here->BSIM3v32cgdb = CoxWL * (T2 - 0.5 + 0.5 * T5);
1605 here->BSIM3v32cgsb = -(here->BSIM3v32cggb
1606 + here->BSIM3v32cgdb + tmp);
1607
1608 T6 = 1.0 / Vdsat;
1609 dAlphaz_dVg = T6 * (1.0 - Alphaz * dVdsat_dVg);
1610 dAlphaz_dVb = -T6 * (dVth_dVb + Alphaz * dVdsat_dVb);
1611
1612 T7 = T1 + T3;
1613 qdrn = -T4 * T7;
1614 qbulk = - (qgate + qdrn + qdrn);
1615 T7 *= T9;
1616 T0 = T4 * (2.0 * T5 - 2.0);
1617
1618 here->BSIM3v32cdgb = (T0 * dVdsat_dVg - T7
1619 * dAlphaz_dVg) * dVgs_eff_dVg;
1620 T12 = T0 * dVdsat_dVb - T7 * dAlphaz_dVb;
1621 here->BSIM3v32cddb = T4 * (1.0 - 2.0 * T2 - T5);
1622 here->BSIM3v32cdsb = -(here->BSIM3v32cdgb + T12
1623 + here->BSIM3v32cddb);
1624
1625 here->BSIM3v32cbgb = -(here->BSIM3v32cggb
1626 + 2.0 * here->BSIM3v32cdgb);
1627 here->BSIM3v32cbdb = -(here->BSIM3v32cgdb
1628 + 2.0 * here->BSIM3v32cddb);
1629 here->BSIM3v32cbsb = -(here->BSIM3v32cgsb
1630 + 2.0 * here->BSIM3v32cdsb);
1631 here->BSIM3v32qinv = -(qgate + qbulk);
1632 }
1633 }
1634 }
1635 }
1636 else
1637 { if (Vbseff < 0.0)
1638 { VbseffCV = Vbseff;
1639 dVbseffCV_dVb = 1.0;
1640 }
1641 else
1642 { VbseffCV = pParam->BSIM3v32phi - Phis;
1643 dVbseffCV_dVb = -dPhis_dVb;
1644 }
1645
1646 CoxWL = model->BSIM3v32cox * pParam->BSIM3v32weffCV
1647 * pParam->BSIM3v32leffCV;
1648
1649 /* Seperate VgsteffCV with noff and voffcv */
1650 noff = n * pParam->BSIM3v32noff;
1651 dnoff_dVd = pParam->BSIM3v32noff * dn_dVd;
1652 dnoff_dVb = pParam->BSIM3v32noff * dn_dVb;
1653 T0 = Vtm * noff;
1654 voffcv = pParam->BSIM3v32voffcv;
1655 VgstNVt = (Vgst - voffcv) / T0;
1656
1657 if (VgstNVt > EXP_THRESHOLD)
1658 { Vgsteff = Vgst - voffcv;
1659 dVgsteff_dVg = dVgs_eff_dVg;
1660 dVgsteff_dVd = -dVth_dVd;
1661 dVgsteff_dVb = -dVth_dVb;
1662 }
1663 else if (VgstNVt < -EXP_THRESHOLD)
1664 { Vgsteff = T0 * log(1.0 + MIN_EXP);
1665 dVgsteff_dVg = 0.0;
1666 dVgsteff_dVd = Vgsteff / noff;
1667 dVgsteff_dVb = dVgsteff_dVd * dnoff_dVb;
1668 dVgsteff_dVd *= dnoff_dVd;
1669 }
1670 else
1671 { ExpVgst = exp(VgstNVt);
1672 Vgsteff = T0 * log(1.0 + ExpVgst);
1673 dVgsteff_dVg = ExpVgst / (1.0 + ExpVgst);
1674 dVgsteff_dVd = -dVgsteff_dVg * (dVth_dVd + (Vgst - voffcv)
1675 / noff * dnoff_dVd) + Vgsteff / noff * dnoff_dVd;
1676 dVgsteff_dVb = -dVgsteff_dVg * (dVth_dVb + (Vgst - voffcv)
1677 / noff * dnoff_dVb) + Vgsteff / noff * dnoff_dVb;
1678 dVgsteff_dVg *= dVgs_eff_dVg;
1679 } /* End of VgsteffCV */
1680
1681 if (model->BSIM3v32capMod == 1)
1682 {
1683 /* Added revision dependent code */
1684 switch (model->BSIM3v32intVersion) {
1685 case BSIM3v32V324:
1686 case BSIM3v32V323:
1687 case BSIM3v32V322:
1688 Vfb = here->BSIM3v32vfbzb;
1689 break;
1690 case BSIM3v32V32:
1691 Vfb = here->BSIM3v32vfbzb;
1692 dVfb_dVb = dVfb_dVd = 0.0;
1693 break;
1694 default:
1695 Vfb = Vth - pParam->BSIM3v32phi - pParam->BSIM3v32k1ox * sqrtPhis;
1696 dVfb_dVb = dVth_dVb - pParam->BSIM3v32k1ox * dsqrtPhis_dVb;
1697 dVfb_dVd = dVth_dVd;
1698 }
1699
1700 Arg1 = Vgs_eff - VbseffCV - Vfb - Vgsteff;
1701
1702 if (Arg1 <= 0.0)
1703 { qgate = CoxWL * Arg1;
1704 Cgg = CoxWL * (dVgs_eff_dVg - dVgsteff_dVg);
1705 /* Added revision dependent code */
1706 switch (model->BSIM3v32intVersion) {
1707 case BSIM3v32V324:
1708 case BSIM3v32V323:
1709 case BSIM3v32V322:
1710 Cgd = -CoxWL * dVgsteff_dVd;
1711 Cgb = -CoxWL * (dVbseffCV_dVb + dVgsteff_dVb);
1712 break;
1713 case BSIM3v32V32:
1714 default:
1715 Cgd = -CoxWL * (dVfb_dVd + dVgsteff_dVd);
1716 Cgb = -CoxWL * (dVfb_dVb + dVbseffCV_dVb + dVgsteff_dVb);
1717 }
1718 }
1719 else
1720 { T0 = 0.5 * pParam->BSIM3v32k1ox;
1721 T1 = sqrt(T0 * T0 + Arg1);
1722 T2 = CoxWL * T0 / T1;
1723
1724 qgate = CoxWL * pParam->BSIM3v32k1ox * (T1 - T0);
1725
1726 Cgg = T2 * (dVgs_eff_dVg - dVgsteff_dVg);
1727 /* Added revision dependent code */
1728 switch (model->BSIM3v32intVersion) {
1729 case BSIM3v32V324:
1730 case BSIM3v32V323:
1731 case BSIM3v32V322:
1732 Cgd = -T2 * dVgsteff_dVd;
1733 Cgb = -T2 * (dVbseffCV_dVb + dVgsteff_dVb);
1734 break;
1735 case BSIM3v32V32:
1736 default:
1737 Cgd = -T2 * (dVfb_dVd + dVgsteff_dVd);
1738 Cgb = -T2 * (dVfb_dVb + dVbseffCV_dVb + dVgsteff_dVb);
1739 }
1740 }
1741 qbulk = -qgate;
1742 Cbg = -Cgg;
1743 Cbd = -Cgd;
1744 Cbb = -Cgb;
1745
1746 One_Third_CoxWL = CoxWL / 3.0;
1747 Two_Third_CoxWL = 2.0 * One_Third_CoxWL;
1748 AbulkCV = Abulk0 * pParam->BSIM3v32abulkCVfactor;
1749 dAbulkCV_dVb = pParam->BSIM3v32abulkCVfactor * dAbulk0_dVb;
1750 VdsatCV = Vgsteff / AbulkCV;
1751 if (VdsatCV < Vds)
1752 { dVdsatCV_dVg = 1.0 / AbulkCV;
1753 dVdsatCV_dVb = -VdsatCV * dAbulkCV_dVb / AbulkCV;
1754 T0 = Vgsteff - VdsatCV / 3.0;
1755 dT0_dVg = 1.0 - dVdsatCV_dVg / 3.0;
1756 dT0_dVb = -dVdsatCV_dVb / 3.0;
1757 qgate += CoxWL * T0;
1758 Cgg1 = CoxWL * dT0_dVg;
1759 Cgb1 = CoxWL * dT0_dVb + Cgg1 * dVgsteff_dVb;
1760 Cgd1 = Cgg1 * dVgsteff_dVd;
1761 Cgg1 *= dVgsteff_dVg;
1762 Cgg += Cgg1;
1763 Cgb += Cgb1;
1764 Cgd += Cgd1;
1765
1766 T0 = VdsatCV - Vgsteff;
1767 dT0_dVg = dVdsatCV_dVg - 1.0;
1768 dT0_dVb = dVdsatCV_dVb;
1769 qbulk += One_Third_CoxWL * T0;
1770 Cbg1 = One_Third_CoxWL * dT0_dVg;
1771 Cbb1 = One_Third_CoxWL * dT0_dVb + Cbg1 * dVgsteff_dVb;
1772 Cbd1 = Cbg1 * dVgsteff_dVd;
1773 Cbg1 *= dVgsteff_dVg;
1774 Cbg += Cbg1;
1775 Cbb += Cbb1;
1776 Cbd += Cbd1;
1777
1778 if (model->BSIM3v32xpart > 0.5)
1779 T0 = -Two_Third_CoxWL;
1780 else if (model->BSIM3v32xpart < 0.5)
1781 T0 = -0.4 * CoxWL;
1782 else
1783 T0 = -One_Third_CoxWL;
1784
1785 qsrc = T0 * Vgsteff;
1786 Csg = T0 * dVgsteff_dVg;
1787 Csb = T0 * dVgsteff_dVb;
1788 Csd = T0 * dVgsteff_dVd;
1789 Cgb *= dVbseff_dVb;
1790 Cbb *= dVbseff_dVb;
1791 Csb *= dVbseff_dVb;
1792 }
1793 else
1794 { T0 = AbulkCV * Vds;
1795 T1 = 12.0 * (Vgsteff - 0.5 * T0 + 1.e-20);
1796 T2 = Vds / T1;
1797 T3 = T0 * T2;
1798 dT3_dVg = -12.0 * T2 * T2 * AbulkCV;
1799 dT3_dVd = 6.0 * T0 * (4.0 * Vgsteff - T0) / T1 / T1 - 0.5;
1800 dT3_dVb = 12.0 * T2 * T2 * dAbulkCV_dVb * Vgsteff;
1801
1802 qgate += CoxWL * (Vgsteff - 0.5 * Vds + T3);
1803 Cgg1 = CoxWL * (1.0 + dT3_dVg);
1804 Cgb1 = CoxWL * dT3_dVb + Cgg1 * dVgsteff_dVb;
1805 Cgd1 = CoxWL * dT3_dVd + Cgg1 * dVgsteff_dVd;
1806 Cgg1 *= dVgsteff_dVg;
1807 Cgg += Cgg1;
1808 Cgb += Cgb1;
1809 Cgd += Cgd1;
1810
1811 qbulk += CoxWL * (1.0 - AbulkCV) * (0.5 * Vds - T3);
1812 Cbg1 = -CoxWL * ((1.0 - AbulkCV) * dT3_dVg);
1813 Cbb1 = -CoxWL * ((1.0 - AbulkCV) * dT3_dVb
1814 + (0.5 * Vds - T3) * dAbulkCV_dVb)
1815 + Cbg1 * dVgsteff_dVb;
1816 Cbd1 = -CoxWL * (1.0 - AbulkCV) * dT3_dVd
1817 + Cbg1 * dVgsteff_dVd;
1818 Cbg1 *= dVgsteff_dVg;
1819 Cbg += Cbg1;
1820 Cbb += Cbb1;
1821 Cbd += Cbd1;
1822
1823 if (model->BSIM3v32xpart > 0.5)
1824 { /* 0/100 Charge petition model */
1825 T1 = T1 + T1;
1826 qsrc = -CoxWL * (0.5 * Vgsteff + 0.25 * T0
1827 - T0 * T0 / T1);
1828 Csg = -CoxWL * (0.5 + 24.0 * T0 * Vds / T1 / T1
1829 * AbulkCV);
1830 Csb = -CoxWL * (0.25 * Vds * dAbulkCV_dVb
1831 - 12.0 * T0 * Vds / T1 / T1 * (4.0 * Vgsteff - T0)
1832 * dAbulkCV_dVb) + Csg * dVgsteff_dVb;
1833 Csd = -CoxWL * (0.25 * AbulkCV - 12.0 * AbulkCV * T0
1834 / T1 / T1 * (4.0 * Vgsteff - T0))
1835 + Csg * dVgsteff_dVd;
1836 Csg *= dVgsteff_dVg;
1837 }
1838 else if (model->BSIM3v32xpart < 0.5)
1839 { /* 40/60 Charge petition model */
1840 T1 = T1 / 12.0;
1841 T2 = 0.5 * CoxWL / (T1 * T1);
1842 T3 = Vgsteff * (2.0 * T0 * T0 / 3.0 + Vgsteff
1843 * (Vgsteff - 4.0 * T0 / 3.0))
1844 - 2.0 * T0 * T0 * T0 / 15.0;
1845 qsrc = -T2 * T3;
1846 T4 = 4.0 / 3.0 * Vgsteff * (Vgsteff - T0)
1847 + 0.4 * T0 * T0;
1848 Csg = -2.0 * qsrc / T1 - T2 * (Vgsteff * (3.0
1849 * Vgsteff - 8.0 * T0 / 3.0)
1850 + 2.0 * T0 * T0 / 3.0);
1851 Csb = (qsrc / T1 * Vds + T2 * T4 * Vds) * dAbulkCV_dVb
1852 + Csg * dVgsteff_dVb;
1853 Csd = (qsrc / T1 + T2 * T4) * AbulkCV
1854 + Csg * dVgsteff_dVd;
1855 Csg *= dVgsteff_dVg;
1856 }
1857 else
1858 { /* 50/50 Charge petition model */
1859 qsrc = -0.5 * (qgate + qbulk);
1860 Csg = -0.5 * (Cgg1 + Cbg1);
1861 Csb = -0.5 * (Cgb1 + Cbb1);
1862 Csd = -0.5 * (Cgd1 + Cbd1);
1863 }
1864 Cgb *= dVbseff_dVb;
1865 Cbb *= dVbseff_dVb;
1866 Csb *= dVbseff_dVb;
1867 }
1868 qdrn = -(qgate + qbulk + qsrc);
1869 here->BSIM3v32cggb = Cgg;
1870 here->BSIM3v32cgsb = -(Cgg + Cgd + Cgb);
1871 here->BSIM3v32cgdb = Cgd;
1872 here->BSIM3v32cdgb = -(Cgg + Cbg + Csg);
1873 here->BSIM3v32cdsb = (Cgg + Cgd + Cgb + Cbg + Cbd + Cbb
1874 + Csg + Csd + Csb);
1875 here->BSIM3v32cddb = -(Cgd + Cbd + Csd);
1876 here->BSIM3v32cbgb = Cbg;
1877 here->BSIM3v32cbsb = -(Cbg + Cbd + Cbb);
1878 here->BSIM3v32cbdb = Cbd;
1879 here->BSIM3v32qinv = -(qgate + qbulk);
1880 }
1881
1882 else if (model->BSIM3v32capMod == 2)
1883 {
1884 /* Added revision dependent code */
1885 switch (model->BSIM3v32intVersion) {
1886 case BSIM3v32V324:
1887 case BSIM3v32V323:
1888 case BSIM3v32V322:
1889 Vfb = here->BSIM3v32vfbzb;
1890 break;
1891 case BSIM3v32V32:
1892 Vfb = here->BSIM3v32vfbzb;
1893 dVfb_dVb = dVfb_dVd = 0.0;
1894 break;
1895 default: /* old code prior to v3.2 */
1896 Vfb = Vth - pParam->BSIM3v32phi - pParam->BSIM3v32k1ox * sqrtPhis;
1897 dVfb_dVb = dVth_dVb - pParam->BSIM3v32k1ox * dsqrtPhis_dVb;
1898 dVfb_dVd = dVth_dVd;
1899 }
1900
1901 V3 = Vfb - Vgs_eff + VbseffCV - DELTA_3;
1902 if (Vfb <= 0.0)
1903 { T0 = sqrt(V3 * V3 - 4.0 * DELTA_3 * Vfb);
1904 T2 = -DELTA_3 / T0;
1905 }
1906 else
1907 { T0 = sqrt(V3 * V3 + 4.0 * DELTA_3 * Vfb);
1908 T2 = DELTA_3 / T0;
1909 }
1910
1911 T1 = 0.5 * (1.0 + V3 / T0);
1912 Vfbeff = Vfb - 0.5 * (V3 + T0);
1913 /* Added revision dependent code */
1914 switch (model->BSIM3v32intVersion) {
1915 case BSIM3v32V324:
1916 case BSIM3v32V323:
1917 case BSIM3v32V322:
1918 /* Do nothing */
1919 break;
1920 case BSIM3v32V32:
1921 default:
1922 dVfbeff_dVd = (1.0 - T1 - T2) * dVfb_dVd;
1923 }
1924 dVfbeff_dVg = T1 * dVgs_eff_dVg;
1925 /* Added revision dependent code */
1926 switch (model->BSIM3v32intVersion) {
1927 case BSIM3v32V324:
1928 case BSIM3v32V323:
1929 case BSIM3v32V322:
1930 dVfbeff_dVb = -T1 * dVbseffCV_dVb;
1931 break;
1932 case BSIM3v32V32:
1933 default:
1934 dVfbeff_dVb = (1.0 - T1 - T2) * dVfb_dVb - T1 * dVbseffCV_dVb;
1935 }
1936 Qac0 = CoxWL * (Vfbeff - Vfb);
1937 dQac0_dVg = CoxWL * dVfbeff_dVg;
1938 /* Added revision dependent code */
1939 switch (model->BSIM3v32intVersion) {
1940 case BSIM3v32V324:
1941 case BSIM3v32V323:
1942 case BSIM3v32V322:
1943 /* Do nothing */
1944 break;
1945 case BSIM3v32V32:
1946 default:
1947 dQac0_dVd = CoxWL * (dVfbeff_dVd - dVfb_dVd);
1948 }
1949 /* Added revision dependent code */
1950 switch (model->BSIM3v32intVersion) {
1951 case BSIM3v32V324:
1952 case BSIM3v32V323:
1953 case BSIM3v32V322:
1954 dQac0_dVb = CoxWL * dVfbeff_dVb;
1955 break;
1956 case BSIM3v32V32:
1957 default:
1958 dQac0_dVb = CoxWL * (dVfbeff_dVb - dVfb_dVb);
1959 }
1960
1961 T0 = 0.5 * pParam->BSIM3v32k1ox;
1962 T3 = Vgs_eff - Vfbeff - VbseffCV - Vgsteff;
1963 if (pParam->BSIM3v32k1ox == 0.0)
1964 { T1 = 0.0;
1965 T2 = 0.0;
1966 }
1967 else if (T3 < 0.0)
1968 { T1 = T0 + T3 / pParam->BSIM3v32k1ox;
1969 T2 = CoxWL;
1970 }
1971 else
1972 { T1 = sqrt(T0 * T0 + T3);
1973 T2 = CoxWL * T0 / T1;
1974 }
1975
1976 Qsub0 = CoxWL * pParam->BSIM3v32k1ox * (T1 - T0);
1977
1978 dQsub0_dVg = T2 * (dVgs_eff_dVg - dVfbeff_dVg - dVgsteff_dVg);
1979 /* Added revision dependent code */
1980 switch (model->BSIM3v32intVersion) {
1981 case BSIM3v32V324:
1982 case BSIM3v32V323:
1983 case BSIM3v32V322:
1984 dQsub0_dVd = -T2 * dVgsteff_dVd;
1985 break;
1986 case BSIM3v32V32:
1987 default:
1988 dQsub0_dVd = -T2 * (dVfbeff_dVd + dVgsteff_dVd);
1989 }
1990 dQsub0_dVb = -T2 * (dVfbeff_dVb + dVbseffCV_dVb
1991 + dVgsteff_dVb);
1992
1993 AbulkCV = Abulk0 * pParam->BSIM3v32abulkCVfactor;
1994 dAbulkCV_dVb = pParam->BSIM3v32abulkCVfactor * dAbulk0_dVb;
1995 VdsatCV = Vgsteff / AbulkCV;
1996
1997 V4 = VdsatCV - Vds - DELTA_4;
1998 T0 = sqrt(V4 * V4 + 4.0 * DELTA_4 * VdsatCV);
1999 VdseffCV = VdsatCV - 0.5 * (V4 + T0);
2000 T1 = 0.5 * (1.0 + V4 / T0);
2001 T2 = DELTA_4 / T0;
2002 T3 = (1.0 - T1 - T2) / AbulkCV;
2003 dVdseffCV_dVg = T3;
2004 dVdseffCV_dVd = T1;
2005 dVdseffCV_dVb = -T3 * VdsatCV * dAbulkCV_dVb;
2006 /* Added revision dependent code */
2007 switch (model->BSIM3v32intVersion) {
2008 case BSIM3v32V324:
2009 case BSIM3v32V323:
2010 case BSIM3v32V322:
2011 /* Added to eliminate non-zero VdseffCV at Vds=0.0 */
2012 if (Vds == 0.0)
2013 {
2014 VdseffCV = 0.0;
2015 dVdseffCV_dVg = 0.0;
2016 dVdseffCV_dVb = 0.0;
2017 }
2018 break;
2019 case BSIM3v32V32:
2020 default:
2021 /* Do nothing */
2022 break;
2023 }
2024
2025 T0 = AbulkCV * VdseffCV;
2026 T1 = 12.0 * (Vgsteff - 0.5 * T0 + 1e-20);
2027 T2 = VdseffCV / T1;
2028 T3 = T0 * T2;
2029
2030 T4 = (1.0 - 12.0 * T2 * T2 * AbulkCV);
2031 T5 = (6.0 * T0 * (4.0 * Vgsteff - T0) / (T1 * T1) - 0.5);
2032 T6 = 12.0 * T2 * T2 * Vgsteff;
2033
2034 qinoi = -CoxWL * (Vgsteff - 0.5 * T0 + AbulkCV * T3);
2035 qgate = CoxWL * (Vgsteff - 0.5 * VdseffCV + T3);
2036 Cgg1 = CoxWL * (T4 + T5 * dVdseffCV_dVg);
2037 Cgd1 = CoxWL * T5 * dVdseffCV_dVd + Cgg1 * dVgsteff_dVd;
2038 Cgb1 = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2039 + Cgg1 * dVgsteff_dVb;
2040 Cgg1 *= dVgsteff_dVg;
2041
2042 T7 = 1.0 - AbulkCV;
2043 qbulk = CoxWL * T7 * (0.5 * VdseffCV - T3);
2044 T4 = -T7 * (T4 - 1.0);
2045 T5 = -T7 * T5;
2046 T6 = -(T7 * T6 + (0.5 * VdseffCV - T3));
2047 Cbg1 = CoxWL * (T4 + T5 * dVdseffCV_dVg);
2048 Cbd1 = CoxWL * T5 * dVdseffCV_dVd + Cbg1 * dVgsteff_dVd;
2049 Cbb1 = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2050 + Cbg1 * dVgsteff_dVb;
2051 Cbg1 *= dVgsteff_dVg;
2052
2053 if (model->BSIM3v32xpart > 0.5)
2054 { /* 0/100 Charge petition model */
2055 T1 = T1 + T1;
2056 qsrc = -CoxWL * (0.5 * Vgsteff + 0.25 * T0
2057 - T0 * T0 / T1);
2058 T7 = (4.0 * Vgsteff - T0) / (T1 * T1);
2059 T4 = -(0.5 + 24.0 * T0 * T0 / (T1 * T1));
2060 T5 = -(0.25 * AbulkCV - 12.0 * AbulkCV * T0 * T7);
2061 T6 = -(0.25 * VdseffCV - 12.0 * T0 * VdseffCV * T7);
2062 Csg = CoxWL * (T4 + T5 * dVdseffCV_dVg);
2063 Csd = CoxWL * T5 * dVdseffCV_dVd + Csg * dVgsteff_dVd;
2064 Csb = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2065 + Csg * dVgsteff_dVb;
2066 Csg *= dVgsteff_dVg;
2067 }
2068 else if (model->BSIM3v32xpart < 0.5)
2069 { /* 40/60 Charge petition model */
2070 T1 = T1 / 12.0;
2071 T2 = 0.5 * CoxWL / (T1 * T1);
2072 T3 = Vgsteff * (2.0 * T0 * T0 / 3.0 + Vgsteff
2073 * (Vgsteff - 4.0 * T0 / 3.0))
2074 - 2.0 * T0 * T0 * T0 / 15.0;
2075 qsrc = -T2 * T3;
2076 T7 = 4.0 / 3.0 * Vgsteff * (Vgsteff - T0)
2077 + 0.4 * T0 * T0;
2078 T4 = -2.0 * qsrc / T1 - T2 * (Vgsteff * (3.0
2079 * Vgsteff - 8.0 * T0 / 3.0)
2080 + 2.0 * T0 * T0 / 3.0);
2081 T5 = (qsrc / T1 + T2 * T7) * AbulkCV;
2082 T6 = (qsrc / T1 * VdseffCV + T2 * T7 * VdseffCV);
2083 Csg = (T4 + T5 * dVdseffCV_dVg);
2084 Csd = T5 * dVdseffCV_dVd + Csg * dVgsteff_dVd;
2085 Csb = (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2086 + Csg * dVgsteff_dVb;
2087 Csg *= dVgsteff_dVg;
2088 }
2089 else
2090 { /* 50/50 Charge petition model */
2091 qsrc = -0.5 * (qgate + qbulk);
2092 Csg = -0.5 * (Cgg1 + Cbg1);
2093 Csb = -0.5 * (Cgb1 + Cbb1);
2094 Csd = -0.5 * (Cgd1 + Cbd1);
2095 }
2096
2097 qgate += Qac0 + Qsub0;
2098 qbulk -= (Qac0 + Qsub0);
2099 qdrn = -(qgate + qbulk + qsrc);
2100
2101 Cgg = dQac0_dVg + dQsub0_dVg + Cgg1;
2102 /* Added revision dependent code */
2103 switch (model->BSIM3v32intVersion) {
2104 case BSIM3v32V324:
2105 case BSIM3v32V323:
2106 case BSIM3v32V322:
2107 Cgd = dQsub0_dVd + Cgd1;
2108 break;
2109 case BSIM3v32V32:
2110 default:
2111 Cgd = dQac0_dVd + dQsub0_dVd + Cgd1;
2112 }
2113 Cgb = dQac0_dVb + dQsub0_dVb + Cgb1;
2114
2115 Cbg = Cbg1 - dQac0_dVg - dQsub0_dVg;
2116 /* Added revision dependent code */
2117 switch (model->BSIM3v32intVersion) {
2118 case BSIM3v32V324:
2119 case BSIM3v32V323:
2120 case BSIM3v32V322:
2121 Cbd = Cbd1 - dQsub0_dVd;
2122 break;
2123 case BSIM3v32V32:
2124 default:
2125 Cbd = Cbd1 - dQac0_dVd - dQsub0_dVd;
2126 }
2127 Cbb = Cbb1 - dQac0_dVb - dQsub0_dVb;
2128
2129 Cgb *= dVbseff_dVb;
2130 Cbb *= dVbseff_dVb;
2131 Csb *= dVbseff_dVb;
2132
2133 here->BSIM3v32cggb = Cgg;
2134 here->BSIM3v32cgsb = -(Cgg + Cgd + Cgb);
2135 here->BSIM3v32cgdb = Cgd;
2136 here->BSIM3v32cdgb = -(Cgg + Cbg + Csg);
2137 here->BSIM3v32cdsb = (Cgg + Cgd + Cgb + Cbg + Cbd + Cbb
2138 + Csg + Csd + Csb);
2139 here->BSIM3v32cddb = -(Cgd + Cbd + Csd);
2140 here->BSIM3v32cbgb = Cbg;
2141 here->BSIM3v32cbsb = -(Cbg + Cbd + Cbb);
2142 here->BSIM3v32cbdb = Cbd;
2143 here->BSIM3v32qinv = qinoi;
2144 }
2145
2146 /* New Charge-Thickness capMod (CTM) begins */
2147 else if (model->BSIM3v32capMod == 3)
2148 { V3 = here->BSIM3v32vfbzb - Vgs_eff + VbseffCV - DELTA_3;
2149 if (here->BSIM3v32vfbzb <= 0.0)
2150 { T0 = sqrt(V3 * V3 - 4.0 * DELTA_3 * here->BSIM3v32vfbzb);
2151 T2 = -DELTA_3 / T0;
2152 }
2153 else
2154 { T0 = sqrt(V3 * V3 + 4.0 * DELTA_3 * here->BSIM3v32vfbzb);
2155 T2 = DELTA_3 / T0;
2156 }
2157
2158 T1 = 0.5 * (1.0 + V3 / T0);
2159 Vfbeff = here->BSIM3v32vfbzb - 0.5 * (V3 + T0);
2160 dVfbeff_dVg = T1 * dVgs_eff_dVg;
2161 dVfbeff_dVb = -T1 * dVbseffCV_dVb;
2162
2163 Cox = model->BSIM3v32cox;
2164 Tox = 1.0e8 * model->BSIM3v32tox;
2165 T0 = (Vgs_eff - VbseffCV - here->BSIM3v32vfbzb) / Tox;
2166 dT0_dVg = dVgs_eff_dVg / Tox;
2167 dT0_dVb = -dVbseffCV_dVb / Tox;
2168
2169 tmp = T0 * pParam->BSIM3v32acde;
2170 if ((-EXP_THRESHOLD < tmp) && (tmp < EXP_THRESHOLD))
2171 { Tcen = pParam->BSIM3v32ldeb * exp(tmp);
2172 dTcen_dVg = pParam->BSIM3v32acde * Tcen;
2173 dTcen_dVb = dTcen_dVg * dT0_dVb;
2174 dTcen_dVg *= dT0_dVg;
2175 }
2176 else if (tmp <= -EXP_THRESHOLD)
2177 { Tcen = pParam->BSIM3v32ldeb * MIN_EXP;
2178 dTcen_dVg = dTcen_dVb = 0.0;
2179 }
2180 else
2181 { Tcen = pParam->BSIM3v32ldeb * MAX_EXP;
2182 dTcen_dVg = dTcen_dVb = 0.0;
2183 }
2184
2185 LINK = 1.0e-3 * model->BSIM3v32tox;
2186 V3 = pParam->BSIM3v32ldeb - Tcen - LINK;
2187 V4 = sqrt(V3 * V3 + 4.0 * LINK * pParam->BSIM3v32ldeb);
2188 Tcen = pParam->BSIM3v32ldeb - 0.5 * (V3 + V4);
2189 T1 = 0.5 * (1.0 + V3 / V4);
2190 dTcen_dVg *= T1;
2191 dTcen_dVb *= T1;
2192
2193 Ccen = EPSSI / Tcen;
2194 T2 = Cox / (Cox + Ccen);
2195 Coxeff = T2 * Ccen;
2196 T3 = -Ccen / Tcen;
2197 dCoxeff_dVg = T2 * T2 * T3;
2198 dCoxeff_dVb = dCoxeff_dVg * dTcen_dVb;
2199 dCoxeff_dVg *= dTcen_dVg;
2200 CoxWLcen = CoxWL * Coxeff / Cox;
2201
2202 Qac0 = CoxWLcen * (Vfbeff - here->BSIM3v32vfbzb);
2203 QovCox = Qac0 / Coxeff;
2204 dQac0_dVg = CoxWLcen * dVfbeff_dVg
2205 + QovCox * dCoxeff_dVg;
2206 dQac0_dVb = CoxWLcen * dVfbeff_dVb
2207 + QovCox * dCoxeff_dVb;
2208
2209 T0 = 0.5 * pParam->BSIM3v32k1ox;
2210 T3 = Vgs_eff - Vfbeff - VbseffCV - Vgsteff;
2211 if (pParam->BSIM3v32k1ox == 0.0)
2212 { T1 = 0.0;
2213 T2 = 0.0;
2214 }
2215 else if (T3 < 0.0)
2216 { T1 = T0 + T3 / pParam->BSIM3v32k1ox;
2217 T2 = CoxWLcen;
2218 }
2219 else
2220 { T1 = sqrt(T0 * T0 + T3);
2221 T2 = CoxWLcen * T0 / T1;
2222 }
2223
2224 Qsub0 = CoxWLcen * pParam->BSIM3v32k1ox * (T1 - T0);
2225 QovCox = Qsub0 / Coxeff;
2226 dQsub0_dVg = T2 * (dVgs_eff_dVg - dVfbeff_dVg - dVgsteff_dVg)
2227 + QovCox * dCoxeff_dVg;
2228 dQsub0_dVd = -T2 * dVgsteff_dVd;
2229 dQsub0_dVb = -T2 * (dVfbeff_dVb + dVbseffCV_dVb + dVgsteff_dVb)
2230 + QovCox * dCoxeff_dVb;
2231
2232 /* Gate-bias dependent delta Phis begins */
2233 if (pParam->BSIM3v32k1ox <= 0.0)
2234 { Denomi = 0.25 * pParam->BSIM3v32moin * Vtm;
2235 T0 = 0.5 * pParam->BSIM3v32sqrtPhi;
2236 }
2237 else
2238 { Denomi = pParam->BSIM3v32moin * Vtm
2239 * pParam->BSIM3v32k1ox * pParam->BSIM3v32k1ox;
2240 T0 = pParam->BSIM3v32k1ox * pParam->BSIM3v32sqrtPhi;
2241 }
2242 T1 = 2.0 * T0 + Vgsteff;
2243
2244 DeltaPhi = Vtm * log(1.0 + T1 * Vgsteff / Denomi);
2245 dDeltaPhi_dVg = 2.0 * Vtm * (T1 -T0) / (Denomi + T1 * Vgsteff);
2246 dDeltaPhi_dVd = dDeltaPhi_dVg * dVgsteff_dVd;
2247 dDeltaPhi_dVb = dDeltaPhi_dVg * dVgsteff_dVb;
2248 /* End of delta Phis */
2249
2250 T3 = 4.0 * (Vth - here->BSIM3v32vfbzb - pParam->BSIM3v32phi);
2251 Tox += Tox;
2252 if (T3 >= 0.0)
2253 {
2254 /* Added revision dependent code */
2255 switch (model->BSIM3v32intVersion) {
2256 case BSIM3v32V324:
2257 case BSIM3v32V323:
2258 case BSIM3v32V322:
2259 T0 = (Vgsteff + T3) / Tox;
2260 dT0_dVd = (dVgsteff_dVd + 4.0 * dVth_dVd) / Tox;
2261 dT0_dVb = (dVgsteff_dVb + 4.0 * dVth_dVb) / Tox;
2262 break;
2263 case BSIM3v32V32:
2264 default:
2265 T0 = (Vgsteff + T3) / Tox;
2266 }
2267 }
2268 else
2269 {
2270 /* Added revision dependent code */
2271 switch (model->BSIM3v32intVersion) {
2272 case BSIM3v32V324:
2273 case BSIM3v32V323:
2274 case BSIM3v32V322:
2275 T0 = (Vgsteff + 1.0e-20) / Tox;
2276 dT0_dVd = dVgsteff_dVd / Tox;
2277 dT0_dVb = dVgsteff_dVb / Tox;
2278 break;
2279 case BSIM3v32V32:
2280 default:
2281 T0 = (Vgsteff + 1.0e-20) / Tox;
2282 }
2283 }
2284 tmp = exp(0.7 * log(T0));
2285 T1 = 1.0 + tmp;
2286 T2 = 0.7 * tmp / (T0 * Tox);
2287 Tcen = 1.9e-9 / T1;
2288 dTcen_dVg = -1.9e-9 * T2 / T1 /T1;
2289 /* Added revision dependent code */
2290 switch (model->BSIM3v32intVersion) {
2291 case BSIM3v32V324:
2292 case BSIM3v32V323:
2293 case BSIM3v32V322:
2294 dTcen_dVd = Tox * dTcen_dVg;
2295 dTcen_dVb = dTcen_dVd * dT0_dVb;
2296 dTcen_dVd *= dT0_dVd;
2297 break;
2298 case BSIM3v32V32:
2299 default:
2300 dTcen_dVd = dTcen_dVg * (4.0 * dVth_dVd + dVgsteff_dVd);
2301 dTcen_dVb = dTcen_dVg * (4.0 * dVth_dVb + dVgsteff_dVb);
2302 }
2303 dTcen_dVg *= dVgsteff_dVg;
2304
2305 Ccen = EPSSI / Tcen;
2306 T0 = Cox / (Cox + Ccen);
2307 Coxeff = T0 * Ccen;
2308 T1 = -Ccen / Tcen;
2309 dCoxeff_dVg = T0 * T0 * T1;
2310 dCoxeff_dVd = dCoxeff_dVg * dTcen_dVd;
2311 dCoxeff_dVb = dCoxeff_dVg * dTcen_dVb;
2312 dCoxeff_dVg *= dTcen_dVg;
2313 CoxWLcen = CoxWL * Coxeff / Cox;
2314
2315 AbulkCV = Abulk0 * pParam->BSIM3v32abulkCVfactor;
2316 dAbulkCV_dVb = pParam->BSIM3v32abulkCVfactor * dAbulk0_dVb;
2317 VdsatCV = (Vgsteff - DeltaPhi) / AbulkCV;
2318 V4 = VdsatCV - Vds - DELTA_4;
2319 T0 = sqrt(V4 * V4 + 4.0 * DELTA_4 * VdsatCV);
2320 VdseffCV = VdsatCV - 0.5 * (V4 + T0);
2321 T1 = 0.5 * (1.0 + V4 / T0);
2322 T2 = DELTA_4 / T0;
2323 T3 = (1.0 - T1 - T2) / AbulkCV;
2324 T4 = T3 * ( 1.0 - dDeltaPhi_dVg);
2325 dVdseffCV_dVg = T4;
2326 dVdseffCV_dVd = T1;
2327 dVdseffCV_dVb = -T3 * VdsatCV * dAbulkCV_dVb;
2328 /* Added revision dependent code */
2329 switch (model->BSIM3v32intVersion) {
2330 case BSIM3v32V324:
2331 case BSIM3v32V323:
2332 case BSIM3v32V322:
2333 /* Added to eliminate non-zero VdseffCV at Vds=0.0 */
2334 if (Vds == 0.0)
2335 {
2336 VdseffCV = 0.0;
2337 dVdseffCV_dVg = 0.0;
2338 dVdseffCV_dVb = 0.0;
2339 }
2340 break;
2341 case BSIM3v32V32:
2342 default:
2343 /* Do nothing */
2344 break;
2345 }
2346
2347 T0 = AbulkCV * VdseffCV;
2348 T1 = Vgsteff - DeltaPhi;
2349 T2 = 12.0 * (T1 - 0.5 * T0 + 1.0e-20);
2350 T3 = T0 / T2;
2351 T4 = 1.0 - 12.0 * T3 * T3;
2352 T5 = AbulkCV * (6.0 * T0 * (4.0 * T1 - T0) / (T2 * T2) - 0.5);
2353 T6 = T5 * VdseffCV / AbulkCV;
2354
2355 qgate = qinoi = CoxWLcen * (T1 - T0 * (0.5 - T3));
2356 QovCox = qgate / Coxeff;
2357 Cgg1 = CoxWLcen * (T4 * (1.0 - dDeltaPhi_dVg)
2358 + T5 * dVdseffCV_dVg);
2359 Cgd1 = CoxWLcen * T5 * dVdseffCV_dVd + Cgg1
2360 * dVgsteff_dVd + QovCox * dCoxeff_dVd;
2361 Cgb1 = CoxWLcen * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2362 + Cgg1 * dVgsteff_dVb + QovCox * dCoxeff_dVb;
2363 Cgg1 = Cgg1 * dVgsteff_dVg + QovCox * dCoxeff_dVg;
2364
2365
2366 T7 = 1.0 - AbulkCV;
2367 T8 = T2 * T2;
2368 T9 = 12.0 * T7 * T0 * T0 / (T8 * AbulkCV);
2369 T10 = T9 * (1.0 - dDeltaPhi_dVg);
2370 T11 = -T7 * T5 / AbulkCV;
2371 T12 = -(T9 * T1 / AbulkCV + VdseffCV * (0.5 - T0 / T2));
2372
2373 qbulk = CoxWLcen * T7 * (0.5 * VdseffCV - T0 * VdseffCV / T2);
2374 QovCox = qbulk / Coxeff;
2375 Cbg1 = CoxWLcen * (T10 + T11 * dVdseffCV_dVg);
2376 Cbd1 = CoxWLcen * T11 * dVdseffCV_dVd + Cbg1
2377 * dVgsteff_dVd + QovCox * dCoxeff_dVd;
2378 Cbb1 = CoxWLcen * (T11 * dVdseffCV_dVb + T12 * dAbulkCV_dVb)
2379 + Cbg1 * dVgsteff_dVb + QovCox * dCoxeff_dVb;
2380 Cbg1 = Cbg1 * dVgsteff_dVg + QovCox * dCoxeff_dVg;
2381
2382 if (model->BSIM3v32xpart > 0.5)
2383 { /* 0/100 partition */
2384 qsrc = -CoxWLcen * (T1 / 2.0 + T0 / 4.0
2385 - 0.5 * T0 * T0 / T2);
2386 QovCox = qsrc / Coxeff;
2387 T2 += T2;
2388 T3 = T2 * T2;
2389 T7 = -(0.25 - 12.0 * T0 * (4.0 * T1 - T0) / T3);
2390 T4 = -(0.5 + 24.0 * T0 * T0 / T3) * (1.0 - dDeltaPhi_dVg);
2391 T5 = T7 * AbulkCV;
2392 T6 = T7 * VdseffCV;
2393
2394 Csg = CoxWLcen * (T4 + T5 * dVdseffCV_dVg);
2395 Csd = CoxWLcen * T5 * dVdseffCV_dVd + Csg * dVgsteff_dVd
2396 + QovCox * dCoxeff_dVd;
2397 Csb = CoxWLcen * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb)
2398 + Csg * dVgsteff_dVb + QovCox * dCoxeff_dVb;
2399 Csg = Csg * dVgsteff_dVg + QovCox * dCoxeff_dVg;
2400 }
2401 else if (model->BSIM3v32xpart < 0.5)
2402 { /* 40/60 partition */
2403 T2 = T2 / 12.0;
2404 T3 = 0.5 * CoxWLcen / (T2 * T2);
2405 T4 = T1 * (2.0 * T0 * T0 / 3.0 + T1 * (T1 - 4.0
2406 * T0 / 3.0)) - 2.0 * T0 * T0 * T0 / 15.0;
2407 qsrc = -T3 * T4;
2408 QovCox = qsrc / Coxeff;
2409 T8 = 4.0 / 3.0 * T1 * (T1 - T0) + 0.4 * T0 * T0;
2410 T5 = -2.0 * qsrc / T2 - T3 * (T1 * (3.0 * T1 - 8.0
2411 * T0 / 3.0) + 2.0 * T0 * T0 / 3.0);
2412 T6 = AbulkCV * (qsrc / T2 + T3 * T8);
2413 T7 = T6 * VdseffCV / AbulkCV;
2414
2415 Csg = T5 * (1.0 - dDeltaPhi_dVg) + T6 * dVdseffCV_dVg;
2416 Csd = Csg * dVgsteff_dVd + T6 * dVdseffCV_dVd
2417 + QovCox * dCoxeff_dVd;
2418 Csb = Csg * dVgsteff_dVb + T6 * dVdseffCV_dVb
2419 + T7 * dAbulkCV_dVb + QovCox * dCoxeff_dVb;
2420 Csg = Csg * dVgsteff_dVg + QovCox * dCoxeff_dVg;
2421 }
2422 else
2423 { /* 50/50 partition */
2424 qsrc = -0.5 * qgate;
2425 Csg = -0.5 * Cgg1;
2426 Csd = -0.5 * Cgd1;
2427 Csb = -0.5 * Cgb1;
2428 }
2429
2430 qgate += Qac0 + Qsub0 - qbulk;
2431 qbulk -= (Qac0 + Qsub0);
2432 qdrn = -(qgate + qbulk + qsrc);
2433
2434 Cbg = Cbg1 - dQac0_dVg - dQsub0_dVg;
2435 Cbd = Cbd1 - dQsub0_dVd;
2436 Cbb = Cbb1 - dQac0_dVb - dQsub0_dVb;
2437
2438 Cgg = Cgg1 - Cbg;
2439 Cgd = Cgd1 - Cbd;
2440 Cgb = Cgb1 - Cbb;
2441
2442 Cgb *= dVbseff_dVb;
2443 Cbb *= dVbseff_dVb;
2444 Csb *= dVbseff_dVb;
2445
2446 here->BSIM3v32cggb = Cgg;
2447 here->BSIM3v32cgsb = -(Cgg + Cgd + Cgb);
2448 here->BSIM3v32cgdb = Cgd;
2449 here->BSIM3v32cdgb = -(Cgg + Cbg + Csg);
2450 here->BSIM3v32cdsb = (Cgg + Cgd + Cgb + Cbg + Cbd + Cbb
2451 + Csg + Csd + Csb);
2452 here->BSIM3v32cddb = -(Cgd + Cbd + Csd);
2453 here->BSIM3v32cbgb = Cbg;
2454 here->BSIM3v32cbsb = -(Cbg + Cbd + Cbb);
2455 here->BSIM3v32cbdb = Cbd;
2456 here->BSIM3v32qinv = -qinoi;
2457 } /* End of CTM */
2458 }
2459
2460 finished:
2461 /* Returning Values to Calling Routine */
2462 /*
2463 * COMPUTE EQUIVALENT DRAIN CURRENT SOURCE
2464 */
2465
2466 here->BSIM3v32qgate = qgate;
2467 here->BSIM3v32qbulk = qbulk;
2468 here->BSIM3v32qdrn = qdrn;
2469 here->BSIM3v32cd = cdrain;
2470
2471 if (ChargeComputationNeeded)
2472 { /* charge storage elements
2473 * bulk-drain and bulk-source depletion capacitances
2474 * czbd : zero bias drain junction capacitance
2475 * czbs : zero bias source junction capacitance
2476 * czbdsw: zero bias drain junction sidewall capacitance
2477 along field oxide
2478 * czbssw: zero bias source junction sidewall capacitance
2479 along field oxide
2480 * czbdswg: zero bias drain junction sidewall capacitance
2481 along gate side
2482 * czbsswg: zero bias source junction sidewall capacitance
2483 along gate side
2484 */
2485
2486 if (model->BSIM3v32acmMod == 0)
2487 {
2488 /* Added revision dependent code */
2489 switch (model->BSIM3v32intVersion) {
2490 case BSIM3v32V324:
2491 case BSIM3v32V323:
2492 czbd = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32drainArea; /*bug fix */
2493 czbs = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32sourceArea;
2494 break;
2495 case BSIM3v32V322:
2496 case BSIM3v32V32:
2497 default:
2498 czbd = model->BSIM3v32unitAreaJctCap * here->BSIM3v32drainArea;
2499 czbs = model->BSIM3v32unitAreaJctCap * here->BSIM3v32sourceArea;
2500 }
2501
2502 if (here->BSIM3v32drainPerimeter < pParam->BSIM3v32weff)
2503 {
2504 czbdsw = 0.0;
2505 /* Added revision dependent code */
2506 switch (model->BSIM3v32intVersion) {
2507 case BSIM3v32V324:
2508 case BSIM3v32V323:
2509 czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
2510 * here->BSIM3v32drainPerimeter;
2511 break;
2512 case BSIM3v32V322:
2513 case BSIM3v32V32:
2514 default:
2515 czbdswg = model->BSIM3v32unitLengthGateSidewallJctCap
2516 * here->BSIM3v32drainPerimeter;
2517 }
2518 }
2519 else
2520 {
2521 /* Added revision dependent code */
2522 switch (model->BSIM3v32intVersion) {
2523 case BSIM3v32V324:
2524 case BSIM3v32V323:
2525 czbdsw = model->BSIM3v32unitLengthSidewallTempJctCap
2526 * (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
2527 czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
2528 * pParam->BSIM3v32weff;
2529 break;
2530 case BSIM3v32V322:
2531 case BSIM3v32V32:
2532 default:
2533 czbdsw = model->BSIM3v32unitLengthSidewallJctCap
2534 * (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
2535 czbdswg = model->BSIM3v32unitLengthGateSidewallJctCap
2536 * pParam->BSIM3v32weff;
2537 }
2538 }
2539 if (here->BSIM3v32sourcePerimeter < pParam->BSIM3v32weff)
2540 {
2541 czbssw = 0.0;
2542 /* Added revision dependent code */
2543 switch (model->BSIM3v32intVersion) {
2544 case BSIM3v32V324:
2545 case BSIM3v32V323:
2546 czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
2547 * here->BSIM3v32sourcePerimeter;
2548 break;
2549 case BSIM3v32V322:
2550 case BSIM3v32V32:
2551 default:
2552 czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
2553 * here->BSIM3v32sourcePerimeter;
2554 }
2555 }
2556 else
2557 {
2558 /* Added revision dependent code */
2559 switch (model->BSIM3v32intVersion) {
2560 case BSIM3v32V324:
2561 case BSIM3v32V323:
2562 czbssw = model->BSIM3v32unitLengthSidewallTempJctCap
2563 * (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
2564 czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
2565 * pParam->BSIM3v32weff;
2566 break;
2567 case BSIM3v32V322:
2568 case BSIM3v32V32:
2569 default:
2570 czbssw = model->BSIM3v32unitLengthSidewallJctCap
2571 * (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
2572 czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
2573 * pParam->BSIM3v32weff;
2574 }
2575 }
2576
2577 } else {
2578 /* Added revision dependent code */
2579 switch (model->BSIM3v32intVersion) {
2580 case BSIM3v32V324:
2581 case BSIM3v32V323:
2582 error = ACM_junctionCapacitances(
2583 model->BSIM3v32acmMod,
2584 model->BSIM3v32calcacm,
2585 here->BSIM3v32geo,
2586 model->BSIM3v32hdif,
2587 model->BSIM3v32wmlt,
2588 here->BSIM3v32w,
2589 model->BSIM3v32xw,
2590 here->BSIM3v32drainAreaGiven,
2591 here->BSIM3v32drainArea,
2592 here->BSIM3v32drainPerimeterGiven,
2593 here->BSIM3v32drainPerimeter,
2594 here->BSIM3v32sourceAreaGiven,
2595 here->BSIM3v32sourceArea,
2596 here->BSIM3v32sourcePerimeterGiven,
2597 here->BSIM3v32sourcePerimeter,
2598 model->BSIM3v32unitAreaTempJctCap,
2599 model->BSIM3v32unitLengthSidewallTempJctCap,
2600 model->BSIM3v32unitLengthGateSidewallTempJctCap,
2601 &czbd,
2602 &czbdsw,
2603 &czbdswg,
2604 &czbs,
2605 &czbssw,
2606 &czbsswg
2607 );
2608 break;
2609 case BSIM3v32V322:
2610 case BSIM3v32V32:
2611 default:
2612 error = ACM_junctionCapacitances(
2613 model->BSIM3v32acmMod,
2614 model->BSIM3v32calcacm,
2615 here->BSIM3v32geo,
2616 model->BSIM3v32hdif,
2617 model->BSIM3v32wmlt,
2618 here->BSIM3v32w,
2619 model->BSIM3v32xw,
2620 here->BSIM3v32drainAreaGiven,
2621 here->BSIM3v32drainArea,
2622 here->BSIM3v32drainPerimeterGiven,
2623 here->BSIM3v32drainPerimeter,
2624 here->BSIM3v32sourceAreaGiven,
2625 here->BSIM3v32sourceArea,
2626 here->BSIM3v32sourcePerimeterGiven,
2627 here->BSIM3v32sourcePerimeter,
2628 model->BSIM3v32unitAreaJctCap,
2629 model->BSIM3v32unitLengthSidewallJctCap,
2630 model->BSIM3v32unitLengthGateSidewallJctCap,
2631 &czbd,
2632 &czbdsw,
2633 &czbdswg,
2634 &czbs,
2635 &czbssw,
2636 &czbsswg
2637 );
2638 }
2639 if (error)
2640 return(error);
2641 }
2642
2643 MJ = model->BSIM3v32bulkJctBotGradingCoeff;
2644 MJSW = model->BSIM3v32bulkJctSideGradingCoeff;
2645 MJSWG = model->BSIM3v32bulkJctGateSideGradingCoeff;
2646
2647 /* Source Bulk Junction */
2648 if (vbs == 0.0)
2649 { *(ckt->CKTstate0 + here->BSIM3v32qbs) = 0.0;
2650 here->BSIM3v32capbs = czbs + czbssw + czbsswg;
2651 }
2652 else if (vbs < 0.0)
2653 { if (czbs > 0.0)
2654 { arg = 1.0 - vbs / model->BSIM3v32PhiB;
2655 if (MJ == 0.5)
2656 sarg = 1.0 / sqrt(arg);
2657 else
2658 sarg = exp(-MJ * log(arg));
2659 *(ckt->CKTstate0 + here->BSIM3v32qbs) = model->BSIM3v32PhiB * czbs
2660 * (1.0 - arg * sarg) / (1.0 - MJ);
2661 here->BSIM3v32capbs = czbs * sarg;
2662 }
2663 else
2664 { *(ckt->CKTstate0 + here->BSIM3v32qbs) = 0.0;
2665 here->BSIM3v32capbs = 0.0;
2666 }
2667 if (czbssw > 0.0)
2668 { arg = 1.0 - vbs / model->BSIM3v32PhiBSW;
2669 if (MJSW == 0.5)
2670 sarg = 1.0 / sqrt(arg);
2671 else
2672 sarg = exp(-MJSW * log(arg));
2673 *(ckt->CKTstate0 + here->BSIM3v32qbs) += model->BSIM3v32PhiBSW * czbssw
2674 * (1.0 - arg * sarg) / (1.0 - MJSW);
2675 here->BSIM3v32capbs += czbssw * sarg;
2676 }
2677 if (czbsswg > 0.0)
2678 { arg = 1.0 - vbs / model->BSIM3v32PhiBSWG;
2679 if (MJSWG == 0.5)
2680 sarg = 1.0 / sqrt(arg);
2681 else
2682 sarg = exp(-MJSWG * log(arg));
2683 *(ckt->CKTstate0 + here->BSIM3v32qbs) += model->BSIM3v32PhiBSWG * czbsswg
2684 * (1.0 - arg * sarg) / (1.0 - MJSWG);
2685 here->BSIM3v32capbs += czbsswg * sarg;
2686 }
2687
2688 }
2689 else
2690 { T0 = czbs + czbssw + czbsswg;
2691 T1 = vbs * (czbs * MJ / model->BSIM3v32PhiB + czbssw * MJSW
2692 / model->BSIM3v32PhiBSW + czbsswg * MJSWG / model->BSIM3v32PhiBSWG);
2693 *(ckt->CKTstate0 + here->BSIM3v32qbs) = vbs * (T0 + 0.5 * T1);
2694 here->BSIM3v32capbs = T0 + T1;
2695 }
2696
2697 /* Drain Bulk Junction */
2698 if (vbd == 0.0)
2699 { *(ckt->CKTstate0 + here->BSIM3v32qbd) = 0.0;
2700 here->BSIM3v32capbd = czbd + czbdsw + czbdswg;
2701 }
2702 else if (vbd < 0.0)
2703 { if (czbd > 0.0)
2704 { arg = 1.0 - vbd / model->BSIM3v32PhiB;
2705 if (MJ == 0.5)
2706 sarg = 1.0 / sqrt(arg);
2707 else
2708 sarg = exp(-MJ * log(arg));
2709 *(ckt->CKTstate0 + here->BSIM3v32qbd) = model->BSIM3v32PhiB * czbd
2710 * (1.0 - arg * sarg) / (1.0 - MJ);
2711 here->BSIM3v32capbd = czbd * sarg;
2712 }
2713 else
2714 { *(ckt->CKTstate0 + here->BSIM3v32qbd) = 0.0;
2715 here->BSIM3v32capbd = 0.0;
2716 }
2717 if (czbdsw > 0.0)
2718 { arg = 1.0 - vbd / model->BSIM3v32PhiBSW;
2719 if (MJSW == 0.5)
2720 sarg = 1.0 / sqrt(arg);
2721 else
2722 sarg = exp(-MJSW * log(arg));
2723 *(ckt->CKTstate0 + here->BSIM3v32qbd) += model->BSIM3v32PhiBSW * czbdsw
2724 * (1.0 - arg * sarg) / (1.0 - MJSW);
2725 here->BSIM3v32capbd += czbdsw * sarg;
2726 }
2727 if (czbdswg > 0.0)
2728 { arg = 1.0 - vbd / model->BSIM3v32PhiBSWG;
2729 if (MJSWG == 0.5)
2730 sarg = 1.0 / sqrt(arg);
2731 else
2732 sarg = exp(-MJSWG * log(arg));
2733 *(ckt->CKTstate0 + here->BSIM3v32qbd) += model->BSIM3v32PhiBSWG * czbdswg
2734 * (1.0 - arg * sarg) / (1.0 - MJSWG);
2735 here->BSIM3v32capbd += czbdswg * sarg;
2736 }
2737 }
2738 else
2739 { T0 = czbd + czbdsw + czbdswg;
2740 T1 = vbd * (czbd * MJ / model->BSIM3v32PhiB + czbdsw * MJSW
2741 / model->BSIM3v32PhiBSW + czbdswg * MJSWG / model->BSIM3v32PhiBSWG);
2742 *(ckt->CKTstate0 + here->BSIM3v32qbd) = vbd * (T0 + 0.5 * T1);
2743 here->BSIM3v32capbd = T0 + T1;
2744 }
2745 }
2746
2747 /*
2748 * check convergence
2749 */
2750 if ((here->BSIM3v32off == 0) || (!(ckt->CKTmode & MODEINITFIX)))
2751 { if (Check == 1)
2752 { ckt->CKTnoncon++;
2753 #ifndef NEWCONV
2754 }
2755 else
2756 { if (here->BSIM3v32mode >= 0)
2757 { Idtot = here->BSIM3v32cd + here->BSIM3v32csub - here->BSIM3v32cbd;
2758 }
2759 else
2760 { Idtot = here->BSIM3v32cd - here->BSIM3v32cbd;
2761 }
2762 tol = ckt->CKTreltol * MAX(fabs(cdhat), fabs(Idtot))
2763 + ckt->CKTabstol;
2764 if (fabs(cdhat - Idtot) >= tol)
2765 { ckt->CKTnoncon++;
2766 }
2767 else
2768 { Ibtot = here->BSIM3v32cbs + here->BSIM3v32cbd - here->BSIM3v32csub;
2769 tol = ckt->CKTreltol * MAX(fabs(cbhat), fabs(Ibtot))
2770 + ckt->CKTabstol;
2771 if (fabs(cbhat - Ibtot) > tol)
2772 { ckt->CKTnoncon++;
2773 }
2774 }
2775 #endif /* NEWCONV */
2776 }
2777 }
2778 *(ckt->CKTstate0 + here->BSIM3v32vbs) = vbs;
2779 *(ckt->CKTstate0 + here->BSIM3v32vbd) = vbd;
2780 *(ckt->CKTstate0 + here->BSIM3v32vgs) = vgs;
2781 *(ckt->CKTstate0 + here->BSIM3v32vds) = vds;
2782 *(ckt->CKTstate0 + here->BSIM3v32qdef) = qdef;
2783
2784 /* bulk and channel charge plus overlaps */
2785
2786 if (!ChargeComputationNeeded)
2787 goto line850;
2788
2789 #ifndef NOBYPASS
2790 line755:
2791 #endif
2792 /* NQS begins */
2793 if (here->BSIM3v32nqsMod)
2794 { qcheq = -(qbulk + qgate);
2795
2796 here->BSIM3v32cqgb = -(here->BSIM3v32cggb + here->BSIM3v32cbgb);
2797 here->BSIM3v32cqdb = -(here->BSIM3v32cgdb + here->BSIM3v32cbdb);
2798 here->BSIM3v32cqsb = -(here->BSIM3v32cgsb + here->BSIM3v32cbsb);
2799 here->BSIM3v32cqbb = -(here->BSIM3v32cqgb + here->BSIM3v32cqdb
2800 + here->BSIM3v32cqsb);
2801
2802 gtau_drift = fabs(here->BSIM3v32tconst * qcheq) * ScalingFactor;
2803 T0 = pParam->BSIM3v32leffCV * pParam->BSIM3v32leffCV;
2804 gtau_diff = 16.0 * here->BSIM3v32u0temp * model->BSIM3v32vtm / T0
2805 * ScalingFactor;
2806 here->BSIM3v32gtau = gtau_drift + gtau_diff;
2807 }
2808
2809 if (model->BSIM3v32capMod == 0)
2810 {
2811 /* code merge -JX */
2812 cgdo = pParam->BSIM3v32cgdo;
2813 qgdo = pParam->BSIM3v32cgdo * vgd;
2814 cgso = pParam->BSIM3v32cgso;
2815 qgso = pParam->BSIM3v32cgso * vgs;
2816 }
2817 else if (model->BSIM3v32capMod == 1)
2818 { if (vgd < 0.0)
2819 { T1 = sqrt(1.0 - 4.0 * vgd / pParam->BSIM3v32ckappa);
2820 cgdo = pParam->BSIM3v32cgdo + pParam->BSIM3v32weffCV
2821 * pParam->BSIM3v32cgdl / T1;
2822 qgdo = pParam->BSIM3v32cgdo * vgd - pParam->BSIM3v32weffCV * 0.5
2823 * pParam->BSIM3v32cgdl * pParam->BSIM3v32ckappa * (T1 - 1.0);
2824 }
2825 else
2826 { cgdo = pParam->BSIM3v32cgdo + pParam->BSIM3v32weffCV
2827 * pParam->BSIM3v32cgdl;
2828 qgdo = (pParam->BSIM3v32weffCV * pParam->BSIM3v32cgdl
2829 + pParam->BSIM3v32cgdo) * vgd;
2830 }
2831
2832 if (vgs < 0.0)
2833 { T1 = sqrt(1.0 - 4.0 * vgs / pParam->BSIM3v32ckappa);
2834 cgso = pParam->BSIM3v32cgso + pParam->BSIM3v32weffCV
2835 * pParam->BSIM3v32cgsl / T1;
2836 qgso = pParam->BSIM3v32cgso * vgs - pParam->BSIM3v32weffCV * 0.5
2837 * pParam->BSIM3v32cgsl * pParam->BSIM3v32ckappa * (T1 - 1.0);
2838 }
2839 else
2840 { cgso = pParam->BSIM3v32cgso + pParam->BSIM3v32weffCV
2841 * pParam->BSIM3v32cgsl;
2842 qgso = (pParam->BSIM3v32weffCV * pParam->BSIM3v32cgsl
2843 + pParam->BSIM3v32cgso) * vgs;
2844 }
2845 }
2846 else
2847 { T0 = vgd + DELTA_1;
2848 T1 = sqrt(T0 * T0 + 4.0 * DELTA_1);
2849 T2 = 0.5 * (T0 - T1);
2850
2851 T3 = pParam->BSIM3v32weffCV * pParam->BSIM3v32cgdl;
2852 T4 = sqrt(1.0 - 4.0 * T2 / pParam->BSIM3v32ckappa);
2853 cgdo = pParam->BSIM3v32cgdo + T3 - T3 * (1.0 - 1.0 / T4)
2854 * (0.5 - 0.5 * T0 / T1);
2855 qgdo = (pParam->BSIM3v32cgdo + T3) * vgd - T3 * (T2
2856 + 0.5 * pParam->BSIM3v32ckappa * (T4 - 1.0));
2857
2858 T0 = vgs + DELTA_1;
2859 T1 = sqrt(T0 * T0 + 4.0 * DELTA_1);
2860 T2 = 0.5 * (T0 - T1);
2861 T3 = pParam->BSIM3v32weffCV * pParam->BSIM3v32cgsl;
2862 T4 = sqrt(1.0 - 4.0 * T2 / pParam->BSIM3v32ckappa);
2863 cgso = pParam->BSIM3v32cgso + T3 - T3 * (1.0 - 1.0 / T4)
2864 * (0.5 - 0.5 * T0 / T1);
2865 qgso = (pParam->BSIM3v32cgso + T3) * vgs - T3 * (T2
2866 + 0.5 * pParam->BSIM3v32ckappa * (T4 - 1.0));
2867 }
2868
2869 here->BSIM3v32cgdo = cgdo;
2870 here->BSIM3v32cgso = cgso;
2871
2872 ag0 = ckt->CKTag[0];
2873 if (here->BSIM3v32mode > 0)
2874 { if (here->BSIM3v32nqsMod == 0)
2875 { gcggb = (here->BSIM3v32cggb + cgdo + cgso
2876 + pParam->BSIM3v32cgbo ) * ag0;
2877 gcgdb = (here->BSIM3v32cgdb - cgdo) * ag0;
2878 gcgsb = (here->BSIM3v32cgsb - cgso) * ag0;
2879
2880 gcdgb = (here->BSIM3v32cdgb - cgdo) * ag0;
2881 gcddb = (here->BSIM3v32cddb + here->BSIM3v32capbd + cgdo) * ag0;
2882 gcdsb = here->BSIM3v32cdsb * ag0;
2883
2884 gcsgb = -(here->BSIM3v32cggb + here->BSIM3v32cbgb
2885 + here->BSIM3v32cdgb + cgso) * ag0;
2886 gcsdb = -(here->BSIM3v32cgdb + here->BSIM3v32cbdb
2887 + here->BSIM3v32cddb) * ag0;
2888 gcssb = (here->BSIM3v32capbs + cgso - (here->BSIM3v32cgsb
2889 + here->BSIM3v32cbsb + here->BSIM3v32cdsb)) * ag0;
2890
2891 gcbgb = (here->BSIM3v32cbgb - pParam->BSIM3v32cgbo) * ag0;
2892 gcbdb = (here->BSIM3v32cbdb - here->BSIM3v32capbd) * ag0;
2893 gcbsb = (here->BSIM3v32cbsb - here->BSIM3v32capbs) * ag0;
2894
2895 qgd = qgdo;
2896 qgs = qgso;
2897 qgb = pParam->BSIM3v32cgbo * vgb;
2898 qgate += qgd + qgs + qgb;
2899 qbulk -= qgb;
2900 qdrn -= qgd;
2901 qsrc = -(qgate + qbulk + qdrn);
2902
2903 ggtg = ggtd = ggtb = ggts = 0.0;
2904 sxpart = 0.6;
2905 dxpart = 0.4;
2906 ddxpart_dVd = ddxpart_dVg = ddxpart_dVb = ddxpart_dVs = 0.0;
2907 dsxpart_dVd = dsxpart_dVg = dsxpart_dVb = dsxpart_dVs = 0.0;
2908 }
2909 else
2910 { if (qcheq > 0.0)
2911 T0 = here->BSIM3v32tconst * qdef * ScalingFactor;
2912 else
2913 T0 = -here->BSIM3v32tconst * qdef * ScalingFactor;
2914 ggtg = here->BSIM3v32gtg = T0 * here->BSIM3v32cqgb;
2915 ggtd = here->BSIM3v32gtd = T0 * here->BSIM3v32cqdb;
2916 ggts = here->BSIM3v32gts = T0 * here->BSIM3v32cqsb;
2917 ggtb = here->BSIM3v32gtb = T0 * here->BSIM3v32cqbb;
2918 gqdef = ScalingFactor * ag0;
2919
2920 gcqgb = here->BSIM3v32cqgb * ag0;
2921 gcqdb = here->BSIM3v32cqdb * ag0;
2922 gcqsb = here->BSIM3v32cqsb * ag0;
2923 gcqbb = here->BSIM3v32cqbb * ag0;
2924
2925 gcggb = (cgdo + cgso + pParam->BSIM3v32cgbo ) * ag0;
2926 gcgdb = -cgdo * ag0;
2927 gcgsb = -cgso * ag0;
2928
2929 gcdgb = -cgdo * ag0;
2930 gcddb = (here->BSIM3v32capbd + cgdo) * ag0;
2931 gcdsb = 0.0;
2932
2933 gcsgb = -cgso * ag0;
2934 gcsdb = 0.0;
2935 gcssb = (here->BSIM3v32capbs + cgso) * ag0;
2936
2937 gcbgb = -pParam->BSIM3v32cgbo * ag0;
2938 gcbdb = -here->BSIM3v32capbd * ag0;
2939 gcbsb = -here->BSIM3v32capbs * ag0;
2940
2941 CoxWL = model->BSIM3v32cox * pParam->BSIM3v32weffCV
2942 * pParam->BSIM3v32leffCV;
2943 if (fabs(qcheq) <= 1.0e-5 * CoxWL)
2944 { if (model->BSIM3v32xpart < 0.5)
2945 { dxpart = 0.4;
2946 }
2947 else if (model->BSIM3v32xpart > 0.5)
2948 { dxpart = 0.0;
2949 }
2950 else
2951 { dxpart = 0.5;
2952 }
2953 ddxpart_dVd = ddxpart_dVg = ddxpart_dVb
2954 = ddxpart_dVs = 0.0;
2955 }
2956 else
2957 { dxpart = qdrn / qcheq;
2958 Cdd = here->BSIM3v32cddb;
2959 Csd = -(here->BSIM3v32cgdb + here->BSIM3v32cddb
2960 + here->BSIM3v32cbdb);
2961 ddxpart_dVd = (Cdd - dxpart * (Cdd + Csd)) / qcheq;
2962 Cdg = here->BSIM3v32cdgb;
2963 Csg = -(here->BSIM3v32cggb + here->BSIM3v32cdgb
2964 + here->BSIM3v32cbgb);
2965 ddxpart_dVg = (Cdg - dxpart * (Cdg + Csg)) / qcheq;
2966
2967 Cds = here->BSIM3v32cdsb;
2968 Css = -(here->BSIM3v32cgsb + here->BSIM3v32cdsb
2969 + here->BSIM3v32cbsb);
2970 ddxpart_dVs = (Cds - dxpart * (Cds + Css)) / qcheq;
2971
2972 ddxpart_dVb = -(ddxpart_dVd + ddxpart_dVg + ddxpart_dVs);
2973 }
2974 sxpart = 1.0 - dxpart;
2975 dsxpart_dVd = -ddxpart_dVd;
2976 dsxpart_dVg = -ddxpart_dVg;
2977 dsxpart_dVs = -ddxpart_dVs;
2978 dsxpart_dVb = -(dsxpart_dVd + dsxpart_dVg + dsxpart_dVs);
2979
2980 qgd = qgdo;
2981 qgs = qgso;
2982 qgb = pParam->BSIM3v32cgbo * vgb;
2983 qgate = qgd + qgs + qgb;
2984 qbulk = -qgb;
2985 qdrn = -qgd;
2986 qsrc = -(qgate + qbulk + qdrn);
2987 }
2988 }
2989 else
2990 { if (here->BSIM3v32nqsMod == 0)
2991 { gcggb = (here->BSIM3v32cggb + cgdo + cgso
2992 + pParam->BSIM3v32cgbo ) * ag0;
2993 gcgdb = (here->BSIM3v32cgsb - cgdo) * ag0;
2994 gcgsb = (here->BSIM3v32cgdb - cgso) * ag0;
2995
2996 gcdgb = -(here->BSIM3v32cggb + here->BSIM3v32cbgb
2997 + here->BSIM3v32cdgb + cgdo) * ag0;
2998 gcddb = (here->BSIM3v32capbd + cgdo - (here->BSIM3v32cgsb
2999 + here->BSIM3v32cbsb + here->BSIM3v32cdsb)) * ag0;
3000 gcdsb = -(here->BSIM3v32cgdb + here->BSIM3v32cbdb
3001 + here->BSIM3v32cddb) * ag0;
3002
3003 gcsgb = (here->BSIM3v32cdgb - cgso) * ag0;
3004 gcsdb = here->BSIM3v32cdsb * ag0;
3005 gcssb = (here->BSIM3v32cddb + here->BSIM3v32capbs + cgso) * ag0;
3006
3007 gcbgb = (here->BSIM3v32cbgb - pParam->BSIM3v32cgbo) * ag0;
3008 gcbdb = (here->BSIM3v32cbsb - here->BSIM3v32capbd) * ag0;
3009 gcbsb = (here->BSIM3v32cbdb - here->BSIM3v32capbs) * ag0;
3010
3011 qgd = qgdo;
3012 qgs = qgso;
3013 qgb = pParam->BSIM3v32cgbo * vgb;
3014 qgate += qgd + qgs + qgb;
3015 qbulk -= qgb;
3016 qsrc = qdrn - qgs;
3017 qdrn = -(qgate + qbulk + qsrc);
3018
3019 ggtg = ggtd = ggtb = ggts = 0.0;
3020 sxpart = 0.4;
3021 dxpart = 0.6;
3022 ddxpart_dVd = ddxpart_dVg = ddxpart_dVb = ddxpart_dVs = 0.0;
3023 dsxpart_dVd = dsxpart_dVg = dsxpart_dVb = dsxpart_dVs = 0.0;
3024 }
3025 else
3026 { if (qcheq > 0.0)
3027 T0 = here->BSIM3v32tconst * qdef * ScalingFactor;
3028 else
3029 T0 = -here->BSIM3v32tconst * qdef * ScalingFactor;
3030 ggtg = here->BSIM3v32gtg = T0 * here->BSIM3v32cqgb;
3031 ggts = here->BSIM3v32gtd = T0 * here->BSIM3v32cqdb;
3032 ggtd = here->BSIM3v32gts = T0 * here->BSIM3v32cqsb;
3033 ggtb = here->BSIM3v32gtb = T0 * here->BSIM3v32cqbb;
3034 gqdef = ScalingFactor * ag0;
3035
3036 gcqgb = here->BSIM3v32cqgb * ag0;
3037 gcqdb = here->BSIM3v32cqsb * ag0;
3038 gcqsb = here->BSIM3v32cqdb * ag0;
3039 gcqbb = here->BSIM3v32cqbb * ag0;
3040
3041 gcggb = (cgdo + cgso + pParam->BSIM3v32cgbo) * ag0;
3042 gcgdb = -cgdo * ag0;
3043 gcgsb = -cgso * ag0;
3044
3045 gcdgb = -cgdo * ag0;
3046 gcddb = (here->BSIM3v32capbd + cgdo) * ag0;
3047 gcdsb = 0.0;
3048
3049 gcsgb = -cgso * ag0;
3050 gcsdb = 0.0;
3051 gcssb = (here->BSIM3v32capbs + cgso) * ag0;
3052
3053 gcbgb = -pParam->BSIM3v32cgbo * ag0;
3054 gcbdb = -here->BSIM3v32capbd * ag0;
3055 gcbsb = -here->BSIM3v32capbs * ag0;
3056
3057 CoxWL = model->BSIM3v32cox * pParam->BSIM3v32weffCV
3058 * pParam->BSIM3v32leffCV;
3059 if (fabs(qcheq) <= 1.0e-5 * CoxWL)
3060 { if (model->BSIM3v32xpart < 0.5)
3061 { sxpart = 0.4;
3062 }
3063 else if (model->BSIM3v32xpart > 0.5)
3064 { sxpart = 0.0;
3065 }
3066 else
3067 { sxpart = 0.5;
3068 }
3069 dsxpart_dVd = dsxpart_dVg = dsxpart_dVb
3070 = dsxpart_dVs = 0.0;
3071 }
3072 else
3073 { sxpart = qdrn / qcheq;
3074 Css = here->BSIM3v32cddb;
3075 Cds = -(here->BSIM3v32cgdb + here->BSIM3v32cddb
3076 + here->BSIM3v32cbdb);
3077 dsxpart_dVs = (Css - sxpart * (Css + Cds)) / qcheq;
3078 Csg = here->BSIM3v32cdgb;
3079 Cdg = -(here->BSIM3v32cggb + here->BSIM3v32cdgb
3080 + here->BSIM3v32cbgb);
3081 dsxpart_dVg = (Csg - sxpart * (Csg + Cdg)) / qcheq;
3082
3083 Csd = here->BSIM3v32cdsb;
3084 Cdd = -(here->BSIM3v32cgsb + here->BSIM3v32cdsb
3085 + here->BSIM3v32cbsb);
3086 dsxpart_dVd = (Csd - sxpart * (Csd + Cdd)) / qcheq;
3087
3088 dsxpart_dVb = -(dsxpart_dVd + dsxpart_dVg + dsxpart_dVs);
3089 }
3090 dxpart = 1.0 - sxpart;
3091 ddxpart_dVd = -dsxpart_dVd;
3092 ddxpart_dVg = -dsxpart_dVg;
3093 ddxpart_dVs = -dsxpart_dVs;
3094 ddxpart_dVb = -(ddxpart_dVd + ddxpart_dVg + ddxpart_dVs);
3095
3096 qgd = qgdo;
3097 qgs = qgso;
3098 qgb = pParam->BSIM3v32cgbo * vgb;
3099 qgate = qgd + qgs + qgb;
3100 qbulk = -qgb;
3101 qsrc = -qgs;
3102 qdrn = -(qgate + qbulk + qsrc);
3103 }
3104 }
3105
3106 cqdef = cqcheq = 0.0;
3107 if (ByPass) goto line860;
3108
3109 *(ckt->CKTstate0 + here->BSIM3v32qg) = qgate;
3110 *(ckt->CKTstate0 + here->BSIM3v32qd) = qdrn
3111 - *(ckt->CKTstate0 + here->BSIM3v32qbd);
3112 *(ckt->CKTstate0 + here->BSIM3v32qb) = qbulk
3113 + *(ckt->CKTstate0 + here->BSIM3v32qbd)
3114 + *(ckt->CKTstate0 + here->BSIM3v32qbs);
3115
3116 if (here->BSIM3v32nqsMod)
3117 { *(ckt->CKTstate0 + here->BSIM3v32qcdump) = qdef * ScalingFactor;
3118 *(ckt->CKTstate0 + here->BSIM3v32qcheq) = qcheq;
3119 }
3120
3121 /* store small signal parameters */
3122 if (ckt->CKTmode & MODEINITSMSIG)
3123 { goto line1000;
3124 }
3125 if (!ChargeComputationNeeded)
3126 goto line850;
3127
3128 if (ckt->CKTmode & MODEINITTRAN)
3129 { *(ckt->CKTstate1 + here->BSIM3v32qb) =
3130 *(ckt->CKTstate0 + here->BSIM3v32qb);
3131 *(ckt->CKTstate1 + here->BSIM3v32qg) =
3132 *(ckt->CKTstate0 + here->BSIM3v32qg);
3133 *(ckt->CKTstate1 + here->BSIM3v32qd) =
3134 *(ckt->CKTstate0 + here->BSIM3v32qd);
3135 if (here->BSIM3v32nqsMod)
3136 { *(ckt->CKTstate1 + here->BSIM3v32qcheq) =
3137 *(ckt->CKTstate0 + here->BSIM3v32qcheq);
3138 *(ckt->CKTstate1 + here->BSIM3v32qcdump) =
3139 *(ckt->CKTstate0 + here->BSIM3v32qcdump);
3140 }
3141 }
3142
3143 error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v32qb);
3144 if (error)
3145 return(error);
3146 error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v32qg);
3147 if (error)
3148 return(error);
3149 error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v32qd);
3150 if (error)
3151 return(error);
3152 if (here->BSIM3v32nqsMod)
3153 { error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v32qcdump);
3154 if (error)
3155 return(error);
3156 error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v32qcheq);
3157 if (error)
3158 return(error);
3159 }
3160
3161 goto line860;
3162
3163 line850:
3164 /* initialize to zero charge conductance and current */
3165 ceqqg = ceqqb = ceqqd = 0.0;
3166 cqcheq = cqdef = 0.0;
3167
3168 gcdgb = gcddb = gcdsb = 0.0;
3169 gcsgb = gcsdb = gcssb = 0.0;
3170 gcggb = gcgdb = gcgsb = 0.0;
3171 gcbgb = gcbdb = gcbsb = 0.0;
3172
3173 gqdef = gcqgb = gcqdb = gcqsb = gcqbb = 0.0;
3174 ggtg = ggtd = ggtb = ggts = 0.0;
3175 sxpart = (1.0 - (dxpart = (here->BSIM3v32mode > 0) ? 0.4 : 0.6));
3176 ddxpart_dVd = ddxpart_dVg = ddxpart_dVb = ddxpart_dVs = 0.0;
3177 dsxpart_dVd = dsxpart_dVg = dsxpart_dVb = dsxpart_dVs = 0.0;
3178
3179 if (here->BSIM3v32nqsMod)
3180 here->BSIM3v32gtau = 16.0 * here->BSIM3v32u0temp * model->BSIM3v32vtm
3181 / pParam->BSIM3v32leffCV / pParam->BSIM3v32leffCV
3182 * ScalingFactor;
3183 else
3184 here->BSIM3v32gtau = 0.0;
3185
3186 goto line900;
3187
3188 line860:
3189 /* evaluate equivalent charge current */
3190
3191 cqgate = *(ckt->CKTstate0 + here->BSIM3v32cqg);
3192 cqbulk = *(ckt->CKTstate0 + here->BSIM3v32cqb);
3193 cqdrn = *(ckt->CKTstate0 + here->BSIM3v32cqd);
3194
3195 ceqqg = cqgate - gcggb * vgb + gcgdb * vbd + gcgsb * vbs;
3196 ceqqb = cqbulk - gcbgb * vgb + gcbdb * vbd + gcbsb * vbs;
3197 ceqqd = cqdrn - gcdgb * vgb + gcddb * vbd + gcdsb * vbs;
3198
3199 if (here->BSIM3v32nqsMod)
3200 { T0 = ggtg * vgb - ggtd * vbd - ggts * vbs;
3201 ceqqg += T0;
3202 T1 = qdef * here->BSIM3v32gtau;
3203 ceqqd -= dxpart * T0 + T1 * (ddxpart_dVg * vgb - ddxpart_dVd
3204 * vbd - ddxpart_dVs * vbs);
3205 cqdef = *(ckt->CKTstate0 + here->BSIM3v32cqcdump) - gqdef * qdef;
3206 cqcheq = *(ckt->CKTstate0 + here->BSIM3v32cqcheq)
3207 - (gcqgb * vgb - gcqdb * vbd - gcqsb * vbs) + T0;
3208 }
3209
3210 if (ckt->CKTmode & MODEINITTRAN)
3211 { *(ckt->CKTstate1 + here->BSIM3v32cqb) =
3212 *(ckt->CKTstate0 + here->BSIM3v32cqb);
3213 *(ckt->CKTstate1 + here->BSIM3v32cqg) =
3214 *(ckt->CKTstate0 + here->BSIM3v32cqg);
3215 *(ckt->CKTstate1 + here->BSIM3v32cqd) =
3216 *(ckt->CKTstate0 + here->BSIM3v32cqd);
3217
3218 if (here->BSIM3v32nqsMod)
3219 { *(ckt->CKTstate1 + here->BSIM3v32cqcheq) =
3220 *(ckt->CKTstate0 + here->BSIM3v32cqcheq);
3221 *(ckt->CKTstate1 + here->BSIM3v32cqcdump) =
3222 *(ckt->CKTstate0 + here->BSIM3v32cqcdump);
3223 }
3224 }
3225
3226 /*
3227 * load current vector
3228 */
3229 line900:
3230
3231 if (here->BSIM3v32mode >= 0)
3232 { Gm = here->BSIM3v32gm;
3233 Gmbs = here->BSIM3v32gmbs;
3234 FwdSum = Gm + Gmbs;
3235 RevSum = 0.0;
3236 cdreq = model->BSIM3v32type * (cdrain - here->BSIM3v32gds * vds
3237 - Gm * vgs - Gmbs * vbs);
3238
3239 ceqbd = -model->BSIM3v32type * (here->BSIM3v32csub
3240 - here->BSIM3v32gbds * vds - here->BSIM3v32gbgs * vgs
3241 - here->BSIM3v32gbbs * vbs);
3242 ceqbs = 0.0;
3243
3244 gbbdp = -here->BSIM3v32gbds;
3245 gbbsp = (here->BSIM3v32gbds + here->BSIM3v32gbgs + here->BSIM3v32gbbs);
3246
3247 gbdpg = here->BSIM3v32gbgs;
3248 gbdpdp = here->BSIM3v32gbds;
3249 gbdpb = here->BSIM3v32gbbs;
3250 gbdpsp = -(gbdpg + gbdpdp + gbdpb);
3251
3252 gbspg = 0.0;
3253 gbspdp = 0.0;
3254 gbspb = 0.0;
3255 gbspsp = 0.0;
3256 }
3257 else
3258 { Gm = -here->BSIM3v32gm;
3259 Gmbs = -here->BSIM3v32gmbs;
3260 FwdSum = 0.0;
3261 RevSum = -(Gm + Gmbs);
3262 cdreq = -model->BSIM3v32type * (cdrain + here->BSIM3v32gds * vds
3263 + Gm * vgd + Gmbs * vbd);
3264
3265 ceqbs = -model->BSIM3v32type * (here->BSIM3v32csub
3266 + here->BSIM3v32gbds * vds - here->BSIM3v32gbgs * vgd
3267 - here->BSIM3v32gbbs * vbd);
3268 ceqbd = 0.0;
3269
3270 gbbsp = -here->BSIM3v32gbds;
3271 gbbdp = (here->BSIM3v32gbds + here->BSIM3v32gbgs + here->BSIM3v32gbbs);
3272
3273 gbdpg = 0.0;
3274 gbdpsp = 0.0;
3275 gbdpb = 0.0;
3276 gbdpdp = 0.0;
3277
3278 gbspg = here->BSIM3v32gbgs;
3279 gbspsp = here->BSIM3v32gbds;
3280 gbspb = here->BSIM3v32gbbs;
3281 gbspdp = -(gbspg + gbspsp + gbspb);
3282 }
3283
3284 if (model->BSIM3v32type > 0)
3285 { ceqbs += (here->BSIM3v32cbs - here->BSIM3v32gbs * vbs);
3286 ceqbd += (here->BSIM3v32cbd - here->BSIM3v32gbd * vbd);
3287 /*
3288 ceqqg = ceqqg;
3289 ceqqb = ceqqb;
3290 ceqqd = ceqqd;
3291 cqdef = cqdef;
3292 cqcheq = cqcheq;
3293 */
3294 }
3295 else
3296 { ceqbs -= (here->BSIM3v32cbs - here->BSIM3v32gbs * vbs);
3297 ceqbd -= (here->BSIM3v32cbd - here->BSIM3v32gbd * vbd);
3298 ceqqg = -ceqqg;
3299 ceqqb = -ceqqb;
3300 ceqqd = -ceqqd;
3301 cqdef = -cqdef;
3302 cqcheq = -cqcheq;
3303 }
3304
3305 m = here->BSIM3v32m;
3306
3307 #ifdef USE_OMP
3308 here->BSIM3v32rhsG = m * ceqqg;
3309 here->BSIM3v32rhsB = m * (ceqbs + ceqbd + ceqqb);
3310 here->BSIM3v32rhsD = m * (ceqbd - cdreq - ceqqd);
3311 here->BSIM3v32rhsS = m * (cdreq + ceqbs + ceqqg
3312 + ceqqb + ceqqd);
3313 if (here->BSIM3v32nqsMod)
3314 here->BSIM3v32rhsQ = m * (cqcheq - cqdef);
3315 #else
3316 (*(ckt->CKTrhs + here->BSIM3v32gNode) -= m * ceqqg);
3317 (*(ckt->CKTrhs + here->BSIM3v32bNode) -= m * (ceqbs + ceqbd + ceqqb));
3318 (*(ckt->CKTrhs + here->BSIM3v32dNodePrime) += m * (ceqbd - cdreq - ceqqd));
3319 (*(ckt->CKTrhs + here->BSIM3v32sNodePrime) += m * (cdreq + ceqbs + ceqqg
3320 + ceqqb + ceqqd));
3321 if (here->BSIM3v32nqsMod)
3322 *(ckt->CKTrhs + here->BSIM3v32qNode) += m * (cqcheq - cqdef);
3323 #endif
3324
3325 /*
3326 * load y matrix
3327 */
3328
3329 T1 = qdef * here->BSIM3v32gtau;
3330 #ifdef USE_OMP
3331 here->BSIM3v32DdPt = m * here->BSIM3v32drainConductance;
3332 here->BSIM3v32GgPt = m * (gcggb - ggtg);
3333 here->BSIM3v32SsPt = m * here->BSIM3v32sourceConductance;
3334 here->BSIM3v32BbPt = m * (here->BSIM3v32gbd + here->BSIM3v32gbs
3335 - gcbgb - gcbdb - gcbsb - here->BSIM3v32gbbs);
3336 here->BSIM3v32DPdpPt = m * (here->BSIM3v32drainConductance
3337 + here->BSIM3v32gds + here->BSIM3v32gbd
3338 + RevSum + gcddb + dxpart * ggtd
3339 + T1 * ddxpart_dVd + gbdpdp);
3340 here->BSIM3v32SPspPt = m * (here->BSIM3v32sourceConductance
3341 + here->BSIM3v32gds + here->BSIM3v32gbs
3342 + FwdSum + gcssb + sxpart * ggts
3343 + T1 * dsxpart_dVs + gbspsp);
3344 here->BSIM3v32DdpPt = m * here->BSIM3v32drainConductance;
3345 here->BSIM3v32GbPt = m * (gcggb + gcgdb + gcgsb + ggtb);
3346 here->BSIM3v32GdpPt = m * (gcgdb - ggtd);
3347 here->BSIM3v32GspPt = m * (gcgsb - ggts);
3348 here->BSIM3v32SspPt = m * here->BSIM3v32sourceConductance;
3349 here->BSIM3v32BgPt = m * (gcbgb - here->BSIM3v32gbgs);
3350 here->BSIM3v32BdpPt = m * (gcbdb - here->BSIM3v32gbd + gbbdp);
3351 here->BSIM3v32BspPt = m * (gcbsb - here->BSIM3v32gbs + gbbsp);
3352 here->BSIM3v32DPdPt = m * here->BSIM3v32drainConductance;
3353 here->BSIM3v32DPgPt = m * (Gm + gcdgb + dxpart * ggtg
3354 + T1 * ddxpart_dVg + gbdpg);
3355 here->BSIM3v32DPbPt = m * (here->BSIM3v32gbd - Gmbs + gcdgb + gcddb
3356 + gcdsb - dxpart * ggtb
3357 - T1 * ddxpart_dVb - gbdpb);
3358 here->BSIM3v32DPspPt = m * (here->BSIM3v32gds + FwdSum - gcdsb
3359 - dxpart * ggts - T1 * ddxpart_dVs - gbdpsp);
3360 here->BSIM3v32SPgPt = m * (gcsgb - Gm + sxpart * ggtg
3361 + T1 * dsxpart_dVg + gbspg);
3362 here->BSIM3v32SPsPt = m * here->BSIM3v32sourceConductance;
3363 here->BSIM3v32SPbPt = m * (here->BSIM3v32gbs + Gmbs + gcsgb + gcsdb
3364 + gcssb - sxpart * ggtb
3365 - T1 * dsxpart_dVb - gbspb);
3366 here->BSIM3v32SPdpPt = m * (here->BSIM3v32gds + RevSum - gcsdb
3367 - sxpart * ggtd - T1 * dsxpart_dVd - gbspdp);
3368
3369 if (here->BSIM3v32nqsMod)
3370 {
3371 here->BSIM3v32QqPt = m * (gqdef + here->BSIM3v32gtau);
3372
3373 here->BSIM3v32DPqPt = m * (dxpart * here->BSIM3v32gtau);
3374 here->BSIM3v32SPqPt = m * (sxpart * here->BSIM3v32gtau);
3375 here->BSIM3v32GqPt = m * here->BSIM3v32gtau;
3376
3377 here->BSIM3v32QgPt = m * (ggtg - gcqgb);
3378 here->BSIM3v32QdpPt = m * (ggtd - gcqdb);
3379 here->BSIM3v32QspPt = m * (ggts - gcqsb);
3380 here->BSIM3v32QbPt = m * (ggtb - gcqbb);
3381 }
3382 #else
3383 (*(here->BSIM3v32DdPtr) += m * here->BSIM3v32drainConductance);
3384 (*(here->BSIM3v32GgPtr) += m * (gcggb - ggtg));
3385 (*(here->BSIM3v32SsPtr) += m * here->BSIM3v32sourceConductance);
3386 (*(here->BSIM3v32BbPtr) += m * (here->BSIM3v32gbd + here->BSIM3v32gbs
3387 - gcbgb - gcbdb - gcbsb - here->BSIM3v32gbbs));
3388 (*(here->BSIM3v32DPdpPtr) += m * (here->BSIM3v32drainConductance
3389 + here->BSIM3v32gds + here->BSIM3v32gbd
3390 + RevSum + gcddb + dxpart * ggtd
3391 + T1 * ddxpart_dVd + gbdpdp));
3392 (*(here->BSIM3v32SPspPtr) += m * (here->BSIM3v32sourceConductance
3393 + here->BSIM3v32gds + here->BSIM3v32gbs
3394 + FwdSum + gcssb + sxpart * ggts
3395 + T1 * dsxpart_dVs + gbspsp));
3396 (*(here->BSIM3v32DdpPtr) -= m * here->BSIM3v32drainConductance);
3397 (*(here->BSIM3v32GbPtr) -= m * (gcggb + gcgdb + gcgsb + ggtb));
3398 (*(here->BSIM3v32GdpPtr) += m * (gcgdb - ggtd));
3399 (*(here->BSIM3v32GspPtr) += m * (gcgsb - ggts));
3400 (*(here->BSIM3v32SspPtr) -= m * here->BSIM3v32sourceConductance);
3401 (*(here->BSIM3v32BgPtr) += m * (gcbgb - here->BSIM3v32gbgs));
3402 (*(here->BSIM3v32BdpPtr) += m * (gcbdb - here->BSIM3v32gbd + gbbdp));
3403 (*(here->BSIM3v32BspPtr) += m * (gcbsb - here->BSIM3v32gbs + gbbsp));
3404 (*(here->BSIM3v32DPdPtr) -= m * here->BSIM3v32drainConductance);
3405 (*(here->BSIM3v32DPgPtr) += m * (Gm + gcdgb + dxpart * ggtg
3406 + T1 * ddxpart_dVg + gbdpg));
3407 (*(here->BSIM3v32DPbPtr) -= m * (here->BSIM3v32gbd - Gmbs + gcdgb + gcddb
3408 + gcdsb - dxpart * ggtb
3409 - T1 * ddxpart_dVb - gbdpb));
3410 (*(here->BSIM3v32DPspPtr) -= m * (here->BSIM3v32gds + FwdSum - gcdsb
3411 - dxpart * ggts - T1 * ddxpart_dVs - gbdpsp));
3412 (*(here->BSIM3v32SPgPtr) += m * (gcsgb - Gm + sxpart * ggtg
3413 + T1 * dsxpart_dVg + gbspg));
3414 (*(here->BSIM3v32SPsPtr) -= m * here->BSIM3v32sourceConductance);
3415 (*(here->BSIM3v32SPbPtr) -= m * (here->BSIM3v32gbs + Gmbs + gcsgb + gcsdb
3416 + gcssb - sxpart * ggtb
3417 - T1 * dsxpart_dVb - gbspb));
3418 (*(here->BSIM3v32SPdpPtr) -= m * (here->BSIM3v32gds + RevSum - gcsdb
3419 - sxpart * ggtd - T1 * dsxpart_dVd - gbspdp));
3420
3421 if (here->BSIM3v32nqsMod)
3422 {
3423 *(here->BSIM3v32QqPtr) += m * (gqdef + here->BSIM3v32gtau);
3424
3425 *(here->BSIM3v32DPqPtr) += m * (dxpart * here->BSIM3v32gtau);
3426 *(here->BSIM3v32SPqPtr) += m * (sxpart * here->BSIM3v32gtau);
3427 *(here->BSIM3v32GqPtr) -= m * here->BSIM3v32gtau;
3428
3429 *(here->BSIM3v32QgPtr) += m * (ggtg - gcqgb);
3430 *(here->BSIM3v32QdpPtr) += m * (ggtd - gcqdb);
3431 *(here->BSIM3v32QspPtr) += m * (ggts - gcqsb);
3432 *(here->BSIM3v32QbPtr) += m * (ggtb - gcqbb);
3433 }
3434 #endif
3435
3436 line1000: ;
3437
3438 #ifndef USE_OMP
3439 } /* End of Mosfet Instance */
3440 } /* End of Model Instance */
3441 #endif
3442
3443 return(OK);
3444 }
3445
3446 #ifdef USE_OMP
BSIM3v32LoadRhsMat(GENmodel * inModel,CKTcircuit * ckt)3447 void BSIM3v32LoadRhsMat(GENmodel *inModel, CKTcircuit *ckt)
3448 {
3449 int InstCount, idx;
3450 BSIM3v32instance **InstArray;
3451 BSIM3v32instance *here;
3452 BSIM3v32model *model = (BSIM3v32model*)inModel;
3453
3454 InstArray = model->BSIM3v32InstanceArray;
3455 InstCount = model->BSIM3v32InstCount;
3456
3457 for (idx = 0; idx < InstCount; idx++) {
3458 here = InstArray[idx];
3459 model = BSIM3v32modPtr(here);
3460 /* Update b for Ax = b */
3461 (*(ckt->CKTrhs + here->BSIM3v32gNode) -= here->BSIM3v32rhsG);
3462 (*(ckt->CKTrhs + here->BSIM3v32bNode) -= here->BSIM3v32rhsB);
3463 (*(ckt->CKTrhs + here->BSIM3v32dNodePrime) += here->BSIM3v32rhsD);
3464 (*(ckt->CKTrhs + here->BSIM3v32sNodePrime) += here->BSIM3v32rhsS);
3465 if (here->BSIM3v32nqsMod)
3466 (*(ckt->CKTrhs + here->BSIM3v32qNode) += here->BSIM3v32rhsQ);
3467
3468 /* Update A for Ax = b */
3469 (*(here->BSIM3v32DdPtr) += here->BSIM3v32DdPt);
3470 (*(here->BSIM3v32GgPtr) += here->BSIM3v32GgPt);
3471 (*(here->BSIM3v32SsPtr) += here->BSIM3v32SsPt);
3472 (*(here->BSIM3v32BbPtr) += here->BSIM3v32BbPt);
3473 (*(here->BSIM3v32DPdpPtr) += here->BSIM3v32DPdpPt);
3474 (*(here->BSIM3v32SPspPtr) += here->BSIM3v32SPspPt);
3475 (*(here->BSIM3v32DdpPtr) -= here->BSIM3v32DdpPt);
3476 (*(here->BSIM3v32GbPtr) -= here->BSIM3v32GbPt);
3477 (*(here->BSIM3v32GdpPtr) += here->BSIM3v32GdpPt);
3478 (*(here->BSIM3v32GspPtr) += here->BSIM3v32GspPt);
3479 (*(here->BSIM3v32SspPtr) -= here->BSIM3v32SspPt);
3480 (*(here->BSIM3v32BgPtr) += here->BSIM3v32BgPt);
3481 (*(here->BSIM3v32BdpPtr) += here->BSIM3v32BdpPt);
3482 (*(here->BSIM3v32BspPtr) += here->BSIM3v32BspPt);
3483 (*(here->BSIM3v32DPdPtr) -= here->BSIM3v32DPdPt);
3484 (*(here->BSIM3v32DPgPtr) += here->BSIM3v32DPgPt);
3485 (*(here->BSIM3v32DPbPtr) -= here->BSIM3v32DPbPt);
3486 (*(here->BSIM3v32DPspPtr) -= here->BSIM3v32DPspPt);
3487 (*(here->BSIM3v32SPgPtr) += here->BSIM3v32SPgPt);
3488 (*(here->BSIM3v32SPsPtr) -= here->BSIM3v32SPsPt);
3489 (*(here->BSIM3v32SPbPtr) -= here->BSIM3v32SPbPt);
3490 (*(here->BSIM3v32SPdpPtr) -= here->BSIM3v32SPdpPt);
3491
3492 if (here->BSIM3v32nqsMod)
3493 {
3494 *(here->BSIM3v32QqPtr) += here->BSIM3v32QqPt;
3495
3496 *(here->BSIM3v32DPqPtr) += here->BSIM3v32DPqPt;
3497 *(here->BSIM3v32SPqPtr) += here->BSIM3v32SPqPt;
3498 *(here->BSIM3v32GqPtr) -= here->BSIM3v32GqPt;
3499
3500 *(here->BSIM3v32QgPtr) += here->BSIM3v32QgPt;
3501 *(here->BSIM3v32QdpPtr) += here->BSIM3v32QdpPt;
3502 *(here->BSIM3v32QspPtr) += here->BSIM3v32QspPt;
3503 *(here->BSIM3v32QbPtr) += here->BSIM3v32QbPt;
3504 }
3505
3506 }
3507 }
3508 #endif
3509